| /freebsd/sys/contrib/device-tree/Bindings/net/ |
| H A D | amd-xgbe.txt | 1 * AMD 10GbE driver (amd-xgbe)
4 - compatible: Should be "amd,xgbe-seattle-v1a"
5 - reg: Address and length of the register sets for the device
6 - MAC registers
7 - PCS registers
8 - SerDes Rx/Tx registers
9 - SerDes integration registers (1/2)
10 - SerDes integration registers (2/2)
11 - interrupts: Should contain the amd-xgbe interrupt(s). The first interrupt
12 listed is required and is the general device interrupt. If the optional
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| /freebsd/sys/contrib/device-tree/Bindings/dma/ |
| H A D | ti-edma.txt | 3 The eDMA3 consists of two components: Channel controller (CC) and Transfer
5 responsible for the DMA channel handling, while the TCs are responsible to
8 ------------------------------------------------------------------------------
9 eDMA3 Channel Controller
12 --------------------
13 - compatible: Should be:
14 - "ti,edma3-tpcc" for the channel controller(s) on OMAP,
16 - "ti,k2g-edma3-tpcc", "ti,edma3-tpcc" for the
17 channel controller(s) on 66AK2G.
18 - #dma-cells: Should be set to <2>. The first number is the DMA request
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| H A D | fsl-edma.txt | 3 The eDMA channels have multiplex capability by programmble memory-mapped
5 specific DMA request source can only be multiplexed by any channel of certain
10 - compatible :
11 - "fsl,vf610-edma" for eDMA used similar to that on Vybrid vf610 SoC
12 - "fsl,imx7ulp-edma" for eDMA2 used similar to that on i.mx7ulp
13 - "fsl,ls1028a-edma" followed by "fsl,vf610-edma" for eDMA used on the
15 - reg : Specifies base physical address(s) and size of the eDMA registers.
17 The 2nd and the 3rd regions are programmable channel multiplexing
19 - interrupts : A list of interrupt-specifiers, one for each entry in
20 interrupt-names on vf610 similar SoC. But for i.mx7ulp per channel
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| H A D | snps-dma.txt | 4 - compatible: "snps,dma-spear1340"
5 - reg: Address range of the DMAC registers
6 - interrupt: Should contain the DMAC interrupt number
7 - dma-channels: Number of channels supported by hardware
8 - dma-requests: Number of DMA request lines supported, up to 16
9 - dma-masters: Number of AHB masters supported by the controller
10 - #dma-cells: must be <3>
11 - chan_allocation_order: order of allocation of channel, 0 (default): ascending,
13 - chan_priority: priority of channels. 0 (default): increase from chan 0->n, 1:
14 increase from chan n->0
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| H A D | mmp-dma.txt | 7 - compatible: Should be "marvell,pdma-1.0"
8 - reg: Should contain DMA registers location and length.
9 - interrupts: Either contain all of the per-channel DMA interrupts
13 - dma-channels: Number of DMA channels supported by the controller (defaults
15 - #dma-channels: deprecated
16 - dma-requests: Number of DMA requestor lines supported by the controller
18 - #dma-requests: deprecated
20 "marvell,pdma-1.0"
26 * Each channel has specific irq
27 * ICU parse out irq channel from ICU register,
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| H A D | fsl,elo-dma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/fsl,elo-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - J. Neuschäfer <j.ne@posteo.net>
13 This is a little-endian 4-channel DMA controller, used in Freescale mpc83xx
19 - enum:
20 - fsl,mpc8313-dma
21 - fsl,mpc8315-dma
22 - fsl,mpc8323-dma
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| H A D | fsl,eloplus-dma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/fsl,eloplus-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - J. Neuschäfer <j.ne@posteo.net>
13 This is a 4-channel DMA controller with extended addresses and chaining,
20 - items:
21 - enum:
22 - fsl,mpc8540-dma
23 - fsl,mpc8541-dma
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| H A D | fsl,elo3-dma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/fsl,elo3-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - J. Neuschäfer <j.ne@posteo.net>
19 const: fsl,elo3-dma
23 - description:
24 DMA General Status Registers starting from DGSR0, for channel 1~4
25 - description:
26 DMA General Status Registers starting from DGSR1, for channel 5~8
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| H A D | snps,dw-axi-dmac.txt | 4 - compatible: "snps,axi-dma-1.01a"
5 - reg: Address range of the DMAC registers. This should include
6 all of the per-channel registers.
7 - interrupt: Should contain the DMAC interrupt number.
8 - dma-channels: Number of channels supported by hardware.
9 - snps,dma-masters: Number of AXI masters supported by the hardware.
10 - snps,data-width: Maximum AXI data width supported by hardware.
11 (0 - 8bits, 1 - 16bits, 2 - 32bits, ..., 6 - 512bits)
12 - snps,priority: Priority of channel. Array size is equal to the number of
13 dma-channels. Priority value must be programmed within [0:dma-channels-1]
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| /freebsd/sys/contrib/device-tree/Bindings/spmi/ |
| H A D | qcom,spmi-pmic-arb.txt | 4 controller with wrapping arbitration logic to allow for multiple on-chip
7 The PMIC Arbiter can also act as an interrupt controller, providing interrupts
13 See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt for
14 generic interrupt controller binding documentation.
17 - compatible : should be "qcom,spmi-pmic-arb".
18 - reg-names : must contain:
19 "core" - core registers
20 "intr" - interrupt controller registers
21 "cnfg" - configuration registers
23 "chnls" - tx-channel per virtual slave registers.
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| H A D | qcom,spmi-pmic-arb.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/spmi/qcom,spmi-pmic-arb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Stephen Boyd <sboyd@kernel.org>
14 controller with wrapping arbitration logic to allow for multiple on-chip
17 The PMIC Arbiter can also act as an interrupt controller, providing interrupts
21 - $ref: spmi.yaml
25 const: qcom,spmi-pmic-arb
29 - items: # V1
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| H A D | qcom,x1e80100-spmi-pmic-arb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spmi/qcom,x1e80100-spmi-pmic-arb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Stephen Boyd <sboyd@kernel.org>
14 controller with wrapping arbitration logic to allow for multiple on-chip
17 The PMIC Arbiter can also act as an interrupt controller, providing interrupts
23 - items:
24 - const: qcom,sar2130p-spmi-pmic-arb
25 - const: qcom,x1e80100-spmi-pmic-arb
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| /freebsd/sys/contrib/device-tree/Bindings/net/wireless/ |
| H A D | mediatek,mt76.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Felix Fietkau <nbd@nbd.name>
12 - Lorenzo Bianconi <lorenzo@kernel.org>
13 - Ryder Lee <ryder.lee@mediatek.com>
25 - mediatek,mt76
26 - mediatek,mt7628-wmac
27 - mediatek,mt7622-wmac
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| /freebsd/sys/contrib/device-tree/Bindings/mfd/ |
| H A D | atmel-tcb.txt | 2 - compatible: Should be "atmel,<chip>-tcb", "simple-mfd", "syscon".
4 - reg: Should contain registers location and length
5 - #address-cells: has to be 1
6 - #size-cells: has to be 0
7 - interrupts: Should contain all interrupts for the TC block
8 Note that you can specify several interrupt cells if the TC
9 block has one interrupt per channel.
10 - clock-names: tuple listing input clock names.
13 - clocks: phandles to input clocks.
17 - compatible: Should be "atmel,tcb-timer"
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| /freebsd/sys/dev/xen/bus/ |
| H A D | xen_intr.c | 4 * Xen event and interrupt services for x86 HVM guests.
6 * Copyright (c) 2002-2005, K A Fraser
9 * Copyright © 2021-2023, Elliott Mitchell
43 #include <sys/interrupt.h>
55 #include <xen/xen-os.h>
60 #include <machine/xen/arch-intr.h>
67 * Per-cpu event channel processing state.
71 * The last event channel bitmap section (level one bit) processed.
78 * The last event channel processed within the event channel
85 * A set bit means interrupt handling is enabled.
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| /freebsd/sys/contrib/device-tree/Bindings/sound/ |
| H A D | img,i2s-in.txt | 5 - compatible : Compatible list, must contain "img,i2s-in"
7 - #sound-dai-cells : Must be equal to 0
9 - reg : Offset and length of the register set for the device
11 - clocks : Contains an entry for each entry in clock-names
13 - clock-names : Must include the following entry:
16 - dmas: Contains an entry for each entry in dma-names.
18 - dma-names: Must include the following entry:
19 "rx" Single DMA channel used by all active I2S channels
21 - img,i2s-channels : Number of I2S channels instantiated in the I2S in block
25 - interrupts : Contains the I2S in interrupts. Depending on
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| H A D | img,i2s-out.txt | 5 - compatible : Compatible list, must contain "img,i2s-out"
7 - #sound-dai-cells : Must be equal to 0
9 - reg : Offset and length of the register set for the device
11 - clocks : Contains an entry for each entry in clock-names
13 - clock-names : Must include the following entries:
17 - dmas: Contains an entry for each entry in dma-names.
19 - dma-names: Must include the following entry:
20 "tx" Single DMA channel used by all active I2S channels
22 - img,i2s-channels : Number of I2S channels instantiated in the I2S out block
24 - resets: Contains a phandle to the I2S out reset signal
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| /freebsd/sys/contrib/device-tree/Bindings/soc/microchip/ |
| H A D | atmel,at91rm9200-tcb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/microchip/atmel,at91rm9200-tcb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandre Belloni <alexandre.belloni@bootlin.com>
19 - items:
20 - enum:
21 - atmel,at91rm9200-tcb
22 - atmel,at91sam9x5-tcb
23 - atmel,sama5d2-tcb
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| /freebsd/sys/contrib/device-tree/Bindings/mailbox/ |
| H A D | arm,mhuv3.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sudeep Holla <sudeep.holla@arm.com>
11 - Cristian Marussi <cristian.marussi@arm.com>
27 - Configure the MHU
28 - Send Transfers to the Receiver
29 - Optionally receive acknowledgment of a Transfer from the Receiver
32 - Configure the MHU
33 - Receive Transfers from the Sender
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| /freebsd/share/man/man4/ |
| H A D | ioat.4 | 34 .Bd -ragged -offset indent
40 .Bd -literal -offset indent
145 There is a number of DMA channels per CPU package.
148 Operations on a single channel proceed sequentially.
150 Blockfill operations can be used to write a 64-bit pattern to memory.
154 Null operations do nothing, but may be used to test the interrupt and callback
157 All operations can optionally trigger an interrupt at completion with the
160 For example, a user might submit multiple operations to the same channel and
161 only enable an interrupt and callback for the last operation.
163 The hardware can delay and coalesce interrupts on a given channel for a
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| /freebsd/sys/contrib/device-tree/Bindings/gpio/ |
| H A D | gpio-xilinx.txt | 3 Dual channel GPIO controller with configurable number of pins
4 (from 1 to 32 per channel). Every pin can be configured as
6 local interrupts can be enabled on channel basis.
9 - compatible : Should be "xlnx,xps-gpio-1.00.a"
10 - reg : Address and length of the register set for the device
11 - #gpio-cells : Should be two. The first cell is the pin number and the
13 - gpio-controller : Marks the device node as a GPIO controller.
16 - clocks : Input clock specifier. Refer to common clock bindings.
17 - interrupts : Interrupt mapping for GPIO IRQ.
18 - xlnx,all-inputs : if n-th bit is setup, GPIO-n is input
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| /freebsd/sys/contrib/device-tree/Bindings/iio/adc/ |
| H A D | st,stm32-adc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/st,stm32-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 STM32 ADC is a successive approximation analog-to-digital converter.
13 stored in a left-aligned or right-aligned 32-bit data register.
17 voltage goes beyond the user-defined, higher or lower thresholds.
22 - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
27 - st,stm32f4-adc-core
28 - st,stm32h7-adc-core
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| /freebsd/sys/arm/ti/ |
| H A D | ti_sdma.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
35 #include <sys/interrupt.h>
73 * Data structure per DMA channel.
79 * The configuration registers for the given channel, these are modified
90 /* Callback function used when an interrupt is tripped on the given channel */
109 * I guess in theory we should have a mutex per DMA channel for register
119 * Bits in the sc_active_channels data field indicate if the channel has
133 #define TI_SDMA_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx)
134 #define TI_SDMA_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx)
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| /freebsd/sys/contrib/device-tree/Bindings/spi/ |
| H A D | spi-fsl-lpspi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-fsl-lpspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawnguo@kernel.org>
11 - Sascha Hauer <s.hauer@pengutronix.de>
12 - Fabio Estevam <festevam@gmail.com>
15 - $ref: /schemas/spi/spi-controller.yaml#
20 - enum:
21 - fsl,imx7ulp-spi
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| /freebsd/sys/contrib/device-tree/Bindings/pwm/ |
| H A D | renesas,rzg2l-gpt.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pwm/renesas,rzg2l-gpt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Biju Das <biju.das.jz@bp.renesas.com>
13 RZ/G2L General PWM Timer (GPT) composed of 8 channels with 32-bit timer
16 * Up-counting or down-counting (saw waves) or up/down-counting
18 * Clock sources independently selectable for each channel.
19 * Two I/O pins per channel.
20 * Two output compare/input capture registers per channel.
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