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Searched +full:per +full:- +full:vpe (Results 1 – 17 of 17) sorted by relevance

/linux/include/linux/irqchip/
H A Darm-gic-v4.h1 /* SPDX-License-Identifier: GPL-2.0-only */
14 * ITSList mechanism to perform inter-ITS synchronization.
33 * vmapp_lock -> vpe_lock ->vmovp_lock.
43 /* per-vPE VLPI tracking */
48 /* VPE resident */
55 /* VPE proxy mapping */
72 /* Track the VPE being mapped */
77 * vPE and vLPI operations using vpe->col_idx.
82 * redistributor for this VPE. The ID itself isn't involved in
86 /* Unique (system-wide) VPE identifier */
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/linux/Documentation/devicetree/bindings/timer/
H A Deconet,en751221-timer.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/econet,en751221-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Caleb James DeLisle <cjd@cjdns.fr>
14 EcoNet SoCs, including the EN751221 and EN751627 families. It provides per-VPE
15 count/compare registers and a per-CPU control register, with a single interrupt
16 line using a percpu-devid interrupt mechanism.
21 - const: econet,en751221-timer
22 - items:
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/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Deconet,en751221-intc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/econet,en751221-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Caleb James DeLisle <cjd@cjdns.fr>
15 be routed to either VPE but not both, so to support per-CPU interrupts, a
16 secondary IRQ number is allocated to control masking/unmasking on VPE#1. For
22 - $ref: /schemas/interrupt-controller.yaml#
26 const: econet,en751221-intc
31 "#interrupt-cells":
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/linux/drivers/irqchip/
H A Dirq-econet-en751221.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * be routed to either VPE but not both, so to support per-CPU interrupts, a
8 * secondary IRQ number is allocated to control masking/unmasking on VPE#1. In
13 * If an interrupt (say 30) needs per-CPU capability, the SoC integrator
15 * reflects this by adding the pair <30 29> to the "econet,shadow-interrupts"
18 * When VPE#1 requests IRQ 30, the driver manipulates the mask bit for IRQ 29,
19 * telling the hardware to mask VPE#1's view of IRQ 30.
46 * - NOT_PERCPU: This interrupt is not per-cpu, so it has no shadow
47 * - IS_SHADOW: This interrupt is a shadow of another per-cpu interrupt
48 * - else: This is a per-cpu interrupt whose shadow is the value
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H A Dirq-gic-v3-its.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved.
37 #include <linux/irqchip/arm-gic-v3.h>
38 #include <linux/irqchip/arm-gic-v4.h>
43 #include "irq-gic-common.h"
44 #include "irq-gic-its-msi-parent.h"
45 #include <linux/irqchip/irq-msi-lib.h>
61 * deal with (one configuration byte per interrupt). PENDBASE has to
62 * be 64kB aligned (one bit per LPI, plus 8192 bits for SPI/PPI/SGI).
72 * Collection structure - just an ID, and a redistributor address to
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/linux/arch/mips/include/asm/
H A Dmipsmtregs.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 * Copyright (C) 2004 - 2005 MIPS Technologies, Inc. All rights reserved.
103 /* VPEControl fields (per VPE) */
124 /* VPEConf0 fields (per VPE) */
132 /* VPEConf1 fields (per VPE) */
140 /* TCStatus fields (per TC) */
289 /* enable multi-threaded execution if previous suggested it should be.
/linux/arch/mips/kernel/
H A Dsmp-cps.c1 // SPDX-License-Identifier: GPL-2.0-or-later
19 #include <asm/mips-cps.h>
22 #include <asm/pm-cps.h>
26 #include <asm/smp-cps.h>
78 timeout--; in power_up_other_cluster()
159 0x0, CSEGX_SIZE - 1); in allocate_cps_vecs()
172 end = SZ_4G - 1; in allocate_cps_vecs()
186 return -ENOMEM; in allocate_cps_vecs()
216 /* Detect & record VPE topology */ in cps_smp_setup()
219 pr_info("%s topology ", cpu_has_mips_r6 ? "VP" : "VPE"); in cps_smp_setup()
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H A Dcpu-probe.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright (C) 1994 - 2006 Ralf Baechle
20 #include <asm/cpu-features.h>
21 #include <asm/cpu-type.h>
28 #include <asm/pgtable-bits.h>
33 #include "fpu-probe.h"
35 #include <asm/mach-loongson64/cpucfg-emul.h>
134 cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways * in ftlb_disable()
145 * Check if the CPU has per tc perf counters
150 c->options |= MIPS_CPU_MT_PER_TC_PERF_COUNTERS; in cpu_set_mt_per_tc_perf()
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H A Dsmp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
34 #include <asm/r4k-timer.h>
35 #include <asm/mips-cps.h>
47 /* Number of TCs (or siblings in Intel speak) per CPU core */
55 /* representing the core map of multi-core chips of each logical CPU */
65 * A logical cpu mask containing only one VPE per core to
144 /* Re-calculate the mask */ in calculate_cpu_foreign_map()
365 mp_ops->init_secondary(); in start_secondary()
407 * irq will be enabled in ->smp_finish(), enabling it too early in start_secondary()
411 mp_ops->smp_finish(); in start_secondary()
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/linux/include/kvm/
H A Darm_vgic.h1 /* SPDX-License-Identifier: GPL-2.0-only */
21 #include <linux/irqchip/arm-gic-v4.h>
32 #define KVM_IRQCHIP_NUM_PINS (1020 - 32)
94 #define VGIC_V3_LR_INDEX(lr) (VGIC_V3_MAX_LRS - 1 - lr)
102 * Per-irq ops overriding some common behavious.
104 * Always called in non-preemptible section and the functions can use
108 /* Per interrupt flags for special-cased interrupts */
114 * Callback function pointer to in-kernel devices that can tell us the
115 * state of the input level of mapped level-triggered IRQ faster than
164 for in-kernel devices. */
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/linux/drivers/bus/
H A Domap_l3_noc.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2011-2015 Texas Instruments Incorporated - http://www.ti.com/
44 /* 1 0 1 */ "Write Non-Posted",
50 * struct l3_masters_data - L3 Master information
60 * struct l3_target_data - L3 Target information
72 * struct l3_flagmux_data - Flag Mux information
91 * struct omap_l3 - Description of data relevant for L3 bus.
96 * @l3_flag_mux: array containing flag mux data per module
97 * offset from corresponding module base indexed per
368 { 0x27, "VPE" },
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/linux/arch/loongarch/kernel/
H A Dsmp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
53 /* Representing the core map of multi-core chips of each logical CPU */
61 * A logcal cpu mask containing only one VPE per core to
91 seq_printf(p, "%*s%u:%s", prec - 1, "IPI", i, prec >= 4 ? " " : ""); in show_ipi_list()
177 /* Re-calculate the mask */ in calculate_cpu_foreign_map()
437 return -EBUSY; in loongson_cpu_disable()
588 * cpus will be added by cpu-hotplug later), for possible but in smp_prepare_boot_cpu()
590 * and we just map them to online nodes in round-robin way. in smp_prepare_boot_cpu()
608 current_thread_info()->cpu = 0; in smp_prepare_cpus()
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/linux/arch/arm64/kvm/vgic/
H A Dvgic-its.c1 // SPDX-License-Identifier: GPL-2.0-only
17 #include <linux/irqchip/arm-gic-v3.h>
24 #include "vgic-mmio.h"
36 int __sz = vgic_its_get_abi(i)->t##_esz; \
37 struct kvm *__k = (i)->dev->kvm; \
44 __ret = -EINVAL; \
53 int __sz = vgic_its_get_abi(i)->t##_esz; \
54 struct kvm *__k = (i)->dev->kvm; \
62 __ret = -EINVAL; \
79 struct vgic_dist *dist = &kvm->arch.vgic; in vgic_add_lpi()
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/linux/include/uapi/drm/
H A Damdgpu_drm.h1 /* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*-
90 * GPU's virtual address space via gart. Gart memory linearizes non-contiguous
97 * %AMDGPU_GEM_DOMAIN_GDS Global on-chip data storage used to share data
178 /* Flag that BO should be coherent across devices when using device-leve
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/linux/drivers/pmdomain/ti/
H A Domap_prm.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
6 * Tero Kristo <t-kristo@ti.com>
19 #include <linux/reset-controller.h>
24 #include <linux/platform_data/ti-prm.h>
35 unsigned long statechange:1; /* Optional low-power state change */
142 { .rst = -1 },
148 { .rst = -1 },
155 { .rst = -1 },
389 .name = "vpe", .base = 0x4ae07c80,
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/linux/arch/mips/mm/
H A Dc-r4k.c22 #include <linux/dma-map-ops.h> /* for dma_default_coherent */
29 #include <asm/cpu-features.h>
30 #include <asm/cpu-type.h>
38 #include <asm/mips-cps.h>
43 * R4K_HIT - Virtual user or kernel address based cache operations. The
46 * R4K_INDEX - Index based cache operations.
53 * r4k_op_needs_ipi() - Decide if a cache op needs to be done on every core.
68 /* The MIPS Coherence Manager (CM) globalizes address-based cache ops */ in r4k_op_needs_ipi()
74 * be needed, but only if there are foreign CPUs (non-siblings with in r4k_op_needs_ipi()
388 * is not cached in the S-cache, we know it also won't be in local_r4k___flush_cache_all()
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/linux/drivers/staging/media/av7110/
H A Dav7110.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * driver for the SAA7146 based AV110 cards (like the Fujitsu-Siemens DVB)
4 * - initialization and demux stuff
6 * Copyright (C) 1999-2002 Ralph Metzler
10 * Copyright (C) 1998,1999 Christian Theiss <mistert@rz.fh-augsburg.de>
42 #include "ttpci-eeprom.h"
83 MODULE_PARM_DESC(rgb_on, "For Siemens DVB-C cards only: Enable RGB control signal on SCART pin 16 t…
85 MODULE_PARM_DESC(volume, "initial volume: default 255 (range 0-255)");
87 MODULE_PARM_DESC(budgetpatch, "use budget-patch hardware modification: default 0 (0 no, 1 autodetec…
89 MODULE_PARM_DESC(full_ts, "enable code for full-ts hardware modification: 0 disable (default), 1 en…
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