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/linux/tools/power/x86/x86_energy_perf_policy/
H A Dx86_energy_perf_policy.81 .\" This page Copyright (C) 2010 - 2015 Len Brown <len.brown@intel.com>
5 x86_energy_perf_policy \- Manage Energy vs. Performance Policy via x86 Model Specific Registers
10 .RB "scope: \-\-cpu\ cpu-list | \-\-pkg\ pkg-list"
12 .RB "cpu-list, pkg-list: # | #,# | #-# | all"
14 .RB "field: \-\-all | \-\-epb | \-\-hwp-epp | \-\-hwp-min | \-\-hwp-max | \-\-hwp-desired"
16 .RB "other: (\-\-force | \-\-hwp-enable | \-\-turbo-enable) value)"
18 .RB "value: # | default | performance | balance-performance | balance-power | power"
21 displays and updates energy-performance policy settings specific to
23 updates, no matter if the Linux cpufreq sub-system is enabled or not.
27 such as how aggressively the hardware enters and exits CPU idle states (C-states)
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/linux/include/linux/
H A Dlocal_lock.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 * local_lock_init - Runtime initialize a lock instance
13 * local_lock - Acquire a per CPU local lock
19 * local_lock_irq - Acquire a per CPU local lock and disable interrupts
25 * local_lock_irqsave - Acquire a per CPU local lock, save and disable
34 * local_unlock - Release a per CPU local lock
40 * local_unlock_irq - Release a per CPU local lock and enable interrupts
46 * local_unlock_irqrestore - Release a per CPU local lock and restore
55 * local_lock_init - Runtime initialize a lock instance
60 * local_trylock - Try to acquire a per CPU local lock
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H A Dsrcutree.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Sleepable Read-Copy Update mechanism for mutual exclusion,
22 atomic_long_t srcu_locks; /* Locks per CPU. */
23 atomic_long_t srcu_unlocks; /* Unlocks per CPU. */
27 * Per-CPU structure feeding into leaf srcu_node, similar in function
31 /* Read-side state. */
32 struct srcu_ctr srcu_ctrs[2]; /* Locks and unlocks per CPU. */
36 /* Update-side state. */
47 /* ->srcu_data_have_cbs[]. */
48 int cpu; member
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H A Dpercpu-defs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/percpu-defs.h - basic definitions for percpu areas
38 * Base implementations of per-CPU variable declarations and definitions, where
106 * Variant on the per-CPU variable declaration/definition theme used for
107 * ordinary per-CPU variables.
116 * Declaration/definition used for per-CPU variables that are frequently
129 * Declaration/definition used for per-CPU variables that must be cacheline
131 * data corresponds to a particular CPU, inefficiencies due to direct access by
135 * An example of this would be statistical data, where each CPU's set of data
136 * is updated by that CPU alone, but the data from across all CPUs is collated
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H A Dworkqueue.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * workqueue.h --- work queue handling for Linux.
23 #define work_data_bits(work) ((unsigned long *)(&(work)->data))
51 * data contains off-queue information when !WORK_STRUCT_PWQ.
60 WORK_OFFQ_FLAG_BITS = WORK_OFFQ_FLAG_END - WORK_OFFQ_FLAG_SHIFT,
66 * When a work item is off queue, the high bits encode off-queu
119 int cpu; global() member
702 schedule_work_on(int cpu,struct work_struct * work) schedule_work_on() argument
800 schedule_delayed_work_on(int cpu,struct delayed_work * dwork,unsigned long delay) schedule_delayed_work_on() argument
821 work_on_cpu(int cpu,long (* fn)(void *),void * arg) work_on_cpu() argument
825 work_on_cpu_safe(int cpu,long (* fn)(void *),void * arg) work_on_cpu_safe() argument
874 wq_watchdog_touch(int cpu) wq_watchdog_touch() argument
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/linux/Documentation/translations/it_IT/locking/
H A Dlocktypes.rst1 .. SPDX-License-Identifier: GPL-2.0
3 .. include:: ../disclaimer-ita.rst
17 - blocchi ad attesa con sospensione
18 - blocchi locali per CPU
19 - blocchi ad attesa attiva
28 ---------------------------------
41 - mutex
42 - rt_mutex
43 - semaphore
44 - rw_semaphore
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/linux/Documentation/trace/
H A Devents-kmem.rst8 - Slab allocation of small objects of unknown type (kmalloc)
9 - Slab allocation of small objects of known type
10 - Page allocation
11 - Per-CPU Allocator Activity
12 - External Fragmentation
40 These events are similar in usage to the kmalloc-related events except that
50 mm_page_alloc_zone_locked page=%p pfn=%lu order=%u migratetype=%d cpu=%d percpu_refill=%d
56 the per-CPU allocator (high performance) or the buddy allocator.
60 amounts of activity imply high activity on the zone->lock. Taking this lock
72 contention on the lruvec->lru_lock.
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/linux/Documentation/virt/
H A Dguest-halt-polling.rst15 2) The VM-exit cost can be avoided.
25 ("per-cpu guest_halt_poll_ns"), which is adjusted by the algorithm
42 Division factor used to shrink per-cpu guest_halt_poll_ns when
49 Multiplication factor used to grow per-cpu guest_halt_poll_ns
50 when event occurs after per-cpu guest_halt_poll_ns
57 The per-cpu guest_halt_poll_ns eventually reaches zero
59 per-cpu guest_halt_poll_ns when growing. This can
70 to avoid it (per-cpu guest_halt_poll_ns will remain
82 - Care should be taken when setting the guest_halt_poll_ns parameter as a
83 large value has the potential to drive the cpu usage to 100% on a machine
/linux/scripts/gdb/linux/
H A Dcpus.py4 # per-cpu tools
6 # Copyright (c) Siemens AG, 2011-2013
27 return gdb.selected_thread().num - 1
31 raise gdb.GdbError("Sorry, obtaining the current CPU is not yet "
35 def per_cpu(var_ptr, cpu): argument
36 if cpu == -1:
37 cpu = get_current_cpu()
40 "trap_block[{0}].__per_cpu_base".format(str(cpu)))
44 "__per_cpu_offset[{0}]".format(str(cpu)))
77 entry = -1
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/linux/drivers/irqchip/
H A Dirq-armada-370-xp.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
23 #include <linux/cpu.h>
41 * To CPU 0 To CPU 1
45 * +---------------+ +---------------+
47 * | per-CPU | | per-CPU |
51 * +---------------+ +---------------+
56 * +-------------------+
61 * +-------------------+
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H A Dirq-riscv-imsic-early.c1 // SPDX-License-Identifier: GPL-2.0
7 #define pr_fmt(fmt) "riscv-imsic: " fmt
9 #include <linux/cpu.h>
15 #include <linux/irqchip/riscv-imsic.h>
21 #include "irq-riscv-imsic-state.h"
26 static void imsic_ipi_send(unsigned int cpu) in imsic_ipi_send() argument
28 struct imsic_local_config *local = per_cpu_ptr(imsic->global.local, cpu); in imsic_ipi_send()
30 writel(IMSIC_IPI_ID, local->msi_va); in imsic_ipi_send()
35 /* Enable IPIs for current CPU. */ in imsic_ipi_starting_cpu()
41 /* Disable IPIs for current CPU. */ in imsic_ipi_dying_cpu()
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/linux/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/
H A Dmetrics.json12 "BriefDescription": "Core-to-uncore bus utilization",
21 "ScaleUnit": "1per cache access"
28 "ScaleUnit": "1per cache access"
35 "ScaleUnit": "1per cache read access"
42 "ScaleUnit": "1per cache access"
49 "ScaleUnit": "1per cache access"
56 "ScaleUnit": "1per cache read access"
61 "BriefDescription": "Misses per thousand instructions (data)",
68 "BriefDescription": "Misses per thousan
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/linux/tools/perf/pmu-events/arch/arm64/ampere/ampereone/
H A Dmetrics.json12 "BriefDescription": "Core-to-uncore bus utilization",
21 "ScaleUnit": "1per cache access"
28 "ScaleUnit": "1per cache access"
35 "ScaleUnit": "1per cache read access"
42 "ScaleUnit": "1per cache access"
49 "ScaleUnit": "1per cache access"
56 "ScaleUnit": "1per cache read access"
61 "BriefDescription": "Misses per thousand instructions (data)",
68 "BriefDescription": "Misses per thousand instructions (instruction)",
89 "BriefDescription": "Giga-floating point operations per second",
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/linux/Documentation/core-api/
H A Dlocal_ops.rst29 Local atomic operations are meant to provide fast and highly reentrant per CPU
34 Having fast per CPU atomic counters is interesting in many cases: it does not
40 CPU which owns the data. Therefore, care must taken to make sure that only one
41 CPU writes to the ``local_t`` data. This is done by using per cpu data and
43 however permitted to read ``local_t`` data from any CPU: it will then appear to
44 be written out of order wrt other memory writes by the owner CPU.
54 ``asm-generic/local.h`` in your architecture's ``local.h`` is sufficient.
66 * Variables touched by local ops must be per cpu variables.
67 * *Only* the CPU owner of these variables must write to them.
68 * This CPU can use local ops from any context (process, irq, softirq, nmi, ...)
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/linux/samples/bpf/
H A Dxdp_sample_user.c1 // SPDX-License-Identifier: GPL-2.0-only
55 #define __COLUMN(x) "%'10" x " %-13s"
93 struct datarec *cpu; member
174 static const char *xdp_redirect_err_help[XDP_REDIRECT_ERR_MAX - 1] = {
215 "By default, redirect success statistics are disabled, use -s to enable.\n" in sample_print_help()
216 "The terse output mode is default, verbose mode can be activated using -v\n" in sample_print_help()
219 " rx/s Number of packets received per second\n" in sample_print_help()
220 " redir/s Number of packets successfully redirected per second\n" in sample_print_help()
221 " err,drop/s Aggregated count of errors per second (including dropped packets)\n" in sample_print_help()
222 " xmit/s Number of packets transmitted on the output device per second\n\n" in sample_print_help()
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H A Dmap_perf_test_user.c1 // SPDX-License-Identifier: GPL-2.0-only
82 static void test_hash_prealloc(int cpu) in test_hash_prealloc() argument
90 printf("%d:hash_map_perf pre-alloc %lld events per sec\n", in test_hash_prealloc()
91 cpu, max_cnt * 1000000000ll / (time_get_ns() - start_time)); in test_hash_prealloc()
120 static void do_test_lru(enum test_type test, int cpu) in do_test_lru() argument
129 if (test == INNER_LRU_HASH_PREALLOC && cpu) { in do_test_lru()
130 /* If CPU is not 0, create inner_lru hash map and insert the fd in do_test_lru()
131 * value into the array_of_lru_hash map. In case of CPU 0, in do_test_lru()
140 assert(cpu < MAX_NR_CPUS); in do_test_lru()
146 inner_lru_map_fds[cpu] = in do_test_lru()
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/linux/kernel/sched/
H A Dext_idle.c1 // SPDX-License-Identifier: GPL-2.0
3 * BPF extensible scheduler class: Documentation/scheduler/sched-ext.rst
5 * Built-in idle CPU tracking policy.
14 /* Enable/disable built-in idle CPU selection policy */
17 /* Enable/disable per-node idle cpumasks */
34 cpumask_var_t cpu; member
39 * Global host-wide idle cpumasks (used when SCX_OPS_BUILTIN_IDLE_PER_NODE
45 * Per-node idle cpumasks.
50 * Local per-CPU cpumasks (used to generate temporary idle cpumasks).
67 * Returns the NUMA node ID associated with a @cpu, or NUMA_NO_NODE if
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/linux/Documentation/bpf/
H A Dmap_hash.rst1 .. SPDX-License-Identifier: GPL-2.0-only
3 .. Copyright (C) 2022-2023 Isovalent, Inc.
10 - ``BPF_MAP_TYPE_HASH`` was introduced in kernel version 3.19
11 - ``BPF_MAP_TYPE_PERCPU_HASH`` was introduced in version 4.6
12 - Both ``BPF_MAP_TYPE_LRU_HASH`` and ``BPF_MAP_TYPE_LRU_PERCPU_HASH``
20 to the max_entries limit that you specify. Hash maps use pre-allocation
22 used to disable pre-allocation when it is too memory expensive.
24 ``BPF_MAP_TYPE_PERCPU_HASH`` provides a separate value slot per
25 CPU. The per-cpu values are stored internally in an array.
32 shared across CPUs but it is possible to request a per CPU LRU list with
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/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dapple,aic.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/apple,aic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hector Martin <marcan@marcan.st>
19 - Level-triggered hardware IRQs wired to SoC blocks
20 - Single mask bit per IRQ
21 - Per-IRQ affinity setting
22 - Automatic masking on event delivery (auto-ack)
23 - Software triggering (ORed with hw line)
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/linux/Documentation/cpu-freq/
H A Dcpu-drivers.rst1 .. SPDX-License-Identifier: GPL-2.0
10 - Dominik Brodowski <linux@brodo.de>
11 - Rafael J. Wysocki <rafael.j.wysocki@intel.com>
12 - Viresh Kumar <viresh.kumar@linaro.org>
18 1.2 Per-CPU Initialization
31 So, you just got a brand-new CPU / chipset with datasheets and want to
32 add cpufreq support for this CPU / chipset? Great. Here are some hints
37 ------------------
40 function check whether this kernel runs on the right CPU and the right
46 .name - The name of this driver.
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/linux/Documentation/admin-guide/cgroup-v1/
H A Dcpusets.rst11 - Portions Copyright (c) 2004-2006 Silicon Graphics, Inc.
12 - Modified by Paul Jackson <pj@sgi.com>
13 - Modified by Christoph Lameter <cl@gentwo.org>
14 - Modified by Paul Menage <menage@google.com>
15 - Modified by Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
41 ----------------------
45 an on-line node that contains memory.
47 Cpusets constrain the CPU and Memory placement of tasks to only
54 Documentation/admin-guide/cgroup-v1/cgroups.rst.
57 include CPUs in its CPU affinity mask, and using the mbind(2) and
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/linux/Documentation/timers/
H A Dhighres.rst8 https://www.kernel.org/doc/ols/2006/ols2006v1-pages-333-346.pdf
11 http://www.cs.columbia.edu/~nahum/w6998/papers/ols2006-hrtimers-slides.pdf
23 - hrtimer base infrastructure
24 - timeofday and clock source management
25 - clock event management
26 - high resolution timer functionality
27 - dynamic ticks
31 ---------------------------
40 - time ordered enqueueing into a rb-tree
41 - independent of ticks (the processing is based on nanoseconds)
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/linux/include/linux/irqchip/
H A Dirq-bcm2836.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
12 * The low 2 bits identify the CPU that the GPU IRQ goes to, and the
13 * next 2 bits identify the CPU that the GPU FIQ goes to.
16 /* When setting bits 0-3, enables PMU interrupts on that CPU. */
18 /* When setting bits 0-3, disables PMU interrupts on that CPU. */
21 * The low 4 bits of this are the CPU's timer IRQ enables, and the
22 * next 4 bits are the CPU's timer FIQ enables (which override the IRQ
27 * The low 4 bits of this are the CPU's per-mailbox IRQ enables, and
28 * the next 4 bits are the CPU's per-mailbox FIQ enables (which
33 * The CPU's interrupt status register. Bits are defined by the
[all …]
/linux/kernel/cgroup/
H A Drstat.c1 // SPDX-License-Identifier: GPL-2.0-only
2 #include "cgroup-internal.h"
15 static void cgroup_base_stat_flush(struct cgroup *cgrp, int cpu);
21 * they define the ss->css_rstat_flush callback.
25 return css_is_self(css) || css->ss->css_rstat_flush != NULL; in css_uses_rstat()
29 struct cgroup_subsys_state *css, int cpu) in css_rstat_cpu() argument
31 return per_cpu_ptr(css->rstat_cpu, cpu); in css_rstat_cpu()
35 struct cgroup *cgrp, int cpu) in cgroup_rstat_base_cpu() argument
37 return per_cpu_ptr(cgrp->rstat_base_cpu, cpu); in cgroup_rstat_base_cpu()
43 return &ss->rstat_ss_lock; in ss_rstat_lock()
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/linux/Documentation/networking/device_drivers/ethernet/freescale/
H A Ddpaa.rst1 .. SPDX-License-Identifier: GPL-2.0
8 - Madalin Bucur <madalin.bucur@nxp.com>
9 - Camelia Groza <camelia.groza@nxp.com>
13 - DPAA Ethernet Overview
14 - DPAA Ethernet Supported SoCs
15 - Configuring DPAA Ethernet in your kernel
16 - DPAA Ethernet Frame Processing
17 - DPAA Ethernet Features
18 - DPAA IRQ Affinity and Receive Side Scaling
19 - Debugging
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