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/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dhost-generic-pci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/host-generic-pci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Will Deacon <will@kernel.org>
13 Firmware-initialised PCI host controllers and PCI emulations, such as the
14 virtio-pci implementations found in kvmtool and other para-virtualised
21 Configuration Space is assumed to be memory-mapped (as opposed to being
26 For CAM, this 24-bit offset is:
41 - description:
[all …]
H A Dcdns,cdns-pcie-host.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/pci/cdns,cdns-pcie-host.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence PCIe host controller
10 - Tom Joseph <tjoseph@cadence.com>
13 - $ref: cdns-pcie-host.yaml#
17 const: cdns,cdns-pcie-host
22 reg-names:
24 - const: reg
[all …]
H A Dxgene-pci.txt1 * AppliedMicro X-Gene PCIe interface
4 - device_type: set to "pci"
5 - compatible: should contain "apm,xgene-pcie" to identify the core.
6 - reg: A list of physical base address and length for each set of controller
7 registers. Must contain an entry for each entry in the reg-names
9 - reg-names: Must include the following entries:
11 "cfg": PCIe configuration space registers.
12 - #address-cells: set to <3>
13 - #size-cells: set to <2>
14 - ranges: ranges for the outbound memory, I/O regions.
[all …]
H A Dxgene-pci-msi.txt1 * AppliedMicro X-Gene v1 PCIe MSI controller
5 - compatible: should be "apm,xgene1-msi" to identify
6 X-Gene v1 PCIe MSI controller block.
7 - msi-controller: indicates that this is an X-Gene v1 PCIe MSI controller node
8 - reg: physical base address (0x79000000) and length (0x900000) for controller
11 - reg-names: not required
12 - interrupts: A list of 16 interrupt outputs of the controller, starting from
14 - interrupt-names: not required
16 Each PCIe node needs to have property msi-parent that points to an MSI
25 compatible = "apm,xgene1-msi";
[all …]
H A Dqcom,pcie-sm8450.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/qcom,pcie-sm8450.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
14 Qualcomm SM8450 SoC PCIe root complex controller is based on the Synopsys
15 DesignWare PCIe IP.
20 - qcom,pcie-sm8450-pcie0
21 - qcom,pcie-sm8450-pcie1
[all …]
H A Dpci-msi.txt23 Documentation/devicetree/bindings/interrupt-controller/msi.txt.
30 -------------------
32 - msi-map: Maps a Requester ID to an MSI controller and associated
33 msi-specifier data. The property is an arbitrary number of tuples of
34 (rid-base,msi-controller,msi-base,length), where:
36 * rid-base is a single cell describing the first RID matched by the entry.
38 * msi-controller is a single phandle to an MSI controller
40 * msi-base is an msi-specifier describing the msi-specifier produced for the
44 following the rid-base.
46 Any RID r in the interval [rid-base, rid-base + length) is associated with
[all …]
/freebsd/sys/contrib/device-tree/src/arm/marvell/
H A Darmada-385.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
12 #include "armada-38x.dtsi"
19 #address-cells = <1>;
20 #size-cells = <0>;
21 enable-method = "marvell,armada-380-smp";
25 compatible = "arm,cortex-a9";
30 compatible = "arm,cortex-a9";
36 pciec: pcie {
[all …]
H A Darmada-380.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
12 #include "armada-38x.dtsi"
19 #address-cells = <1>;
20 #size-cells = <0>;
21 enable-method = "marvell,armada-380-smp";
25 compatible = "arm,cortex-a9";
31 internal-regs {
33 compatible = "marvell,mv88f6810-pinctrl";
[all …]
H A Darmada-xp-mv78230.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 #include "armada-xp.dtsi"
17 compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
25 #address-cells = <1>;
26 #size-cells = <0>;
27 enable-method = "marvell,armada-xp-smp";
31 compatible = "marvell,sheeva-v7";
34 clock-latency = <1000000>;
39 compatible = "marvell,sheeva-v7";
[all …]
H A Dkirkwood-98dx4122.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 pciec: pcie@82000000 {
5 compatible = "marvell,kirkwood-pcie";
9 #address-cells = <3>;
10 #size-cells = <2>;
12 bus-range = <0x00 0xff>;
16 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
17 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>;
19 pcie0: pcie@1,0 {
21 assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
[all …]
/freebsd/sys/contrib/device-tree/src/powerpc/fsl/
H A Dmpc8544ds.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /include/ "mpc8544si-pre.dtsi"
16 reg = <0 0 0 0>; // Filled by U-Boot
33 clock-frequency = <66666666>;
34 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
35 interrupt-map = <
38 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
39 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
40 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
41 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
[all …]
H A Dmpc8572si-post.dtsi36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
44 compatible = "fsl,mpc8548-pcie";
46 #size-cells = <2>;
47 #address-cells = <3>;
48 bus-range = <0 255>;
49 clock-frequency = <33333333>;
52 pcie@0 {
54 #interrupt-cells = <1>;
[all …]
H A Dmpc8544si-post.dtsi36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,mpc8544-lbc", "fsl,pq3-localbus", "simple-bus";
44 compatible = "fsl,mpc8540-pci";
47 bus-range = <0 0xff>;
48 #interrupt-cells = <1>;
49 #size-cells = <2>;
50 #address-cells = <3>;
55 compatible = "fsl,mpc8548-pcie";
57 #size-cells = <2>;
[all …]
H A Dp2020si-post.dtsi36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,p2020-elbc", "fsl,elbc", "simple-bus";
44 compatible = "fsl,mpc8548-pcie";
46 #size-cells = <2>;
47 #address-cells = <3>;
48 bus-range = <0 255>;
49 clock-frequency = <33333333>;
53 pcie@0 {
55 #interrupt-cells = <1>;
[all …]
H A Dp1010si-post.dtsi36 #address-cells = <2>;
37 #size-cells = <1>;
44 compatible = "fsl,p1010-pcie", "fsl,qoriq-pcie-v2.3";
46 #size-cells = <2>;
47 #address-cells = <3>;
48 bus-range = <0 255>;
49 clock-frequency = <33333333>;
52 pcie@0 {
54 #interrupt-cells = <1>;
55 #size-cells = <2>;
[all …]
H A Dp1022si-post.dtsi36 #address-cells = <2>;
37 #size-cells = <1>;
39 * The localbus on the P1022 is not a simple-bus because of the eLBC
42 compatible = "fsl,p1022-elbc", "fsl,elbc";
49 compatible = "fsl,mpc8548-pcie";
51 #size-cells = <2>;
52 #address-cells = <3>;
53 bus-range = <0 255>;
54 clock-frequency = <33333333>;
57 pcie@0 {
[all …]
H A Dmpc8536si-post.dtsi36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,mpc8536-elbc", "fsl,elbc", "simple-bus";
44 compatible = "fsl,mpc8540-pci";
47 bus-range = <0 0xff>;
48 #interrupt-cells = <1>;
49 #size-cells = <2>;
50 #address-cells = <3>;
55 compatible = "fsl,mpc8548-pcie";
57 #size-cells = <2>;
[all …]
H A Dmpc8641si-post.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2016 Elettra-Sincrotrone Trieste S.C.p.A.
9 #address-cells = <2>;
10 #size-cells = <1>;
11 compatible = "fsl,mpc8641-localbus", "simple-bus";
16 #address-cells = <1>;
17 #size-cells = <1>;
19 compatible = "fsl,mpc8641-soc", "simple-bus";
20 bus-frequency = <0>;
22 mcm-law@0 {
[all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/ivytown/
H A Duncore-cache.json10 … "BriefDescription": "All LLC Misses (code+ data rd + data wr - including demand and prefetch)",
14 "Filter": "filter_state=0x1",
27 "UMask": "0x1",
31 …"BriefDescription": "LLC misses - demand and prefetch data reads - excludes LLC prefetches. Derive…
42 …"BriefDescription": "LLC misses - Uncacheable reads. Derived from unc_c_tor_inserts.miss_opcode.un…
86 …"BriefDescription": "PCIe allocating writes that miss LLC - DDIO misses. Derived from unc_c_tor_in…
97 …"BriefDescription": "LLC misses for PCIe read current. Derived from unc_c_tor_inserts.miss_opcode.…
119 …"BriefDescription": "LLC misses for PCIe non-snoop reads. Derived from unc_c_tor_inserts.miss_opco…
130 …"BriefDescription": "LLC misses for PCIe non-snoop writes (full line). Derived from unc_c_tor_inse…
148 "UMask": "0x1",
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/broadcom/stingray/
H A Dstingray-pcie.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
6 pcie8: pcie@60400000 {
7 compatible = "brcm,iproc-pcie-paxc-v
[all...]
/freebsd/lib/libpmc/pmu-events/arch/x86/jaketown/
H A Duncore-cache.json10 … "BriefDescription": "All LLC Misses (code+ data rd + data wr - including demand and prefetch)",
14 "Filter": "filter_state=0x1",
27 "UMask": "0x1",
31 …"BriefDescription": "LLC misses - demand and prefetch data reads - excludes LLC prefetches. Derive…
42 …"BriefDescription": "LLC misses - Uncacheable reads. Derived from unc_c_tor_inserts.miss_opcode.un…
53 …"BriefDescription": "PCIe allocating writes that miss LLC - DDIO misses. Derived from unc_c_tor_in…
82 "UMask": "0x1",
93 "UMask": "0x1",
97 … "BriefDescription": "Partial PCIe reads. Derived from unc_c_tor_inserts.opcode.pcie_partial",
104 "UMask": "0x1",
[all …]
/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dnvidia,tegra210-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xus
[all...]
/freebsd/lib/libpmc/pmu-events/arch/x86/broadwellde/
H A Duncore-cache.json10 … "BriefDescription": "All LLC Misses (code+ data rd + data wr - including demand and prefetch)",
14 "Filter": "filter_state=0x1",
27 "UMask": "0x1",
31 …"BriefDescription": "LLC misses - demand and prefetch data reads - excludes LLC prefetches. Derive…
42 …"BriefDescription": "LLC misses - Uncacheable reads (from cpu) . Derived from unc_c_tor_inserts.mi…
108 …"BriefDescription": "LLC misses for PCIe read current. Derived from unc_c_tor_inserts.miss_opcode",
119 …"BriefDescription": "ItoM write misses (as part of fast string memcpy stores) + PCIe full line wri…
130 …"BriefDescription": "PCIe write misses (full cache line). Derived from unc_c_tor_inserts.miss_opco…
141 … "BriefDescription": "PCIe writes (partial cache line). Derived from unc_c_tor_inserts.opcode",
147 "UMask": "0x1",
[all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/broadwellx/
H A Duncore-cache.json10 … "BriefDescription": "All LLC Misses (code+ data rd + data wr - including demand and prefetch)",
14 "Filter": "filter_state=0x1",
27 "UMask": "0x1",
31 …"BriefDescription": "LLC misses - demand and prefetch data reads - excludes LLC prefetches. Derive…
42 …"BriefDescription": "LLC misses - Uncacheable reads (from cpu) . Derived from unc_c_tor_inserts.mi…
108 …"BriefDescription": "LLC misses for PCIe read current. Derived from unc_c_tor_inserts.miss_opcode",
119 …"BriefDescription": "ItoM write misses (as part of fast string memcpy stores) + PCIe full line wri…
130 …"BriefDescription": "PCIe write misses (full cache line). Derived from unc_c_tor_inserts.miss_opco…
141 … "BriefDescription": "PCIe writes (partial cache line). Derived from unc_c_tor_inserts.opcode",
147 "UMask": "0x1",
[all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/haswellx/
H A Duncore-cache.json10 … "BriefDescription": "All LLC Misses (code+ data rd + data wr - including demand and prefetch)",
14 "Filter": "filter_state=0x1",
27 "UMask": "0x1",
31 …"BriefDescription": "LLC misses - demand and prefetch data reads - excludes LLC prefetches. Derive…
42 …"BriefDescription": "LLC misses - Uncacheable reads (from cpu) . Derived from unc_c_tor_inserts.mi…
108 …"BriefDescription": "LLC misses for PCIe read current. Derived from unc_c_tor_inserts.miss_opcode",
119 …"BriefDescription": "ItoM write misses (as part of fast string memcpy stores) + PCIe full line wri…
130 …"BriefDescription": "PCIe write misses (full cache line). Derived from unc_c_tor_inserts.miss_opco…
141 … "BriefDescription": "PCIe writes (partial cache line). Derived from unc_c_tor_inserts.opcode",
147 "UMask": "0x1",
[all …]

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