| /linux/Documentation/admin-guide/perf/ |
| H A D | hisi-pcie-pmu.rst | 2 HiSilicon PCIe Performance Monitoring Unit (PMU)
5 On Hip09, HiSilicon PCIe Performance Monitoring Unit (PMU) could monitor
6 bandwidth, latency, bus utilization and buffer occupancy data of PCIe.
8 Each PCIe Core has a PMU to monitor multi Root Ports of this PCIe Core and
9 all Endpoints downstream these Root Ports.
12 HiSilicon PCIe PMU driver
15 The PCIe PMU driver registers a perf PMU with the name of its sicl-id and PCIe
30 The "bus" sysfs file allows users to get the bus number of Root Ports
31 monitored by PMU. Furthermore users can get the Root Ports range in
40 ------------------------------------------
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| H A D | dwc_pcie_pmu.rst | 2 Synopsys DesignWare Cores (DWC) PCIe Performance Monitoring Unit (PMU)
5 DesignWare Cores (DWC) PCIe PMU
8 The PMU is a PCIe configuration space register block provided by each PCIe Root
9 Port in a Vendor-Specific Extended Capability named RAS D.E.S (Debug, Error
14 collection of statistics, Synopsys DesignWare Cores PCIe controller
17 - one 64-bit counter for Time Based Analysis (RX/TX data throughput and
18 time spent in each low-power LTSSM state) and
19 - one 32-bit counter per event for Event Counting (error and non-error
25 -------------------
28 throughput and time spent in each low-power LTSSM state by the controller.
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| /linux/drivers/pci/pcie/ |
| H A D | pme.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe Native PME support
5 * Copyright (C) 2007 - 2009 Intel Corp
6 * Copyright (C) 2007 - 2009 Shaohua Li <shaohua.li@intel.com>
26 * If this switch is set, MSI will not be used for PCIe PME signaling. This
27 * causes the PCIe port driver to use INTx interrupts only, but it turns out
28 * that using MSI for PCIe PME signaling doesn't play well with PCIe PME-based
29 * wake-up from system sleep states.
38 return 1; in pcie_pme_setup()
50 * pcie_pme_interrupt_enable - Enable/disable PCIe PME interrupt generation.
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| H A D | aer.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Implement the AER root port service driver. The driver registers an IRQ
4 * handler. When a root port triggers an AER interrupt, the IRQ handler
5 * collects Root Port status and schedules work.
11 * (C) Copyright 2009 Hewlett-Packard Development Company, L.P.
22 #include <linux/pci-acpi.h>
41 dev_printk(level, &(pdev)->dev, fmt, ##arg)
54 struct pci_dev *rpd; /* Root Port device */
65 * at its link partner (e.g. Root Port) because the errors will be
84 * Fields for Root Ports & Root Complex Event Collectors only; these
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| H A D | aspm.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Enable PCIe link L0s/L1 state and Clock Power Management
50 cap = &save_state->cap.data[0]; in pci_save_ltr_state()
66 cap = &save_state->cap.data[0]; in pci_restore_ltr_state()
74 pdev->l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS); in pci_configure_aspm_l1ss()
85 struct pci_dev *parent = pdev->bus->self; in pci_save_aspm_l1ss_state()
90 * If this is a Downstream Port, we never restore the L1SS state in pci_save_aspm_l1ss_state()
92 * Upstream Port below it. in pci_save_aspm_l1ss_state()
97 if (!pdev->l1ss || !parent->l1ss) in pci_save_aspm_l1ss_state()
108 cap = &save_state->cap.data[0]; in pci_save_aspm_l1ss_state()
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| H A D | bwctrl.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * PCIe bandwidth controller
8 * Copyright (C) 2023-2024 Intel Corporation
10 * The PCIe bandwidth controller provides a way to alter PCIe Link Speeds
12 * notification capability is required for all Root Ports and Downstream
15 * This service port driver hooks into the Bandwidth Notification interrupt
30 #include <linux/pci-bwctrl.h>
39 * struct pcie_bwctrl_data - PCIe bandwidth controller
41 * @cdev: Thermal cooling device associated with the port
48 /* Prevent port removal during Link Speed changes. */
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| /linux/tools/perf/Documentation/ |
| H A D | perf-iostat.txt | 1 perf-iostat(1)
5 ----
6 perf-iostat - Show I/O performance metrics
9 --------
12 'perf iostat' <ports> \-- <command> [<options>]
15 -----------
16 Mode is intended to provide four I/O performance metrics per each PCIe root port:
18 - Inbound Read - I/O devices below root port read from the host memory, in MB
20 - Inbound Write - I/O devices below root port write to the host memory, in MB
22 - Outbound Read - CPU reads from I/O devices below root port, in MB
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| /linux/Documentation/devicetree/bindings/pci/ |
| H A D | qcom,pcie-common.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/qcom,pcie-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm PCI Express Root Complex Common Properties
10 - Bjorn Andersson <andersson@kernel.org>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
18 reg-names:
23 minItems: 1
26 interrupt-names:
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| H A D | nvidia,tegra20-pcie.txt | 1 NVIDIA Tegra PCIe controller
4 - compatible: Must be:
5 - "nvidia,tegra20-pcie": for Tegra20
6 - "nvidia,tegra30-pcie": for Tegra30
7 - "nvidia,tegra124-pcie": for Tegra124 and Tegra132
8 - "nvidia,tegra210-pcie": for Tegra210
9 - "nvidia,tegra186-pcie": for Tegra186
10 - power-domains: To ungate power partition by BPMP powergate driver. Must
11 contain BPMP phandle and PCIe power partition ID. This is required only
13 - device_type: Must be "pci"
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| H A D | apple,pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/apple,pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Apple PCIe host controller
10 - Mark Kettenis <kettenis@openbsd.org>
13 The Apple PCIe host controller is a PCIe host controller with
14 multiple root ports present in Apple ARM SoC platforms, including
16 The controller incorporates Synopsys DesigWare PCIe logic to
17 implements its root ports. But the ATU found on most DesignWare
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| H A D | snps,dw-pcie.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare PCIe interface
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
14 Synopsys DesignWare PCIe host controller
16 # Please create a separate DT-schema for your DWC PCIe Root Port controller
17 # and make sure it's assigned with the vendor-specific compatible string.
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| H A D | mediatek,mt7621-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/mediatek,mt7621-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek MT7621 PCIe controller
10 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
13 MediaTek MT7621 PCIe subsys supports a single Root Complex (RC)
14 with 3 Root Ports. Each Root Port supports a Gen1 1-lane Link
16 MT7621 PCIe HOST Topology
18 .-------.
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| H A D | baikal,bt1-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/baikal,bt1-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Baikal-T1 PCIe Root Port Controller
10 - Serge Semin <fancer.lancer@gmail.com>
13 Embedded into Baikal-T1 SoC Root Complex controller with a single port
14 activated. It's based on the DWC RC PCIe v4.60a IP-core, which is configured
15 to have just a single Root Port function and is capable of establishing the
18 performed by software. There four in- and four outbound iATU regions
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| H A D | snps,dw-pcie-common.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DWC PCIe RP/EP controller
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
14 Generic Synopsys DesignWare PCIe Root Port and Endpoint controller
22 DWC PCIe CSR space is normally accessed over the dedicated Data Bus
23 Interface - DBI. In accordance with the reference manual the register
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| /linux/drivers/pci/controller/ |
| H A D | pci-mvebu.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe driver for Marvell Armada 370 and Armada XP SoCs
5 * Author: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
27 #include "../pci-bridge-emul.h"
30 * PCIe unit register offsets.
40 #define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4))
65 #define PCIE_CTRL_RC_MODE BIT(1)
83 /* Structure representing all PCIe interfaces */
99 /* Structure representing one PCIe interface */
103 u32 port; member
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| H A D | pcie-altera.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright Altera Corporation (C) 2013-2015. All rights reserved
6 * Description: Altera PCIe host controller driver
45 #define S10_RP_CFG_ADDR(pcie, reg) \ argument
46 (((pcie)->hip_base) + (reg) + (1 << 20))
47 #define S10_RP_SECONDARY(pcie) \ argument
48 readb(S10_RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS))
50 /* TLP configuration type 0 and 1 */
53 #define TLP_FMTTYPE_CFGRD1 0x05 /* Configuration Read Type 1 */
54 #define TLP_FMTTYPE_CFGWR1 0x45 /* Configuration Write Type 1 */
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| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
11 tristate "Aardvark PCIe controller"
18 Add support for Aardvark 64bit PCIe Host Controller. This
23 tristate "Altera PCIe controller"
26 Say Y here if you want to enable PCIe controller support on Altera
30 tristate "Altera PCIe MSI feature"
35 Say Y here if you want PCIe MSI support for the Altera FPGA.
44 tristate "Apple PCIe controller"
51 Say Y here if you want to enable PCIe controller support on Apple
52 system-on-chips, like the Apple M1. This is required for the USB
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| H A D | pcie-xilinx.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * PCIe host controller driver for Xilinx AXI PCIe Bridge
5 * Copyright (c) 2012 - 2014 Xilinx, Inc.
7 * Based on the Tegra PCIe driver
15 #include <linux/irqchip/irq-msi-lib.h>
25 #include <linux/pci-ecam.h>
44 #define XILINX_PCIE_INTR_ECRC_ERR BIT(1)
66 /* Root Port Error FIFO Read Register definitions */
71 /* Root Port Interrupt FIFO Read Register 1 definitions */
82 /* Root Port Interrupt FIFO Read Register 2 definitions */
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| H A D | pcie-xilinx-dma-pl.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * PCIe host controller driver for Xilinx XDMA PCIe Bridge
10 #include <linux/irqchip/irq-msi-lib.h>
19 #include "pcie-xilinx-common.h"
62 /* Root Port Error Register definitions */
67 /* Root Port Interrupt Register definitions */
70 /* Root Port Status/control Register definitions */
86 * struct xilinx_pl_dma_variant - PL DMA PCIe variant information
102 * struct pl_dma_pcie - PCIe port information
115 * @variant: PL DMA PCIe version check pointer
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| /linux/arch/powerpc/boot/dts/ |
| H A D | turris1x.dts | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Turris 1.x Device Tree Source
5 * Copyright 2013 - 2022 CZ.NIC z.s.p.o. (http://www.nic.cz/)
8 * and available at: https://docs.turris.cz/hw/turris-1x/turris-1x/
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/leds/common.h>
14 /include/ "fsl/p2020si-pre.dtsi"
17 model = "Turris 1.x";
41 gpio-controller@18 {
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| H A D | currituck.dts | 11 /dts-v1/;
16 #address-cells = <2>;
17 #size-cells = <2>;
20 dcr-parent = <&{/cpus/cpu@0}>;
27 #address-cells = <1>;
28 #size-cells = <0>;
34 clock-frequency = <1600000000>; // 1.6 GHz
35 timebase-frequency = <100000000>; // 100Mhz
36 i-cache-line-size = <32>;
37 d-cache-line-size = <32>;
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| /linux/drivers/pci/controller/cadence/ |
| H A D | pcie-cadence.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 // Cadence PCIe controller driver.
4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
11 #include <linux/pci-epf.h>
35 /* Root Port Requester ID Register */
74 /* Root Complex BAR Configuration Register */
96 /* BAR control values applicable to both Endpoint Function and Root Complex */
117 (((aperture) - 2) << ((bar) * 8))
135 * Root Port Registers (PCI configuration space for the root port function)
145 /* Region r Outbound AXI to PCIe Address Translation Register 0 */
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| /linux/Documentation/driver-api/cxl/ |
| H A D | theory-of-operation.rst | 1 .. SPDX-License-Identifier: GPL-2.0
14 range across multiple devices underneath a host-bridge or interleaved
15 across host-bridges.
20 logical device, the CXL subsystem is tasked to take PCIe and ACPI objects and
28 Platform firmware enumerates a menu of interleave options at the "CXL root port"
29 (Linux term for the top of the CXL decode topology). From there, PCIe topology
31 Each PCIe Switch in the path between the root and an endpoint introduces a point
34 interleave cycles across multiple Root Ports. An intervening Switch between a
35 port and an endpoint may interleave cycles across multiple Downstream Switch
39 module generates an emulated CXL topology of 2 Host Bridges each with 2 Root
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| /linux/drivers/pci/controller/dwc/ |
| H A D | pcie-hisi.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for HiSilicon SoCs
15 #include <linux/pci-acpi.h>
16 #include <linux/pci-ecam.h>
18 #include "../pci-host-common.h"
29 struct pci_config_window *cfg = bus->sysdata; in hisi_pcie_rd_conf()
32 if (bus->number == cfg->busr.start) { in hisi_pcie_rd_conf()
33 /* access only one slot on each root port */ in hisi_pcie_rd_conf()
47 struct pci_config_window *cfg = bus->sysdata; in hisi_pcie_wr_conf()
50 if (bus->number == cfg->busr.start) { in hisi_pcie_wr_conf()
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| H A D | pcie-qcom.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Qualcomm PCIe root complex driver
5 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
8 * Author: Stanimir Varbanov <svarbanov@mm-sol.com>
26 #include <linux/pci-ecam.h>
30 #include <linux/phy/pcie.h>
39 #include "../pci-host-common.h"
40 #include "pcie-designware.h"
41 #include "pcie-qcom-common.h"
109 #define L1_CLK_RMV_DIS BIT(1)
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