| /linux/Documentation/admin-guide/perf/ |
| H A D | hisi-pcie-pmu.rst | 2 HiSilicon PCIe Performance Monitoring Unit (PMU)
5 On Hip09, HiSilicon PCIe Performance Monitoring Unit (PMU) could monitor
6 bandwidth, latency, bus utilization and buffer occupancy data of PCIe.
8 Each PCIe Core has a PMU to monitor multi Root Ports of this PCIe Core and
9 all Endpoints downstream these Root Ports.
12 HiSilicon PCIe PMU driver
15 The PCIe PMU driver registers a perf PMU with the name of its sicl-id and PCIe
30 The "bus" sysfs file allows users to get the bus number of Root Ports
31 monitored by PMU. Furthermore users can get the Root Ports range in
40 ------------------------------------------
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| /linux/drivers/pci/pcie/ |
| H A D | pme.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe Native PME support
5 * Copyright (C) 2007 - 2009 Intel Corp
6 * Copyright (C) 2007 - 2009 Shaohua Li <shaohua.li@intel.com>
26 * If this switch is set, MSI will not be used for PCIe PME signaling. This
27 * causes the PCIe port driver to use INTx interrupts only, but it turns out
28 * that using MSI for PCIe PME signaling doesn't play well with PCIe PME-based
29 * wake-up from system sleep states.
38 return 1; in pcie_pme_setup()
50 * pcie_pme_interrupt_enable - Enable/disable PCIe PME interrupt generation.
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| H A D | aer.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Implement the AER root port service driver. The driver registers an IRQ
4 * handler. When a root port triggers an AER interrupt, the IRQ handler
5 * collects root port status and schedules work.
11 * (C) Copyright 2009 Hewlett-Packard Development Company, L.P.
21 #include <linux/pci-acpi.h>
49 struct pci_dev *rpd; /* Root Port device */
60 * at its link partner (e.g. root port) because the errors will be
79 * Fields for Root ports & root complex event collectors only, these
81 * messages received by the root port / event collector, INCLUDING the
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| H A D | aspm.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Enable PCIe link L0s/L1 state and Clock Power Management
49 cap = &save_state->cap.data[0]; in pci_save_ltr_state()
65 cap = &save_state->cap.data[0]; in pci_restore_ltr_state()
73 pdev->l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS); in pci_configure_aspm_l1ss()
84 struct pci_dev *parent = pdev->bus->self; in pci_save_aspm_l1ss_state()
89 * If this is a Downstream Port, we never restore the L1SS state in pci_save_aspm_l1ss_state()
91 * Upstream Port below it. in pci_save_aspm_l1ss_state()
96 if (!pdev->l1ss || !parent->l1ss) in pci_save_aspm_l1ss_state()
107 cap = &save_state->cap.data[0]; in pci_save_aspm_l1ss_state()
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| H A D | bwctrl.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * PCIe bandwidth controller
8 * Copyright (C) 2023-2024 Intel Corporation
10 * The PCIe bandwidth controller provides a way to alter PCIe Link Speeds
12 * notification capability is required for all Root Ports and Downstream
15 * This service port driver hooks into the Bandwidth Notification interrupt
30 #include <linux/pci-bwctrl.h>
39 * struct pcie_bwctrl_data - PCIe bandwidth controller
42 * @cdev: Thermal cooling device associated with the port
51 * Prevent port removal during LBMS count accessors and Link Speed changes.
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| H A D | portdrv.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Purpose: PCI Express Port Bus Driver
26 * The PCIe Capability Interrupt Message Number (PCIe r3.1, sec 7.8.2) must
27 * be one of the first 32 MSI-X entries. Per PCI r3.0, sec 6.8.3.1, MSI
32 #define get_descriptor_id(type, service) (((type - 4) << 8) | service)
41 * release_pcie_device - free PCI Express port service device structure
42 * @dev: Port service device to release
54 * services are enabled in "mask". Return the number of MSI/MSI-X vectors
65 * the MSI-X table entry or the MSI offset between the base Message in pcie_message_numbers()
66 * Data and the generated interrupt message. See PCIe r3.1, sec in pcie_message_numbers()
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| /linux/Documentation/devicetree/bindings/pci/ |
| H A D | altr,pcie-root-port.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/altr,pcie-root-port.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Altera PCIe Root Port
11 - Matthew Gerlach <matthew.gerlach@linux.intel.com>
16 - altr,pcie-root-port-1.0
17 - altr,pcie-root-port-2.0
21 - description: TX slave port region
22 - description: Control register access region
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| H A D | nvidia,tegra20-pcie.txt | 1 NVIDIA Tegra PCIe controller
4 - compatible: Must be:
5 - "nvidia,tegra20-pcie": for Tegra20
6 - "nvidia,tegra30-pcie": for Tegra30
7 - "nvidia,tegra124-pcie": for Tegra124 and Tegra132
8 - "nvidia,tegra210-pcie": for Tegra210
9 - "nvidia,tegra186-pcie": for Tegra186
10 - power-domains: To ungate power partition by BPMP powergate driver. Must
11 contain BPMP phandle and PCIe power partition ID. This is required only
13 - device_type: Must be "pci"
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| H A D | pci.txt | 3 PCI Bus Binding to: IEEE Std 1275-1994
4 https://www.devicetree.org/open-firmware/bindings/pci/pci2_1.pdf
9 https://www.devicetree.org/open-firmware/practice/imap/imap0_9d.pdf
14 - linux,pci-domain:
19 may be assigned to root buses behind different host bridges. The domain
21 - max-link-speed:
26 for gen2, and '1' for gen1. Any other values are invalid.
27 - reset-gpios:
30 - supports-clkreq:
32 root port to downstream device and host bridge drivers can do programming
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| H A D | mediatek,mt7621-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/mediatek,mt7621-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek MT7621 PCIe controller
10 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
13 MediaTek MT7621 PCIe subsys supports a single Root Complex (RC)
14 with 3 Root Ports. Each Root Port supports a Gen1 1-lane Link
16 MT7621 PCIe HOST Topology
18 .-------.
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| H A D | baikal,bt1-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/baikal,bt1-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Baikal-T1 PCIe Root Port Controller
10 - Serge Semin <fancer.lancer@gmail.com>
13 Embedded into Baikal-T1 SoC Root Complex controller with a single port
14 activated. It's based on the DWC RC PCIe v4.60a IP-core, which is configured
15 to have just a single Root Port function and is capable of establishing the
18 performed by software. There four in- and four outbound iATU regions
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| H A D | snps,dw-pcie-common.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DWC PCIe RP/EP controller
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
14 Generic Synopsys DesignWare PCIe Root Port and Endpoint controller
22 DWC PCIe CSR space is normally accessed over the dedicated Data Bus
23 Interface - DBI. In accordance with the reference manual the register
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| H A D | mediatek-pcie.txt | 1 MediaTek Gen2 PCIe controller
4 - compatible: Should contain one of the following strings:
5 "mediatek,mt2701-pcie"
6 "mediatek,mt2712-pcie"
7 "mediatek,mt7622-pcie"
8 "mediatek,mt7623-pcie"
9 "mediatek,mt7629-pcie"
10 "airoha,en7523-pcie"
11 - device_type: Must be "pci"
12 - reg: Base addresses and lengths of the root ports.
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| /linux/tools/perf/Documentation/ |
| H A D | perf-iostat.txt | 1 perf-iostat(1)
5 ----
6 perf-iostat - Show I/O performance metrics
9 --------
12 'perf iostat' <ports> \-- <command> [<options>]
15 -----------
16 Mode is intended to provide four I/O performance metrics per each PCIe root port:
18 - Inbound Read - I/O devices below root port read from the host memory, in MB
20 - Inbound Write - I/O devices below root port write to the host memory, in MB
22 - Outbound Read - CPU reads from I/O devices below root port, in MB
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| /linux/arch/powerpc/boot/dts/ |
| H A D | turris1x.dts | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Turris 1.x Device Tree Source
5 * Copyright 2013 - 2022 CZ.NIC z.s.p.o. (http://www.nic.cz/)
8 * and available at: https://docs.turris.cz/hw/turris-1x/turris-1x/
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/leds/common.h>
14 /include/ "fsl/p2020si-pre.dtsi"
17 model = "Turris 1.x";
41 gpio-controller@18 {
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| H A D | currituck.dts | 11 /dts-v1/;
16 #address-cells = <2>;
17 #size-cells = <2>;
20 dcr-parent = <&{/cpus/cpu@0}>;
27 #address-cells = <1>;
28 #size-cells = <0>;
34 clock-frequency = <1600000000>; // 1.6 GHz
35 timebase-frequency = <100000000>; // 100Mhz
36 i-cache-line-size = <32>;
37 d-cache-line-size = <32>;
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| /linux/drivers/pci/controller/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
7 tristate "Aardvark PCIe controller"
13 Add support for Aardvark 64bit PCIe Host Controller. This
18 tristate "Altera PCIe controller"
21 Say Y here if you want to enable PCIe controller support on Altera
25 tristate "Altera PCIe MSI feature"
29 Say Y here if you want PCIe MSI support for the Altera FPGA.
38 tristate "Apple PCIe controller"
44 Say Y here if you want to enable PCIe controller support on Apple
45 system-on-chips, like the Apple M1. This is required for the USB
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| H A D | pcie-xilinx.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * PCIe host controller driver for Xilinx AXI PCIe Bridge
5 * Copyright (c) 2012 - 2014 Xilinx, Inc.
7 * Based on the Tegra PCIe driver
24 #include <linux/pci-ecam.h>
43 #define XILINX_PCIE_INTR_ECRC_ERR BIT(1)
65 /* Root Port Error FIFO Read Register definitions */
70 /* Root Port Interrupt FIFO Read Register 1 definitions */
81 /* Root Port Interrupt FIFO Read Register 2 definitions */
84 /* Root Port Status/control Register definitions */
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| H A D | pcie-xilinx-dma-pl.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * PCIe host controller driver for Xilinx XDMA PCIe Bridge
18 #include "pcie-xilinx-common.h"
61 /* Root Port Error Register definitions */
66 /* Root Port Interrupt Register definitions */
69 /* Root Port Status/control Register definitions */
85 * struct xilinx_pl_dma_variant - PL DMA PCIe variant information
102 * struct pl_dma_pcie - PCIe port information
115 * @variant: PL DMA PCIe version check pointer
133 static inline u32 pcie_read(struct pl_dma_pcie *port, u32 reg) in pcie_read() argument
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| /linux/drivers/pci/controller/cadence/ |
| H A D | pcie-cadence.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 // Cadence PCIe controller driver.
4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
11 #include <linux/pci-epf.h>
35 /* Root Port Requester ID Register */
74 /* Root Complex BAR Configuration Register */
96 /* BAR control values applicable to both Endpoint Function and Root Complex */
117 (((aperture) - 2) << ((bar) * 8))
140 * Root Port Registers (PCI configuration space for the root port function)
150 /* Region r Outbound AXI to PCIe Address Translation Register 0 */
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| H A D | pcie-cadence-host.c | 1 // SPDX-License-Identifier: GPL-2.0
3 // Cadence PCIe host controller driver.
4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
13 #include "pcie-cadence.h"
33 struct cdns_pcie *pcie = &rc->pcie; in cdns_pci_map_bus() local
34 unsigned int busn = bus->number; in cdns_pci_map_bus()
39 * Only the root port (devfn == 0) is connected to this bus. in cdns_pci_map_bus()
46 return pcie->reg_base + (where & 0xfff); in cdns_pci_map_bus()
49 if (!(cdns_pcie_readl(pcie, CDNS_PCIE_LM_BASE) & 0x1)) in cdns_pci_map_bus()
51 /* Clear AXI link-down status */ in cdns_pci_map_bus()
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| /linux/Documentation/driver-api/cxl/ |
| H A D | memory-devices.rst | 1 .. SPDX-License-Identifier: GPL-2.0
14 range across multiple devices underneath a host-bridge or interleaved
15 across host-bridges.
20 logical device, the CXL subsystem is tasked to take PCIe and ACPI objects and
28 Platform firmware enumerates a menu of interleave options at the "CXL root port"
29 (Linux term for the top of the CXL decode topology). From there, PCIe topology
31 Each PCIe Switch in the path between the root and an endpoint introduces a point
33 given range only decodes to 1 one Host Bridge, but that Host Bridge may in turn
34 interleave cycles across multiple Root Ports. An intervening Switch between a
35 port and an endpoint may interleave cycles across multiple Downstream Switch
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| /linux/drivers/pci/controller/dwc/ |
| H A D | pcie-hisi.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for HiSilicon SoCs
15 #include <linux/pci-acpi.h>
16 #include <linux/pci-ecam.h>
28 struct pci_config_window *cfg = bus->sysdata; in hisi_pcie_rd_conf()
31 if (bus->number == cfg->busr.start) { in hisi_pcie_rd_conf()
32 /* access only one slot on each root port */ in hisi_pcie_rd_conf()
46 struct pci_config_window *cfg = bus->sysdata; in hisi_pcie_wr_conf()
49 if (bus->number == cfg->busr.start) { in hisi_pcie_wr_conf()
50 /* access only one slot on each root port */ in hisi_pcie_wr_conf()
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| /linux/arch/arm/mach-mv78xx0/ |
| H A D | pcie.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm/mach-mv78xx0/pcie.c
5 * PCIe functions for Marvell MV78xx0 SoCs
14 #include <plat/pcie.h>
18 #define MV78XX0_MBUS_PCIE_MEM_TARGET(port, lane) ((port) ? 8 : 4) argument
19 #define MV78XX0_MBUS_PCIE_MEM_ATTR(port, lane) (0xf8 & ~(0x10 << (lane))) argument
20 #define MV78XX0_MBUS_PCIE_IO_TARGET(port, lane) ((port) ? 8 : 4) argument
21 #define MV78XX0_MBUS_PCIE_IO_ATTR(port, lane) (0xf0 & ~(0x10 << (lane))) argument
60 pcie_io_space.name = "PCIe I/O Space"; in mv78xx0_pcie_preinit()
63 MV78XX0_PCIE_IO_PHYS_BASE(0) + MV78XX0_PCIE_IO_SIZE * 8 - 1; in mv78xx0_pcie_preinit()
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| /linux/Documentation/devicetree/bindings/net/dsa/ |
| H A D | mscc,ocelot.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vladimir Oltean <vladimir.oltean@nxp.com>
11 - Claudiu Manoil <claudiu.manoil@nxp.com>
12 - Alexandre Belloni <alexandre.belloni@bootlin.com>
13 - UNGLinuxDriver@microchip.com
16 There are multiple switches which are either part of the Ocelot-1 family, or
19 SPI or PCIe. The present DSA binding shall be used when the host controlling
20 them performs packet I/O primarily through an Ethernet port of the switch
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