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/linux/drivers/pci/controller/
H A Dpcie-rcar-host.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe driver for Renesas R-Car SoCs
4 * Copyright (C) 2014-2020 Renesas Electronics Europe Ltd
7 * arch/sh/drivers/pci/pcie-sh7786.c
8 * arch/sh/drivers/pci/ops-sh7786.c
9 * Copyright (C) 2009 - 2011 Paul Mundt
17 #include <linux/clk-provider.h>
21 #include <linux/irqchip/irq-msi-lib.h>
36 #include "pcie-rcar.h"
47 /* Structure representing the PCIe interface */
[all …]
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
11 tristate "Aardvark PCIe controller"
18 Add support for Aardvark 64bit PCIe Host Controller. This
23 tristate "Altera PCIe controller"
26 Say Y here if you want to enable PCIe controller support on Altera
30 tristate "Altera PCIe MSI feature"
35 Say Y here if you want PCIe MS
[all...]
H A Dpcie-mediatek.c1 // SPDX-License-Identifier: GPL-2.0
3 * MediaTek PCIe host controller driver.
15 #include <linux/irqchip/irq-msi-lib.h>
33 /* PCIe shared registers */
39 /* PCIe per port registers */
45 #define PCIE_PORT_PERST(x) BIT(1
190 struct mtk_pcie *pcie; global() member
226 mtk_pcie_subsys_powerdown(struct mtk_pcie * pcie) mtk_pcie_subsys_powerdown() argument
238 struct mtk_pcie *pcie = port->pcie; mtk_pcie_port_free() local
246 mtk_pcie_put_resources(struct mtk_pcie * pcie) mtk_pcie_put_resources() argument
340 struct mtk_pcie *pcie = bus->sysdata; mtk_pcie_find_port() local
522 mtk_pcie_irq_teardown(struct mtk_pcie * pcie) mtk_pcie_irq_teardown() argument
629 struct mtk_pcie *pcie = port->pcie; mtk_pcie_setup_irq() local
656 struct mtk_pcie *pcie = port->pcie; mtk_pcie_startup_port_v2() local
657 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie); mtk_pcie_startup_port_v2() local
750 struct mtk_pcie *pcie = bus->sysdata; mtk_pcie_map_bus() local
766 struct mtk_pcie *pcie = port->pcie; mtk_pcie_startup_port() local
826 struct mtk_pcie *pcie = port->pcie; mtk_pcie_enable_port() local
905 mtk_pcie_parse_port(struct mtk_pcie * pcie,struct device_node * node,int slot) mtk_pcie_parse_port() argument
985 mtk_pcie_subsys_powerup(struct mtk_pcie * pcie) mtk_pcie_subsys_powerup() argument
1037 mtk_pcie_setup(struct mtk_pcie * pcie) mtk_pcie_setup() argument
1081 struct mtk_pcie *pcie; mtk_pcie_probe() local
1082 struct pci_host_bridge *host; mtk_pcie_probe() local
1118 mtk_pcie_free_resources(struct mtk_pcie * pcie) mtk_pcie_free_resources() argument
1120 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie); mtk_pcie_free_resources() local
1128 struct mtk_pcie *pcie = platform_get_drvdata(pdev); mtk_pcie_remove() local
1129 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie); mtk_pcie_remove() local
1142 struct mtk_pcie *pcie = dev_get_drvdata(dev); mtk_pcie_suspend_noirq() local
1166 struct mtk_pcie *pcie = dev_get_drvdata(dev); mtk_pcie_resume_noirq() local
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H A Dpcie-mediatek-gen3.c1 // SPDX-License-Identifier: GPL-2.0
3 * MediaTek PCIe host controller driver.
11 #include <linux/clk-provider.h>
15 #include <linux/irqchip/irq-msi-lib.h>
61 #define PCIE_PHY_RSTB BIT(1)
79 #define PCIE_MSI_ENABLE GENMASK(PCIE_MSI_SET_NUM + 8 - 1, 8)
83 GENMASK(PCIE_INTX_SHIFT + PCI_NUM_INTX - 1, PCIE_INTX_SHIFT)
87 #define PCIE_MSI_SET_ENABLE GENMASK(PCIE_MSI_SET_NUM - 1, 0)
112 #define PCIE_DISABLE_DVFSRC_VLT_REQ BIT(1)
124 (((((size) - 1) << 1) & GENMASK(6, 1)) | PCIE_ATR_EN)
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H A Dpcie-rcar.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe driver for Renesas R-Car SoCs
4 * Copyright (C) 2014-2020 Renesas Electronics Europe Ltd
12 #include "pcie-rcar.h"
14 void rcar_pci_write_reg(struct rcar_pcie *pcie, u32 val, unsigned int reg) in rcar_pci_write_reg() argument
16 writel(val, pcie->base + reg); in rcar_pci_write_reg()
19 u32 rcar_pci_read_reg(struct rcar_pcie *pcie, unsigned int reg) in rcar_pci_read_reg() argument
21 return readl(pcie->base + reg); in rcar_pci_read_reg()
24 void rcar_rmw32(struct rcar_pcie *pcie, int where, u32 mask, u32 data) in rcar_rmw32() argument
27 u32 val = rcar_pci_read_reg(pcie, where & ~3); in rcar_rmw32()
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/linux/Documentation/devicetree/bindings/pci/
H A Dhost-generic-pci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/host-generic-pci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic PCI host controller
10 - Will Deacon <will@kernel.org>
13 Firmware-initialised PCI host controllers and PCI emulations, such as the
14 virtio-pci implementations found in kvmtool and other para-virtualised
21 Configuration Space is assumed to be memory-mapped (as opposed to being
26 For CAM, this 24-bit offset is:
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H A Dti-pci.txt3 PCIe DesignWare Controller
4 - compatible: Should be "ti,dra7-pcie" for RC (deprecated)
5 Should be "ti,dra7-pcie-ep" for EP (deprecated)
6 Should be "ti,dra746-pcie-rc" for dra74x/dra76 in RC mode
7 Should be "ti,dra746-pcie-ep" for dra74x/dra76 in EP mode
8 Should be "ti,dra726-pcie-rc" for dra72x in RC mode
9 Should be "ti,dra726-pcie-ep" for dra72x in EP mode
10 - phys : list of PHY specifiers (used by generic PHY framework)
11 - phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
13 - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",
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H A Dapple,pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/apple,pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Apple PCIe host controller
10 - Mark Kettenis <kettenis@openbsd.org>
13 The Apple PCIe host controller is a PCIe host controller with
16 The controller incorporates Synopsys DesigWare PCIe logic to
18 PCIe host bridges is absent.
26 the standard "reset-gpios" and "max-link-speed" properties appear on
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H A Drcar-pci-host.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pci/rcar-pci-host.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Renesas R-Car PCIe Host
11 - Marek Vasut <marek.vasut+renesas@gmail.com>
12 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
15 - $ref: /schemas/pci/pci-host-bridge.yaml#
20 - const: renesas,pcie-r8a7779 # R-Car H1
21 - items:
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H A Dmediatek,mt7621-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/mediatek,mt7621-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek MT7621 PCIe controller
10 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
13 MediaTek MT7621 PCIe subsys supports a single Root Complex (RC)
14 with 3 Root Ports. Each Root Port supports a Gen1 1-lane Link
16 MT7621 PCIe HOST Topology
18 .-------.
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H A Dti,am65-pci-host.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/pci/ti,am65-pci-host.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: TI AM65 PCI Host
11 - Kishon Vijay Abraham I <kishon@ti.com>
14 - $ref: /schemas/pci/pci-host-bridge.yaml#
19 - ti,am654-pcie-rc
20 - ti,keystone-pcie
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H A Dbrcm,stb-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/brcm,stb-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Brcmstb PCIe Host Controller
10 - Jim Quinlan <james.quinlan@broadcom.com>
15 - enum:
16 - brcm,bcm2711-pcie # The Raspberry Pi 4
17 - brcm,bcm2712-pcie # Raspberry Pi 5
18 - brcm,bcm4908-pcie
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H A Daxis,artpec6-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pci/axis,artpec6-pcie.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Axis ARTPEC-6 PCIe host controller
11 - Jesper Nilsson <jesper.nilsson@axis.com>
14 This PCIe host controller is based on the Synopsys DesignWare PCIe IP.
21 - axis,artpec6-pcie
22 - axis,artpec6-pcie-ep
23 - axis,artpec7-pcie
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H A Damazon,al-alpine-v3-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/amazon,al-alpine-v3-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Amazon Annapurna Labs Alpine v3 PCIe Host Bridge
10 - Jonathan Chocron <jonnyc@amazon.com>
13 Amazon's Annapurna Labs PCIe Host Controller is based on the Synopsys
17 - $ref: snps,dw-pcie.yaml#
22 - amazon,al-alpine-v2-pcie
23 - amazon,al-alpine-v3-pcie
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H A Dsamsung,exynos-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/samsung,exynos-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung SoC series PCIe Host Controller
10 - Marek Szyprowski <m.szyprowski@samsung.com>
11 - Jaehoon Chung <jh80.chung@samsung.com>
14 Exynos5433 SoC PCIe host controller is based on the Synopsys DesignWare
15 PCIe IP and thus inherits all the common properties defined in
16 snps,dw-pcie.yaml.
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H A Damd,versal2-mdb-host.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/amd,versal2-mdb-host.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: AMD Versal2 MDB(Multimedia DMA Bridge) Host Controller
10 - Thippeswamy Havalige <thippeswamy.havalige@amd.com>
13 - $ref: /schemas/pci/pci-host-bridge.yaml#
14 - $ref: /schemas/pci/snps,dw-pcie.yaml#
18 const: amd,versal2-mdb-host
22 - description: MDB System Level Control and Status Register (SLCR) Base
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/linux/Documentation/admin-guide/
H A Dthunderbolt.rst1 .. SPDX-License-Identifier: GPL-2.0
8 manager is an entity running on the host router (host controller)
19 ``user`` which means PCIe tunneling is disabled by default. The
25 -----------------------------------
27 should be a userspace tool that handles all the low-level details, keeps
31 found in Documentation/ABI/testing/sysfs-bus-thunderbolt.
35 ``/etc/udev/rules.d/99-local.rules``::
37 ACTION=="add", SUBSYSTEM=="thunderbolt", ATTR{authorized}=="0", ATTR{authorized}="1"
46 be DMA masters and thus read contents of the host memory without CPU and OS
50 Some USB4 systems have a BIOS setting to disable PCIe tunneling. This is
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/linux/Documentation/devicetree/bindings/phy/
H A Dnvidia,tegra210-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
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H A Dnvidia,tegra124-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra124-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
/linux/Documentation/nvme/
H A Dnvme-pci-endpoint-target.rst1 .. SPDX-License-Identifier: GPL-2.0
9 The NVMe PCI endpoint function target driver implements an NVMe PCIe controller
16 controller over a PCIe link, thus implementing an NVMe PCIe device similar to a
21 files or block devices, or can use NVMe passthrough to expose to the PCI host an
22 existing physical NVMe device or an NVMe fabrics host controller (e.g. a NVMe
23 TCP host controller).
26 NVMe target core code to parse and execute NVMe commands submitted by the PCIe
27 host. However, using the PCI endpoint framework API and DMA API, the driver is
28 also responsible for managing all data transfers over the PCIe link. This
32 1) The driver manages retrieval of NVMe commands in submission queues using DMA
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/linux/Documentation/misc-devices/
H A Dspear-pcie-gadget.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Spear PCIe Gadget Driver
24 PCIe gadget support for SPEAr13XX platform
29 Its main purpose is to configure selected dual mode PCIe controller as device
31 type. This driver can be used to show spear's PCIe device capability.
37 -----------------------
42 no_of_msi zero if MSI is not enabled by host. A positive value is the
53 ------------------------
61 inta write 1 to assert INTA and 0 to de-assert.
78 Program all PCIe registers in such a way that when this device is connected
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/linux/drivers/pci/controller/cadence/
H A Dpcie-sg2042.c1 // SPDX-License-Identifier: GPL-2.0
3 * pcie-sg2042 - PCIe controller driver for Sophgo SG2042 SoC
14 #include "pcie-cadence.h"
17 * SG2042 only supports 4-byt
39 struct cdns_pcie *pcie; sg2042_pcie_probe() local
76 struct cdns_pcie *pcie = platform_get_drvdata(pdev); sg2042_pcie_remove() local
90 struct cdns_pcie *pcie = dev_get_drvdata(dev); sg2042_pcie_suspend_noirq() local
99 struct cdns_pcie *pcie = dev_get_drvdata(dev); sg2042_pcie_resume_noirq() local
[all...]
H A Dpci-j721e.c1 // SPDX-License-Identifier: GPL-2.0
3 * pci-j721e - PCIe controller driver for TI's J721E SoCs
5 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
10 #include <linux/clk-provider.h>
26 #include "pcie-cadenc
83 j721e_pcie_user_readl(struct j721e_pcie * pcie,u32 offset) j721e_pcie_user_readl() argument
88 j721e_pcie_user_writel(struct j721e_pcie * pcie,u32 offset,u32 value) j721e_pcie_user_writel() argument
94 j721e_pcie_intd_readl(struct j721e_pcie * pcie,u32 offset) j721e_pcie_intd_readl() argument
99 j721e_pcie_intd_writel(struct j721e_pcie * pcie,u32 offset,u32 value) j721e_pcie_intd_writel() argument
107 struct j721e_pcie *pcie = priv; j721e_pcie_link_irq_handler() local
121 j721e_pcie_disable_link_irq(struct j721e_pcie * pcie) j721e_pcie_disable_link_irq() argument
130 j721e_pcie_config_link_irq(struct j721e_pcie * pcie) j721e_pcie_config_link_irq() argument
141 struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev); j721e_pcie_start_link() local
153 struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev); j721e_pcie_stop_link() local
163 struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev); j721e_pcie_link_up() local
176 j721e_pcie_set_mode(struct j721e_pcie * pcie,struct regmap * syscon,unsigned int offset) j721e_pcie_set_mode() argument
195 j721e_pcie_set_link_speed(struct j721e_pcie * pcie,struct regmap * syscon,unsigned int offset) j721e_pcie_set_link_speed() argument
216 j721e_pcie_set_lane_count(struct j721e_pcie * pcie,struct regmap * syscon,unsigned int offset) j721e_pcie_set_lane_count() argument
236 j721e_enable_acspcie_refclk(struct j721e_pcie * pcie,struct regmap * syscon) j721e_enable_acspcie_refclk() argument
266 j721e_pcie_ctrl_init(struct j721e_pcie * pcie) j721e_pcie_ctrl_init() argument
477 struct j721e_pcie *pcie; j721e_pcie_probe() local
666 struct j721e_pcie *pcie = platform_get_drvdata(pdev); j721e_pcie_remove() local
691 struct j721e_pcie *pcie = dev_get_drvdata(dev); j721e_pcie_suspend_noirq() local
705 struct j721e_pcie *pcie = dev_get_drvdata(dev); j721e_pcie_resume_noirq() local
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/linux/Documentation/PCI/endpoint/
H A Dpci-ntb-howto.rst1 .. SPDX-License-Identifier: GPL-2.0
4 PCI Non-Transparent Bridge (NTB) Endpoint Function (EPF) User Guide
9 This document is a guide to help users use pci-epf-ntb function driver
10 and ntb_hw_epf host driver for NTB functionality. The list of steps to
11 be followed in the host side and EP side is given below. For the hardware
13 Documentation/PCI/endpoint/pci-ntb-function.rst
19 ---------------------------
27 2900000.pcie-ep 2910000.pcie-ep
32 2900000.pcie-ep 2910000.pcie-ep
36 -------------------------
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/linux/arch/powerpc/sysdev/
H A Dfsl_pci.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * MPC83xx/85xx/86xx PCI/PCIE support routing.
5 * Copyright 2007-2012 Freescale Semiconductor, Inc.
6 * Copyright 2008-2009 MontaVista Software, Inc.
11 * Roy Zang <tie-fei.zang@freescale.com>
12 * MPC83xx PCI-Express support:
34 #include <asm/pci-bridge.h>
35 #include <asm/ppc-pci.h>
39 #include <asm/ppc-opcode.h>
51 /* if we aren't a PCIe don't bother */ in quirk_fsl_pcie_early()
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