/freebsd/sys/contrib/device-tree/Bindings/clock/ |
H A D | mvebu-gated-clock.txt | 12 ----------------------------------- 14 1 pex0_en PCIe 0 Clock out 15 2 pex1_en PCIe 1 Clock out 16 3 ge1 Gigabit Ethernet 1 18 5 pex0 PCIe Cntrl 0 19 9 pex1 PCIe Cntrl 1 20 15 sata0 SATA Host 0 21 17 sdio SDHCI Host 25 30 sata1 SATA Host 0 29 ----------------------------------- [all …]
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/freebsd/sys/contrib/device-tree/Bindings/pci/ |
H A D | ti,j721e-pci-host.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ 4 --- [all...] |
H A D | host-generic-pci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pci/host-generic-pci.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Generic PCI host controller 10 - Will Deacon <will@kernel.org> 13 Firmware-initialised PCI host controllers and PCI emulations, such as the 14 virtio-pci implementations found in kvmtool and other para-virtualised 21 Configuration Space is assumed to be memory-mapped (as opposed to being 26 For CAM, this 24-bit offset is: [all …]
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H A D | uniphier-pcie.txt | 1 Socionext UniPhier PCIe host controller bindings 3 This describes the devicetree bindings for PCIe host controller implemented 6 UniPhier PCIe host controller is based on the Synopsys DesignWare PCI core. 7 It shares common functions with the PCIe DesignWare core driver and inherits 9 Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml. 12 - compatible: Should be "socionext,uniphier-pcie". 13 - reg: Specifies offset and length of the register set for the device. 14 According to the reg-names, appropriate register sets are required. 15 - reg-names: Must include the following entries: 16 "dbi" - controller configuration registers [all …]
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H A D | ti-pci.txt | 3 PCIe DesignWare Controller 4 - compatible: Should be "ti,dra7-pcie" for RC (deprecated) 5 Should be "ti,dra7-pcie-ep" for EP (deprecated) 6 Should be "ti,dra746-pcie-rc" for dra74x/dra76 in RC mode 7 Should be "ti,dra746-pcie-ep" for dra74x/dra76 in EP mode 8 Should be "ti,dra726-pcie-rc" for dra72x in RC mode 9 Should be "ti,dra726-pcie-ep" for dra72x in EP mode 10 - phys : list of PHY specifiers (used by generic PHY framework) 11 - phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the 13 - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>", [all …]
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H A D | apple,pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pci/apple,pcie.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Apple PCIe host controller 10 - Mark Kettenis <kettenis@openbsd.org> 13 The Apple PCIe host controller is a PCIe host controller with 16 The controller incorporates Synopsys DesigWare PCIe logic to 18 PCIe host bridges is absent. 22 the standard "reset-gpios" and "max-link-speed" properties appear on [all …]
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H A D | pcie-al.txt | 1 * Amazon Annapurna Labs PCIe host bridge 3 Amazon's Annapurna Labs PCIe Host Controller is based on the Synopsys DesignWare 5 Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml. 7 Properties of the host controller node that differ from it are: 9 - compatible: 13 - "amazon,al-alpine-v2-pcie" for alpine_v2 14 - "amazon,al-alpine-v3-pcie" for alpine_v3 16 - reg: 18 Value type: <prop-encoded-array> 19 Definition: Register ranges as listed in the reg-names property [all …]
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H A D | fsl,imx6q-pcie.txt | 1 * Freescale i.MX6 PCIe interface 3 This PCIe host controller is based on the Synopsys DesignWare PCIe IP 4 and thus inherits all the common properties defined in designware-pcie.txt. 7 - compatible: 8 - "fsl,imx6q-pcie" 9 - "fsl,imx6sx-pcie", 10 - "fsl,imx6qp-pcie" 11 - "fsl,imx7d-pcie" 12 - "fsl,imx8mq-pcie" 13 - reg: base address and length of the PCIe controller [all …]
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H A D | microchip,pcie-host.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pci/microchip,pcie-host.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Microchip PCIe Root Port Bridge Controller 10 - Daire McNamara <daire.mcnamara@microchip.com> 13 - $ref: /schemas/pci/pci-bus.yaml# 14 - $ref: /schemas/interrupt-controller/msi-controller.yaml# 18 const: microchip,pcie-host-1.0 # PolarFire 23 reg-names: [all …]
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H A D | hisilicon-pcie.txt | 1 HiSilicon Hip05 and Hip06 PCIe host bridge DT description 3 HiSilicon PCIe host controller is based on the Synopsys DesignWare PCI core. 4 It shares common functions with the PCIe DesignWare core driver and inherits 6 Documentation/devicetree/bindings/pci/designware-pcie.txt. 11 - compatible: Should contain "hisilicon,hip05-pcie" or "hisilicon,hip06-pcie". 12 - reg: Should contain rc_dbi, config registers location and length. 13 - reg-names: Must include the following entries: 15 "config": PCIe configuration space registers. 16 - msi-parent: Should be its_pcie which is an ITS receiving MSI interrupts. 17 - port-id: Should be 0, 1, 2 or 3. [all …]
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H A D | xilinx-pcie.txt | 1 * Xilinx AXI PCIe Root Port Bridge DT description 4 - #address-cells: Address representation for root ports, set to <3> 5 - #size-cells: Size representation for root ports, set to <2> 6 - #interrupt-cells: specifies the number of cells needed to encode an 7 interrupt source. The value must be 1. 8 - compatible: Should contain "xlnx,axi-pcie-host-1.00.a" 9 - reg: Should contain AXI PCIe registers location and length 10 - device_type: must be "pci" 11 - interrupts: Should contain AXI PCIe interrupt 12 - interrupt-map-mask, [all …]
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H A D | pci.txt | 3 PCI Bus Binding to: IEEE Std 1275-1994 4 https://www.devicetree.org/open-firmware/bindings/pci/pci2_1.pdf 9 https://www.devicetree.org/open-firmware/practice/imap/imap0_9d.pdf 11 Additionally to the properties specified in the above standards a host bridge 14 - linux,pci-domain: 15 If present this property assigns a fixed PCI domain number to a host bridge, 18 host bridges in the system, otherwise potentially conflicting domain numbers 19 may be assigned to root buses behind different host bridges. The domain 20 number for each host bridge in the system must be unique. 21 - max-link-speed: [all …]
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H A D | kirin-pcie.txt | 1 HiSilicon Kirin SoCs PCIe host DT description 3 Kirin PCIe host controller is based on the Synopsys DesignWare PCI core. 4 It shares common functions with the PCIe DesignWare core driver and 6 Documentation/devicetree/bindings/pci/designware-pcie.txt. 11 - compatible: 12 "hisilicon,kirin960-pcie" for PCIe of Kirin960 SoC 13 - reg: Should contain rc_dbi, apb, phy, config registers location and length. 14 - reg-names: Must include the following entries: 18 "config": PCIe configuration space registers. 19 - reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal. [all …]
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H A D | rcar-pci-host.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 4 --- 5 $id: http://devicetree.org/schemas/pci/rcar-pc [all...] |
H A D | xlnx,axi-pcie-host.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pci/xlnx,axi-pcie-host.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Xilinx AXI PCIe Root Port Bridge 10 - Thippeswamy Havalige <thippeswamy.havalige@amd.com> 13 - $ref: /schemas/pci/pci-bus.yaml# 17 const: xlnx,axi-pcie-host-1.00.a 20 maxItems: 1 23 maxItems: 1 [all …]
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H A D | samsung,exynos-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pci/samsung,exynos-pcie.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Samsung SoC series PCIe Host Controller 10 - Marek Szyprowski <m.szyprowski@samsung.com> 11 - Jaehoon Chung <jh80.chung@samsung.com> 14 Exynos5433 SoC PCIe host controller is based on the Synopsys DesignWare 15 PCIe IP and thus inherits all the common properties defined in 16 snps,dw-pcie.yaml. [all …]
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H A D | socionext,uniphier-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pci/socionext,uniphier-pcie.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Socionext UniPhier PCIe host controller 10 UniPhier PCIe host controller is based on the Synopsys DesignWare 11 PCI core. It shares common features with the PCIe DesignWare core and 13 Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml. 16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com> 19 - $ref: /schemas/pci/snps,dw-pcie.yaml# [all …]
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H A D | hisilicon-histb-pcie.txt | 1 HiSilicon STB PCIe host bridge DT description 3 The HiSilicon STB PCIe host controller is based on the DesignWare PCIe core. 4 It shares common functions with the DesignWare PCIe core driver and inherits 6 Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml. 11 - compatible: Should be one of the following strings: 12 "hisilicon,hi3798cv200-pcie" 13 - reg: Should contain sysctl, rc_dbi, config registers location and length. 14 - reg-names: Must include the following entries: 15 "control": control registers of PCIe controller; 16 "rc-dbi": configuration space of PCIe controller; [all …]
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H A D | fsl,imx6q-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Freescale i.MX6 PCIe host controller 10 - Lucas Stach <l.stach@pengutronix.de> 11 - Richard Zhu <hongxing.zhu@nxp.com> 14 This PCIe host controller is based on the Synopsys DesignWare PCIe IP 15 and thus inherits all the common properties defined in snps,dw-pcie.yaml. 19 See fsl,imx6q-pcie-ep.yaml for details on the Endpoint mode device tree [all …]
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H A D | ti,am65-pci-host.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 # Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/ 4 --- 5 $id: http://devicetree.org/schemas/pci/ti,am65-pci-host.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 title: TI AM65 PCI Host 11 - Kishon Vijay Abraham I <kishon@ti.com> 14 - $ref: /schemas/pci/pci-bus.yaml# 19 - ti,am654-pcie-rc 20 - ti,keystone-pcie [all …]
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H A D | toshiba,visconti-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pci/toshiba,visconti-pci [all...] |
/freebsd/sys/contrib/device-tree/Bindings/phy/ |
H A D | nvidia,tegra210-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xus [all...] |
H A D | nvidia,tegra124-xusb-padctl.txt | 11 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or 12 super-speed USB. Other lanes are for various types of low-speed, full-speed 13 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller 14 contains a software-configurable mux that sits between the I/O controller 15 ports (e.g. PCIe) and the lanes. 17 In addition to per-lane configuration, USB 3.0 ports may require additional 18 settings on a per-board basis. 20 Pads will be represented as children of the top-level XUSB pad controller 23 PHY bindings, as described by the phy-bindings.txt file in this directory. 34 -------------------- [all …]
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H A D | nvidia,tegra124-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/phy/nvidia,tegra124-xusb-padctl.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or 22 super-speed USB. Other lanes are for various types of low-speed, full-speed 23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller 24 contains a software-configurable mux that sits between the I/O controller [all …]
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/freebsd/share/misc/ |
H A D | pci_vendors | 5 # Date: 2024-09-20 03:15:02 8 # the PCI ID Project at https://pci-ids.ucw.cz/. 14 # (version 2 or higher) or the 3-clause BSD License. 25 # device device_name <-- single tab 26 # subvendor subdevice subsystem_name <-- two tabs 30 # This is a relabelled RTL-8139 31 8139 AT-2500TX V3 Ethernet 41 7a09 PCI-to-PCI Bridge 49 7a19 PCI-to-PCI Bridge 53 7a29 PCI-to-PCI Bridge [all …]
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