1*c66ec88fSEmmanuel VadotHiSilicon Hip05 and Hip06 PCIe host bridge DT description 2*c66ec88fSEmmanuel Vadot 3*c66ec88fSEmmanuel VadotHiSilicon PCIe host controller is based on the Synopsys DesignWare PCI core. 4*c66ec88fSEmmanuel VadotIt shares common functions with the PCIe DesignWare core driver and inherits 5*c66ec88fSEmmanuel Vadotcommon properties defined in 6*c66ec88fSEmmanuel VadotDocumentation/devicetree/bindings/pci/designware-pcie.txt. 7*c66ec88fSEmmanuel Vadot 8*c66ec88fSEmmanuel VadotAdditional properties are described here: 9*c66ec88fSEmmanuel Vadot 10*c66ec88fSEmmanuel VadotRequired properties 11*c66ec88fSEmmanuel Vadot- compatible: Should contain "hisilicon,hip05-pcie" or "hisilicon,hip06-pcie". 12*c66ec88fSEmmanuel Vadot- reg: Should contain rc_dbi, config registers location and length. 13*c66ec88fSEmmanuel Vadot- reg-names: Must include the following entries: 14*c66ec88fSEmmanuel Vadot "rc_dbi": controller configuration registers; 15*c66ec88fSEmmanuel Vadot "config": PCIe configuration space registers. 16*c66ec88fSEmmanuel Vadot- msi-parent: Should be its_pcie which is an ITS receiving MSI interrupts. 17*c66ec88fSEmmanuel Vadot- port-id: Should be 0, 1, 2 or 3. 18*c66ec88fSEmmanuel Vadot 19*c66ec88fSEmmanuel VadotOptional properties: 20*c66ec88fSEmmanuel Vadot- status: Either "ok" or "disabled". 21*c66ec88fSEmmanuel Vadot- dma-coherent: Present if DMA operations are coherent. 22*c66ec88fSEmmanuel Vadot 23*c66ec88fSEmmanuel VadotHip05 Example (note that Hip06 is the same except compatible): 24*c66ec88fSEmmanuel Vadot pcie@b0080000 { 25*c66ec88fSEmmanuel Vadot compatible = "hisilicon,hip05-pcie", "snps,dw-pcie"; 26*c66ec88fSEmmanuel Vadot reg = <0 0xb0080000 0 0x10000>, <0x220 0x00000000 0 0x2000>; 27*c66ec88fSEmmanuel Vadot reg-names = "rc_dbi", "config"; 28*c66ec88fSEmmanuel Vadot bus-range = <0 15>; 29*c66ec88fSEmmanuel Vadot msi-parent = <&its_pcie>; 30*c66ec88fSEmmanuel Vadot #address-cells = <3>; 31*c66ec88fSEmmanuel Vadot #size-cells = <2>; 32*c66ec88fSEmmanuel Vadot device_type = "pci"; 33*c66ec88fSEmmanuel Vadot dma-coherent; 34*c66ec88fSEmmanuel Vadot ranges = <0x82000000 0 0x00000000 0x220 0x00000000 0 0x10000000>; 35*c66ec88fSEmmanuel Vadot num-lanes = <8>; 36*c66ec88fSEmmanuel Vadot port-id = <1>; 37*c66ec88fSEmmanuel Vadot #interrupt-cells = <1>; 38*c66ec88fSEmmanuel Vadot interrupt-map-mask = <0xf800 0 0 7>; 39*c66ec88fSEmmanuel Vadot interrupt-map = <0x0 0 0 1 &mbigen_pcie 1 10 40*c66ec88fSEmmanuel Vadot 0x0 0 0 2 &mbigen_pcie 2 11 41*c66ec88fSEmmanuel Vadot 0x0 0 0 3 &mbigen_pcie 3 12 42*c66ec88fSEmmanuel Vadot 0x0 0 0 4 &mbigen_pcie 4 13>; 43*c66ec88fSEmmanuel Vadot }; 44