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/freebsd/sys/contrib/device-tree/src/arm/st/
H A Dspear600.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
7 #address-cells = <1>;
8 #size-cells = <1>;
12 #address-cells = <0>;
13 #size-cells = <0>;
16 compatible = "arm,arm926ej-s";
27 #address-cells = <1>;
28 #size-cells = <1>;
29 compatible = "simple-bus";
32 vic0: interrupt-controller@f1100000 {
[all …]
H A Dspear320.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
12 #address-cells = <1>;
13 #size-cells = <1>;
14 compatible = "simple-bus";
19 compatible = "st,spear320-pinmux";
21 #gpio-range-cells = <3>;
28 interrupt-parent = <&shirq>;
33 compatible = "st,spear600-fsmc-nand";
34 #address-cells = <1>;
35 #size-cells = <1>;
[all …]
H A Dspear310.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
12 #address-cells = <1>;
13 #size-cells = <1>;
14 compatible = "simple-bus";
20 compatible = "st,spear310-pinmux";
22 #gpio-range-cells = <3>;
26 compatible = "st,spear600-fsmc-nand";
27 #address-cells = <1>;
28 #size-cells = <1>;
30 0x40000000 0x0010 /* NAND Base DATA */
[all …]
H A Dspear300.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
12 #address-cells = <1>;
13 #size-cells = <1>;
14 compatible = "simple-bus";
19 compatible = "st,spear300-pinmux";
31 compatible = "st,spear600-fsmc-nand";
32 #address-cells = <1>;
33 #size-cells = <1>;
35 0x80000000 0x0010 /* NAND Base DATA */
36 0x80020000 0x0010 /* NAND Base ADDR */
[all …]
/freebsd/sys/contrib/device-tree/Bindings/net/dsa/
H A Dmarvell.txt2 ----------
[all...]
/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dloongson,pch-pic.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/loongson,pch-pic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jiaxun Yang <jiaxun.yang@flygoat.com>
13 This interrupt controller is found in the Loongson LS7A family of PCH for
14 transforming interrupts from on-chip devices into HyperTransport vectorized
19 const: loongson,pch-pic-1.0
24 loongson,pic-base-vec:
26 u32 value of the base of parent HyperTransport vector allocated
[all …]
H A Dsocionext,synquacer-exiu.txt1 Socionext SynQuacer External Interrupt Unit (EXIU)
3 The Socionext Synquacer SoC has an external interrupt unit (EXIU)
5 level-high type GICv3 SPIs.
9 - compatible : Should be "socionext,synquacer-exiu".
10 - reg : Specifies base physical address and size of the
12 - interrupt-controller : Identifies the node as an interrupt controller.
13 - #interrupt-cells : Specifies the number of cells needed to encode an
14 interrupt source. The value must be 3.
15 - socionext,spi-base : The SPI number of the first SPI of the 32 adjacent
20 - Only SPIs can use the EXIU as an interrupt parent.
[all …]
H A Dloongson,pch-msi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/loongson,pch-msi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jiaxun Yang <jiaxun.yang@flygoat.com>
13 This interrupt controller is found in the Loongson LS7A family of PCH for
19 const: loongson,pch-msi-1.0
24 loongson,msi-base-vec:
26 u32 value of the base of parent HyperTransport vector allocated
32 loongson,msi-num-vecs:
[all …]
H A Dfsl,ls-scfg-msi.txt5 - compatible: should be "fsl,<soc-name>-msi" to identify
7 "fsl,ls1021a-msi"
8 "fsl,ls1043a-msi"
9 "fsl,ls1046a-msi"
10 "fsl,ls1043a-v1.1-msi"
11 "fsl,ls1012a-msi"
12 - msi-controller: indicates that this is a PCIe MSI controller node
13 - reg: physical base address of the controller and length of memory mapped.
14 - interrupts: an interrupt to the parent interrupt controller.
16 This interrupt controller hardware is a second level interrupt controller that
[all …]
H A Dti,sci-intr.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/ti,sci-intr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Texas Instruments K3 Interrupt Router
10 - Lokesh Vutla <lokeshvutla@ti.com>
13 - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
16 The Interrupt Router (INTR) module provides a mechanism to mux M
17 interrupt inputs to N interrupt outputs, where all M inputs are selectable
18 to be driven per N output. An Interrupt Router can either handle edge
[all …]
H A Dbrcm,bcm6345-l1-intc.txt1 Broadcom BCM6345-style Level 1 interrupt controller
3 This block is a first level interrupt controller that is typically connected
8 - 32, 64 or 128 incoming level IRQ lines
10 - Most onchip peripherals are wired directly to an L1 input
12 - A separate instance of the register set for each CPU, allowing individual
15 - Contains one or more enable/status word pairs per CPU
17 - No atomic set/clear operations
19 - No polarity/level/edge settings
21 - No FIFO or priority encoder logic; software is expected to read all
22 2-4 status words to determine which IRQs are pending
[all …]
H A Dabilis,tb10x-ictl.txt1 TB10x Top Level Interrupt Controller
4 The Abilis TB10x SOC contains a custom interrupt controller. It performs
5 one-to-one mapping of external interrupt sources to CPU interrupts and
9 -------------------
11 - compatible: Should be "abilis,tb10x-ictl"
12 - reg: specifies physical base address and size of register range.
13 - interrupt-congroller: Identifies the node as an interrupt controller.
14 - #interrupt cells: Specifies the number of cells used to encode an interrupt
16 - interrupts: Specifies the list of interrupt lines which are handled by
17 the interrupt controller in the parent controller's notation. Interrupts
[all …]
/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Daltera-pcie.txt4 - compatible : should contain "altr,pcie-root-port-1.0" or "altr,pcie-root-port-2.0"
5 - reg: a list of physical base address and length for TXS and CRA.
6 For "altr,pcie-root-port-2.0", additional HIP base address and length.
7 - reg-names: must include the following entries:
10 "Hip": Hard IP region (if "altr,pcie-root-port-2.0")
11 - interrupts: specifies the interrupt source of the parent interrupt
12 controller. The format of the interrupt specifier depends
13 on the parent interrupt controller.
14 - device_type: must be "pci"
15 - #address-cells: set to <3>
[all …]
/freebsd/sys/contrib/device-tree/src/riscv/microchip/
H A Dmpfs.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
4 /dts-v1/;
5 #include "dt-bindings/clock/microchip,mpfs-clock.h"
8 #address-cells = <2>;
9 #size-cells = <2>;
14 #address-cells = <1>;
15 #size-cells = <0>;
16 timebase-frequency = <1000000>;
21 i-cache-block-size = <64>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/arm/
H A Dcci.txt5 ARM multi-cluster systems maintain intra-cluster coherency through a
19 Node's parent must be the root node /, and the address space visible
24 - compatible
28 "arm,cci-400"
29 "arm,cci-500"
30 "arm,cci-550"
32 - reg
35 of cells, containing base and size.
36 Definition: A standard property. Specifies base physical
40 - ranges:
[all …]
/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Dsamsung-pinctrl.txt6 on-chip controllers onto these pads.
9 - compatible: should be one of the following.
10 - "samsung,s3c2412-pinctrl": for S3C2412-compatible pin-controller,
11 - "samsung,s3c2416-pinctrl": for S3C2416-compatible pin-controller,
12 - "samsung,s3c2440-pinctrl": for S3C2440-compatible pin-controller,
13 - "samsung,s3c2450-pinctrl": for S3C2450-compatible pin-controller,
14 - "samsung,s3c64xx-pinctrl": for S3C64xx-compatible pin-controller,
15 - "samsung,s5pv210-pinctrl": for S5PV210-compatible pin-controller,
16 - "samsung,exynos3250-pinctrl": for Exynos3250 compatible pin-controller.
17 - "samsung,exynos4210-pinctrl": for Exynos4210 compatible pin-controller.
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/broadcom/northstar2/
H A Dns2.dtsi35 #include <dt-bindings/interrupt-controller/arm-gic.h>
36 #include <dt-bindings/clock/bcm-ns2.h>
40 interrupt-parent = <&gic>;
41 #address-cells = <2>;
42 #size-cells = <2>;
45 #address-cells = <2>;
46 #size-cells = <0>;
50 compatible = "arm,cortex-a57";
52 enable-method = "psci";
53 next-level-cache = <&CLUSTER0_L2>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/gpio/
H A Dsocionext,uniphier-gpio.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/gpio/socionext,uniphier-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Masahiro Yamada <yamada.masahiro@socionext.com>
14 pattern: "^gpio@[0-9a-f]+$"
17 const: socionext,uniphier-gpio
22 gpio-controller: true
24 "#gpio-cells":
27 interrupt-controller: true
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/marvell/
H A Darmada-ap80x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/thermal.h>
11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cells = <2>;
25 compatible = "arm,psci-0.2";
29 reserved-memory {
30 #address-cells = <2>;
31 #size-cells = <2>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/display/tegra/
H A Dnvidia,tegra20-host1x.txt4 - compatible: "nvidia,tegra<chip>-host1x"
5 - reg: Physical base address and length of the controller's registers.
6 For pre-Tegra186, one entry describing the whole register area.
7 For Tegra186, one entry for each entry in reg-names:
8 "vm" - VM region assigned to Linux
9 "hypervisor" - Hypervisor region (only if Linux acts as hypervisor)
10 - interrupts: The interrupt outputs from the controller.
11 - #address-cells: The number of cells used to represent physical base addresses
13 - #size-cells: The number of cells used to represent the size of an address
15 - ranges: The mapping of the host1x address space to the CPU address space.
[all …]
/freebsd/sys/contrib/device-tree/src/loongarch/
H A Dloongson-2k2000.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/clock/loongson,ls2k-clk.h>
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <1>;
17 #size-cells = <0>;
34 ref_100m: clock-ref-100m {
35 compatible = "fixed-clock";
[all …]
/freebsd/sys/contrib/device-tree/src/powerpc/
H A Dsbc8548-post.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
12 #address-cells = <1>;
13 #size-cells = <1>;
16 bus-frequency = <0>;
17 compatible = "simple-bus";
19 ecm-law@0 {
20 compatible = "fsl,ecm-law";
22 fsl,num-laws = <10>;
26 compatible = "fsl,mpc8548-ecm", "fsl,ecm";
29 interrupt-parent = <&mpic>;
[all …]
H A Dtqm8541.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /dts-v1/;
15 #address-cells = <1>;
16 #size-cells = <1>;
27 #address-cells = <1>;
28 #size-cells = <0>;
33 d-cache-line-size = <32>;
34 i-cache-line-size = <32>;
35 d-cache-size = <32768>;
36 i-cache-size = <32768>;
[all …]
H A Dtqm8555.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /dts-v1/;
15 #address-cells = <1>;
16 #size-cells = <1>;
27 #address-cells = <1>;
28 #size-cells = <0>;
33 d-cache-line-size = <32>;
34 i-cache-line-size = <32>;
35 d-cache-size = <32768>;
36 i-cache-size = <32768>;
[all …]
H A Dtqm8540.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /dts-v1/;
15 #address-cells = <1>;
16 #size-cells = <1>;
28 #address-cells = <1>;
29 #size-cells = <0>;
34 d-cache-line-size = <32>;
35 i-cache-line-size = <32>;
36 d-cache-size = <32768>;
37 i-cache-size = <32768>;
[all …]

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