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/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dnvidia,tegra124-car.txt1 NVIDIA Tegra124 and Tegra132 Clock And Reset Controller
3 This binding uses the common clock binding:
4 Documentation/devicetree/bindings/clock/clock-bindings.txt
6 The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
10 - compatible : Should be "nvidia,tegra124-car" or "nvidia,tegra132-car"
11 - reg : Should contain CAR registers location and length
12 - clocks : Should contain phandle and clock specifiers for two clocks:
13 the 32 KHz "32k_in", and the board-specific oscillator "osc".
14 - #clock-cells : Should be 1.
15 In clock consumers, this cell represents the clock ID exposed by the
[all …]
H A Dnvidia,tegra124-car.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/nvidia,tegra124-ca
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H A Dqoriq-clock.txt1 * Clock Block on Freescale QorIQ Platforms
4 SYSCLK signal. The SYSCLK input (frequency) is multiplied using
14 --------------- -------------
18 1. Clock Block Binding
21 - compatible: Should contain a chip-specific clock block compatible
22 string and (if applicable) may contain a chassis-version clock
25 Chip-specific strings are of the form "fsl,<chip>-clockgen", such as:
26 * "fsl,p2041-clockgen"
27 * "fsl,p3041-clockgen"
28 * "fsl,p4080-clockgen"
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/freebsd/sys/dev/qcom_clk/
H A Dqcom_clk_rcg2.c1 /*-
52 ((sc)->cmd_rcgr + (sc)->cfg_offset + QCOM_CLK_RCG2_CFG_REG)
54 ((sc)->cmd_rcgr + QCOM_CLK_RCG2_CMD_REG)
56 ((sc)->cmd_rcgr + (sc)->cfg_offset + QCOM_CLK_RCG2_M_REG)
58 ((sc)->cmd_rcgr + (sc)->cfg_offset + QCOM_CLK_RCG2_N_REG)
60 ((sc)->cmd_rcgr + (sc)->cfg_offset + QCOM_CLK_RCG2_D_REG)
76 * Finish a clock update.
88 CLKDEV_READ_4(clknode_get_device(sc->clknode), in qcom_clk_rcg2_update_config_locked()
91 CLKDEV_WRITE_4(clknode_get_device(sc->clknode), in qcom_clk_rcg2_update_config_locked()
99 CLKDEV_READ_4(clknode_get_device(sc->clknode), in qcom_clk_rcg2_update_config_locked()
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/freebsd/sys/contrib/device-tree/src/arm/nvidia/
H A Dtegra124-apalis-emc.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR X11
3 * Copyright 2016-2019 Toradex AG
7 #include <dt-bindings/clock/tegra124-car.h>
10 clock@60006000 {
11 emc-timings-1 {
12 nvidia,ram-code = <1>;
14 timing-12750000 {
15 clock-frequency = <12750000>;
16 nvidia,parent-clock-frequency = <408000000>;
18 clock-names = "emc-parent";
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H A Dtegra124-jetson-tk1-emc.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/tegra124-car.h>
6 clock@60006000 {
7 emc-timings-3 {
8 nvidia,ram-code = <3>;
10 timing-12750000 {
11 clock-frequency = <12750000>;
12 nvidia,parent-clock-frequency = <408000000>;
14 clock-names = "emc-parent";
17 timing-20400000 {
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H A Dtegra124-nyan-blaze-emc.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/tegra124-car.h>
6 clock@60006000 {
7 emc-timings-1 {
8 nvidia,ram-code = <1>;
10 timing-12750000 {
11 clock-frequency = <12750000>;
12 nvidia,parent-clock-frequency = <408000000>;
14 clock-names = "emc-parent";
17 timing-20400000 {
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/freebsd/sys/contrib/device-tree/src/nios2/
H A D10m50_devboard.dts1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
10 compatible = "altr,niosii-max10";
11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
20 compatible = "altr,nios2-1.1";
22 interrupt-controller;
23 #interrupt-cells = <1>;
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/freebsd/sys/contrib/device-tree/src/powerpc/
H A Dmpc836x_rdk.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright 2007-2008 MontaVista Software, Inc.
11 /dts-v1/;
14 #address-cells = <1>;
15 #size-cells = <1>;
31 #address-cells = <1>;
32 #size-cells = <0>;
37 d-cache-line-size = <32>;
38 i-cache-line-size = <32>;
39 d-cache-size = <32768>;
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H A Dacadia.dts11 /dts-v1/;
14 #address-cells = <1>;
15 #size-cells = <1>;
18 dcr-parent = <&{/cpus/cpu@0}>;
27 #address-cells = <1>;
28 #size-cells = <0>;
34 clock-frequency = <0>; /* Filled in by wrapper */
35 timebase-frequency = <0>; /* Filled in by wrapper */
36 i-cache-line-size = <32>;
37 d-cache-line-size = <32>;
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H A Dmpc7448hpc2.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
9 /dts-v1/;
14 #address-cells = <1>;
15 #size-cells = <1>;
28 #address-cells = <1>;
29 #size-cells =<0>;
34 d-cache-line-size = <32>; // 32 bytes
35 i-cache-line-size = <32>; // 32 bytes
36 d-cache-size = <0x8000>; // L1, 32K bytes
37 i-cache-size = <0x8000>; // L1, 32K bytes
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H A Dbamboo.dts14 /dts-v1/;
17 #address-cells = <2>;
18 #size-cells = <1>;
21 dcr-parent = <&{/cpus/cpu@0}>;
33 #address-cells = <1>;
34 #size-cells = <0>;
40 clock-frequency = <0>; /* Filled in by zImage */
41 timebase-frequency = <0>; /* Filled in by zImage */
42 i-cache-line-size = <32>;
43 d-cache-line-size = <32>;
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H A Dsam440ep.dts16 /dts-v1/;
19 #address-cells = <2>;
20 #size-cells = <1>;
34 #address-cells = <1>;
35 #size-cells = <0>;
41 clock-frequency = <0>; /* Filled in by zImage */
42 timebase-frequency = <0>; /* Filled in by zImage */
43 i-cache-line-size = <32>;
44 d-cache-line-size = <32>;
45 i-cache-size = <32768>;
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H A Dtqm8xx.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
9 /dts-v1/;
14 #address-cells = <1>;
15 #size-cells = <1>;
25 #address-cells = <1>;
26 #size-cells = <0>;
31 d-cache-line-size = <16>; // 16 bytes
32 i-cache-line-size = <16>; // 16 bytes
33 d-cache-size = <0x1000>; // L1, 4K
34 i-cache-size = <0x1000>; // L1, 4K
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/freebsd/sys/contrib/device-tree/Bindings/devfreq/
H A Dexynos-bus.txt1 * Generic Exynos Bus frequency device
4 and sub-blocks in SoC. Most Exynos SoCs share the common architecture
5 for buses. Generally, each bus of Exynos SoC includes a source clock
6 and a power line, which are able to change the clock frequency
9 is able to measure the current load of sub-blocks.
11 The Exynos SoC includes the various sub-blocks which have the each AXI bus.
12 The each AXI bus has the owned source clock but, has not the only owned
13 power line. The power line might be shared among one more sub-blocks.
14 So, we can divide into two type of device as the role of each sub-block.
16 - parent bus device
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/freebsd/sys/contrib/device-tree/src/mips/brcm/
H A Dbcm7125.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <0>;
11 mips-hpt-frequency = <202500000>;
30 cpu_intc: interrupt-controller {
31 #address-cells = <0>;
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
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H A Dbcm7420.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <0>;
11 mips-hpt-frequency = <93750000>;
30 cpu_intc: interrupt-controller {
31 #address-cells = <0>;
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
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H A Dbcm7358.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <0>;
11 mips-hpt-frequency = <375000000>;
24 cpu_intc: interrupt-controller {
25 #address-cells = <0>;
26 compatible = "mti,cpu-interrupt-controller";
28 interrupt-controller;
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/freebsd/sys/dev/clk/
H A Dclk.c1 /*-
51 SYSCTL_NODE(_hw, OID_AUTO, clock, CTLFLAG_RD | CTLFLAG_MPSAFE, NULL,
54 MALLOC_DEFINE(M_CLOCK, "clocks", "Clock framework");
64 /* Default clock methods. */
73 * Clock controller methods.
87 * Clock node - basic element for modeling SOC clock graph. It holds the clock
88 * provider's data about the clock, and the links for the clock's membership in
94 /* Clock nodes topology. */
95 struct clkdom *clkdom; /* Owning clock domain */
99 /* String based parent list. */
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/freebsd/sys/contrib/device-tree/src/arm64/zte/
H A Dzx296718.dtsi5 * This file is dual-licensed: you can use it either under the terms
44 #include <dt-bindings/input/input.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/gpio/gpio.h>
47 #include <dt-bindings/clock/zx296718-clock.h>
51 #address-cells = <1>;
52 #size-cells = <1>;
53 interrupt-parent = <&gic>;
67 #address-cells = <2>;
68 #size-cells = <0>;
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/freebsd/sys/contrib/device-tree/src/arm/hpe/
H A Dhpe-gxp.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
10 #address-cells = <1>;
11 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
18 compatible = "arm,cortex-a9";
21 next-level-cache = <&L2>;
26 pll: clock-0 {
27 compatible = "fixed-clock";
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/freebsd/sys/contrib/device-tree/Bindings/interconnect/
H A Dsamsung,exynos-bus.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interconnect/samsung,exynos-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
15 sub-blocks in SoC. Most Exynos SoCs share the common architecture for buses.
16 Generally, each bus of Exynos SoC includes a source clock and a power line,
17 which are able to change the clock frequency of the bus in runtime. To
20 sub-blocks.
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/freebsd/sys/powerpc/cpufreq/
H A Dpmufreq.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
51 static void pmufreq_identify(driver_t *driver, device_t parent);
82 pmufreq_identify(driver_t *driver, device_t parent) in pmufreq_identify() argument
87 node = ofw_bus_get_node(parent); in pmufreq_identify()
88 if (OF_getprop(node, "min-clock-frequency", &min_freq, sizeof(min_freq)) == -1) in pmufreq_identify()
92 if (device_find_child(parent, "pmufreq", -1) != NULL) in pmufreq_identify()
99 if (BUS_ADD_CHILD(parent, 10, "pmufreq", -1) == NULL) in pmufreq_identify()
100 device_printf(parent, "add pmufreq child failed\n"); in pmufreq_identify()
114 * A scalable MPC7455 has min-clock-frequency/max-clock-frequency as OFW in pmufreq_probe()
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/freebsd/sys/contrib/device-tree/src/mips/ingenic/
H A Djz4780.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/ingenic,jz4780-cgu.h>
3 #include <dt-bindings/clock/ingenic,tcu.h>
4 #include <dt-bindings/dma/jz4780-dma.h>
7 #address-cells = <1>;
8 #size-cells = <1>;
12 #address-cells = <1>;
13 #size-cells = <0>;
17 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
21 clock-names = "cpu";
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/freebsd/sys/dts/arm/
H A Dannapurna-alpine.dts1 /*-
28 /dts-v1/;
32 #address-cells = <1>;
33 #size-cells = <1>;
40 #address-cells = <1>;
41 #size-cells = <0>;
45 compatible = "arm,cortex-a15";
47 d-cache-line-size = <64>; // 64 bytes
48 i-cache-line-size = <64>; // 64 bytes
49 d-cache-size = <0x8000>; // L1, 32K
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