| /freebsd/sys/contrib/device-tree/Bindings/pinctrl/ |
| H A D | thead,th1520-pinctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/thead,th1520-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: T-Head TH1520 SoC pin controller
10 - Emil Renner Berthing <emil.renner.berthing@canonical.com>
13 Pinmux and pinconf controller in the T-Head TH1520 RISC-V SoC.
17 PADCTRL_AOSYS -> PAD Group 1
18 PADCTRL1_APSYS -> PAD Group 2
19 PADCTRL0_APSYS -> PAD Group 3
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| H A D | fsl,imx-pinctrl.txt | 4 to share one PAD to several functional blocks. The sharing is done by
5 multiplexing the PAD input/output signals. For each PAD there are up to
7 different PAD settings (like pull up, keeper, etc) the IOMUXC controls
8 also the PAD settings parameters.
10 Please refer to pinctrl-bindings.txt in this directory for details of the
14 Freescale IMX pin configuration node is a node of a group of pins which can be
16 of the pins in that group. The 'mux' selects the function mode(also named mux
17 mode) this pin can work on and the 'config' configures various pad settings
18 such as pull-up, open drain, drive strength, etc.
21 - compatible: "fsl,<soc>-iomuxc"
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| H A D | nvidia,tegra124-xusb-padctl.txt | 1 Device tree binding for NVIDIA Tegra XUSB pad controller
5 pad controller. While the description is good enough for the functional subset
7 needed for USB. For the new binding, see ../phy/nvidia,tegra-xusb-padctl.txt.
10 The Tegra XUSB pad controller manages a set of lanes, each of which can be
12 associated PHY that must be powered up before the pad can be used.
14 This document defines the device-specific binding for the XUSB pad controller.
16 Refer to pinctrl-bindings.txt in this directory for generic information about
17 pin controller device tree bindings and ../phy/phy-bindings.txt for details on
21 --------------------
22 - compatible: For Tegra124, must contain "nvidia,tegra124-xusb-padctl".
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| H A D | atmel,at91-pinctrl.txt | 4 to share one PAD to several functional blocks. The sharing is done by
5 multiplexing the PAD input/output signals. For each PAD there are up to
7 different PAD settings (like pull up, keeper, etc) the controller controls
8 also the PAD settings parameters.
10 Please refer to pinctrl-bindings.txt in this directory for details of the
14 Atmel AT91 pin configuration node is a node of a group of pins which can be
16 of the pins in that group. The 'pins' selects the function mode(also named pin
17 mode) this pin can work on and the 'config' configures various pad settings
18 such as pull-up, multi drive, etc.
21 - compatible: "atmel,at91rm9200-pinctrl" or "atmel,at91sam9x5-pinctrl"
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| H A D | rockchip,pinctrl.txt | 4 to share one PAD to several functional blocks. The sharing is done by
5 multiplexing the PAD input/output signals. For each PAD there are several
8 Please refer to pinctrl-bindings.txt in this directory for details of the
12 The Rockchip pin configuration node is a node of a group of pins which can be
14 config of the pins in that group. The 'pins' selects the function mode(also
15 named pin mode) this pin can work on and the 'config' configures various pad
16 settings such as pull-up, etc.
19 defined as gpio sub-nodes of the pinmux controller.
22 - compatible: should be
23 "rockchip,px30-pinctrl": for Rockchip PX30
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| H A D | fsl,mxs-pinctrl.txt | 6 voltage and pull-up.
9 - compatible: "fsl,imx23-pinctrl" or "fsl,imx28-pinctrl"
10 - reg: Should contain the register physical address and length for the
13 Please refer to pinctrl-bindings.txt in this directory for details of the
18 a group of pins, and only affects those parameters that are explicitly listed.
20 information about pull-up. For this reason, even seemingly boolean values are
26 One is to set up a group of pins for a function, both mux selection and pin
27 configurations, and it's called group node in the binding document. The other
29 different configuration than what is defined in group node. The binding
32 On mxs, there is no hardware pin group. The pin group in this binding only
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| H A D | nvidia,tegra210-pinmux.txt | 4 - compatible: "nvidia,tegra210-pinmux"
5 - reg: Should contain a list of base address and size pairs for:
6 - first entry: The APB_MISC_GP_*_PADCTRL registers (pad control)
7 - second entry: The PINMUX_AUX_* registers (pinmux)
9 Please refer to pinctrl-bindings.txt in this directory for details of the
15 pin, a group, or a list of pins or groups. This configuration can include the
16 mux function to select on those pin(s)/group(s), and various pin configuration
17 parameters, such as pull-up, tristate, drive strength, etc.
31 See the TRM to determine which properties and values apply to each pin/group.
33 include/dt-binding/pinctrl/pinctrl-tegra.h.
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| H A D | nvidia,tegra124-dpaux-padctl.txt | 1 Device tree binding for NVIDIA Tegra DPAUX pad controller
4 The Tegra Display Port Auxiliary (DPAUX) pad controller manages two pins
8 This document defines the device-specific binding for the DPAUX pad
9 controller. Refer to pinctrl-bindings.txt in this directory for generic
11 the binding document ../display/tegra/nvidia,tegra20-host1x.txt for more
15 -----------
18 from the pinctrl-bindings.txt document.
22 Furthermore, given that the pad functions are only applicable to a
23 single set of pads, the child nodes only need to describe the pad group
27 - groups: Must be "dpaux-io"
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| H A D | rockchip,pinctrl.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
13 The Rockchip Pinmux Controller enables the IC to share one PAD
15 the PAD input/output signals. For each PAD there are several muxing
18 Please refer to pinctrl-bindings.txt in this directory for details of the
22 The Rockchip pin configuration node is a node of a group of pins which can be
24 config of the pins in that group. The 'pins' selects the function mode
26 various pad settings such as pull-up, etc.
[all …]
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| H A D | nvidia,tegra20-pinmux.txt | 4 - compatible: "nvidia,tegra20-pinmux"
5 - reg: Should contain the register physical address and length for each of
6 the tri-state, mux, pull-up/down, and pad control register sets.
8 Please refer to pinctrl-bindings.txt in this directory for details of the
14 pin, a group, or a list of pins or groups. This configuration can include the
15 mux function to select on those pin(s)/group(s), and various pin configuration
16 parameters, such as pull-up, tristate, drive strength, etc.
30 Required subnode-properties:
31 - nvidia,pins : An array of strings. Each string contains the name of a pin or
32 group. Valid values for these names are listed below.
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| H A D | fsl,imx50-pinctrl.txt | 3 Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
7 - compatible: "fsl,imx50-iomuxc"
8 - fsl,pins: two integers array, represents a group of pins mux and config
10 pin working on a specific function, CONFIG is the pad setting value like
11 pull-up for this pin. Please refer to imx50 datasheet for the valid pad
31 Refer to imx50-pinfunc.h in device tree source folder for all available
|
| H A D | fsl,imx51-pinctrl.txt | 3 Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
7 - compatible: "fsl,imx51-iomuxc"
8 - fsl,pins: two integers array, represents a group of pins mux and config
10 pin working on a specific function, CONFIG is the pad setting value like
11 pull-up for this pin. Please refer to imx51 datasheet for the valid pad
31 Refer to imx51-pinfunc.h in device tree source folder for all available
|
| H A D | fsl,imx53-pinctrl.txt | 3 Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
7 - compatible: "fsl,imx53-iomuxc"
8 - fsl,pins: two integers array, represents a group of pins mux and config
10 pin working on a specific function, CONFIG is the pad setting value like
11 pull-up for this pin. Please refer to imx53 datasheet for the valid pad
31 Refer to imx53-pinfunc.h in device tree source folder for all available
|
| H A D | fsl,imx35-pinctrl.txt | 3 Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
7 - compatible: "fsl,imx35-iomuxc"
8 - fsl,pins: two integers array, represents a group of pins mux and config
10 pin working on a specific function, CONFIG is the pad setting value like
11 pull-up for this pin. Please refer to imx35 datasheet for the valid pad
32 Refer to imx35-pinfunc.h in device tree source folder for all available
|
| /freebsd/contrib/bsddialog/lib/ |
| H A D | menubox.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2021-2025 Alfonso Sabato Siciliano
50 int group; /* index menu in menugroup */ member
58 WINDOW *pad; /* pad for the private items */ member
59 int ypad; /* start pad line */
60 int ys, ye, xs, xe; /* pad pos */
69 int sel; /* current focus item, can be -1 */
74 getmode(enum menumode mode, struct bsddialog_menugroup group) in getmode() argument
77 if (group.type == BSDDIALOG_SEPARATOR) in getmode()
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| /freebsd/contrib/wpa/src/eap_common/ |
| H A D | eap_eke_common.c | 2 * EAP server/peer: EAP-EKE shared routines
3 * Copyright (c) 2011-2013, Jouni Malinen <j@w1.fi>
23 static int eap_eke_dh_len(u8 group) in eap_eke_dh_len() argument
25 switch (group) { in eap_eke_dh_len()
38 return -1; in eap_eke_dh_len()
48 return -1; in eap_eke_dhcomp_len()
53 static const struct dh_group * eap_eke_dh_group(u8 group) in eap_eke_dh_group() argument
55 switch (group) { in eap_eke_dh_group()
72 static int eap_eke_dh_generator(u8 group) in eap_eke_dh_generator() argument
74 switch (group) { in eap_eke_dh_generator()
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| /freebsd/crypto/openssl/include/openssl/ |
| H A D | core_names.h | 5 * Copyright 2019-2025 The OpenSSL Project Authors. All Rights Reserved.
28 # define OSSL_CIPHER_NAME_AES_128_GCM_SIV "AES-128-GCM-SIV"
29 # define OSSL_CIPHER_NAME_AES_192_GCM_SIV "AES-192-GCM-SIV"
30 # define OSSL_CIPHER_NAME_AES_256_GCM_SIV "AES-256-GCM-SIV"
34 # define OSSL_DIGEST_NAME_MD5_SHA1 "MD5-SHA1"
36 # define OSSL_DIGEST_NAME_SHA2_224 "SHA2-224"
37 # define OSSL_DIGEST_NAME_SHA2_256 "SHA2-256"
38 # define OSSL_DIGEST_NAME_SHA2_256_192 "SHA2-256/192"
39 # define OSSL_DIGEST_NAME_SHA2_384 "SHA2-384"
40 # define OSSL_DIGEST_NAME_SHA2_512 "SHA2-512"
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| /freebsd/contrib/libarchive/cpio/test/ |
| H A D | test_format_newc.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2003-2007 Tim Kientzle
9 /* Number of bytes needed to pad 'n' to multiple of 'block', assuming
11 * remembered as -n & (block - 1), but many compilers quite reasonably
12 * warn about "-n" when n is an unsigned value. (~(n) + 1) is the
14 #define PAD(n, block) ((~(n) + 1) & ((block) - 1)) macro
24 --l; in is_hex()
33 /* Convert up to 8 hex characters to unsigned 32-bit decimal integer */
42 r += *p + 10 - 'a'; in from_hex()
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| /freebsd/contrib/libpcap/pcap/ |
| H A D | nflog.h | 31 #include <pcap/pcap-inttypes.h>
37 * The NFLOG header is big-endian.
40 * big-endian or is an array of bytes in some externally-specified byte
41 * order (text string, link-layer address, link-layer header, packet
59 uint8_t pad; /* padding to 32 bits */ member
64 uint16_t pad; /* padding to 32-bit boundary */ member
79 #define NFULA_IFINDEX_INDEV 4 /* ifindex of device on which packet received (possibly bridge group…
80 …NFULA_IFINDEX_OUTDEV 5 /* ifindex of device on which packet transmitted (possibly bridge group) */
81 …A_IFINDEX_PHYSINDEV 6 /* ifindex of physical device on which packet received (not bridge group) */
82 …FINDEX_PHYSOUTDEV 7 /* ifindex of physical device on which packet transmitted (not bridge group) */
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| /freebsd/sys/contrib/device-tree/Bindings/arm/tegra/ |
| H A D | nvidia,tegra186-pmc.txt | 4 - compatible: Should contain one of the following:
5 - "nvidia,tegra186-pmc": for Tegra186
6 - "nvidia,tegra194-pmc": for Tegra194
7 - "nvidia,tegra234-pmc": for Tegra234
8 - reg: Must contain an (offset, length) pair of the register set for each
9 entry in reg-names.
10 - reg-names: Must include the following entries:
11 - "pmc"
12 - "wake"
13 - "aotag"
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| H A D | nvidia,tegra186-pmc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra186-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra186-pmc
17 - nvidia,tegra194-pmc
18 - nvidia,tegra234-pmc
19 - nvidia,tegra264-pmc
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/phy/ |
| H A D | nvidia,tegra20-usb-phy.txt | 6 - compatible : For Tegra20, must contain "nvidia,tegra20-usb-phy".
7 For Tegra30, must contain "nvidia,tegra30-usb-phy". Otherwise, must contain
8 "nvidia,<chip>-usb-phy" plus at least one of the above, where <chip> is
10 - reg : Defines the following set of registers, in the order listed:
11 - The PHY's own register set.
13 - The register set of the PHY containing the UTMI pad control registers.
14 Present if-and-only-if phy_type == utmi.
15 - phy_type : Should be one of "utmi", "ulpi" or "hsic".
16 - clocks : Defines the clocks listed in the clock-names property.
17 - clock-names : The following clock names must be present:
[all …]
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| /freebsd/sys/contrib/dev/mediatek/mt76/mt7615/ |
| H A D | usb_sdio.c | 1 // SPDX-License-Identifier: ISC
49 __le32 *txwi = (__le32 *)(skb->data - MT_USB_TXD_SIZE); in mt7663_usb_sdio_write_txwi()
59 struct mt7615_rate_desc *rate = &wrd->rate; in mt7663_usb_sdio_set_rates()
60 struct mt7615_sta *sta = wrd->sta; in mt7663_usb_sdio_set_rates()
64 lockdep_assert_held(&dev->mt76.mutex); in mt7663_usb_sdio_set_rates()
67 return -EINVAL; in mt7663_usb_sdio_set_rates()
70 return -ETIMEDOUT; in mt7663_usb_sdio_set_rates()
72 addr = mt7615_mac_wtbl_addr(dev, sta->wcid.idx); in mt7663_usb_sdio_set_rates()
76 w27 |= FIELD_PREP(MT_WTBL_W27_CC_BW_SEL, rate->bw); in mt7663_usb_sdio_set_rates()
83 w5 |= FIELD_PREP(MT_WTBL_W5_BW_CAP, rate->bw) | in mt7663_usb_sdio_set_rates()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/DebugInfo/PDB/Native/ |
| H A D | RawTypes.h | 1 //===- RawTypes.h -----------------------------------------------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
27 /// https://github.com/Microsoft/microsoft-pdb/blob/master/PDB/dbi/gsi.h
77 support::ulittle16_t Group; // Group index into descriptor array. member
79 support::ulittle16_t SecName; // Byte index of the segment or group name
85 // If group is set in flags, offset is the
86 // offset of the group.
87 support::ulittle32_t SecByteLength; // Byte count of the segment or group.
174 /// Pad to 64 bytes
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| /freebsd/crypto/openssl/util/perl/OpenSSL/ |
| H A D | paramnames.pm | 2 # Copyright 2023-2025 The OpenSSL Project Authors. All Rights Reserved.
24 'PROV_PARAM_CORE_VERSION' => "openssl-version",# utf8_ptr
25 'PROV_PARAM_CORE_PROV_NAME' => "provider-name", # utf8_ptr
26 'PROV_PARAM_CORE_MODULE_FILENAME' => "module-filename",# utf8_ptr
33 'PROV_PARAM_SECURITY_CHECKS' => "security-checks", # uint
34 'PROV_PARAM_HMAC_KEY_CHECK' => "hmac-key-check", # uint
35 'PROV_PARAM_KMAC_KEY_CHECK' => "kmac-key-check", # uint
36 'PROV_PARAM_TLS1_PRF_EMS_CHECK' => "tls1-prf-ems-check", # uint
37 'PROV_PARAM_NO_SHORT_MAC' => "no-short-mac", # uint
38 'PROV_PARAM_DRBG_TRUNC_DIGEST' => "drbg-no-trunc-md", # uint
[all …]
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