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/linux/Documentation/admin-guide/pm/
H A Dintel_pstate.rst1 .. SPDX-License-Identifier: GPL-2.0
22 Documentation/admin-guide/pm/cpufreq.rst if you have not done that yet.]
24 For the processors supported by ``intel_pstate``, the P-state concept is broader
27 information about that). For this reason, the representation of P-states used
32 ``intel_pstate`` maps its internal representation of P-states to frequencies too
38 Since the hardware P-state selection interface used by ``intel_pstate`` is
43 time the corresponding CPU is taken offline and need to be re-initialized when
47 only way to pass early-configuration-time parameters to it is via the kernel
66 -----------
69 hardware-managed P-states (HWP) support. If it works in this mode, the
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H A Dcpufreq.rst1 .. SPDX-License-Identifier: GPL-2.0
20 Operating Performance Points or P-states (in ACPI terminology). As a rule,
24 time (or the more power is drawn) by the CPU in the given P-state. Therefore
29 as possible and then there is no reason to use any P-states different from the
30 highest one (i.e. the highest-performance frequency/voltage configuration
38 put into different P-states.
41 capacity, so as to decide which P-states to put the CPUs into. Of course, since
64 information on the available P-states (or P-state ranges in some cases) and
65 access platform-specific hardware interfaces to change CPU P-states as requested
70 performance scaling algorithms for P-state selection can be represented in a
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H A Damd-pstate.rst1 .. SPDX-License-Identifier: GPL-2.0
5 ``amd-pstate`` CPU Performance Scaling Driver
16 ``amd-pstate`` is the AMD CPU performance scaling driver that introduces a
20 than legacy ACPI hardware P-States. Current AMD CPU/APU platforms are using
21 the ACPI P-states driver to manage CPU frequency and clocks with switching
22 only in 3 P-states. CPPC replaces the ACPI P-states controls and allows a
23 flexible, low-latency interface for the Linux kernel to directly
26 ``amd-pstate`` leverages the Linux kernel governors such as ``schedutil``,
30 Volume 2: System Programming [1]_). Currently, ``amd-pstate`` supports basic
40 continuous, abstract, and unit-less performance value in a scale that is
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/linux/drivers/gpu/drm/amd/display/dc/dml2/
H A Ddml2_wrapper.c1 /* SPDX-License-Identifier: MIT */
39 if (dml2->config.use_native_soc_bb_construction) in initialize_dml2_ip_params()
47 if (dml2->config.use_native_soc_bb_construction) in initialize_dml2_soc_bbox()
56 if (dml2->config.use_native_soc_bb_construction) in initialize_dml2_soc_states()
59 dml2_translate_soc_states(in_dc, out, in_dc->dml.soc.num_states); in initialize_dml2_soc_states()
69 in_out_display_cfg->hw.ODMMode[i] = mode_support_info->ODMMode[i]; in map_hw_resources()
70 in_out_display_cfg->hw.DPPPerSurface[i] = mode_support_info->DPPPerSurface[i]; in map_hw_resources()
71 in_out_display_cfg->hw.DSCEnabled[i] = mode_support_info->DSCEnabled[i]; in map_hw_resources()
72 in_out_display_cfg->hw.NumberOfDSCSlices[i] = mode_support_info->NumberOfDSCSlices[i]; in map_hw_resources()
73 in_out_display_cfg->hw.DLGRefClkFreqMHz = 24; in map_hw_resources()
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H A Ddml2_policy.c1 /* SPDX-License-Identifier: MIT */
33 if (entry->dcfclk_mhz > 0) { in get_optimal_ntuple()
34 …float bw_on_sdp = (float)(entry->dcfclk_mhz * socbb->return_bus_width_bytes * ((float)socbb->pct_i… in get_optimal_ntuple()
36 …entry->fabricclk_mhz = bw_on_sdp / (socbb->return_bus_width_bytes * ((float)socbb->pct_ideal_fabri… in get_optimal_ntuple()
37 entry->dram_speed_mts = bw_on_sdp / (socbb->num_chans * in get_optimal_ntuple()
38 …socbb->dram_channel_width_bytes * ((float)socbb->pct_ideal_dram_bw_after_urgent_pixel_only / 100)); in get_optimal_ntuple()
39 } else if (entry->fabricclk_mhz > 0) { in get_optimal_ntuple()
40 …float bw_on_fabric = (float)(entry->fabricclk_mhz * socbb->return_bus_width_bytes * ((float)socbb-… in get_optimal_ntuple()
42 …entry->dcfclk_mhz = bw_on_fabric / (socbb->return_bus_width_bytes * ((float)socbb->pct_ideal_sdp_b… in get_optimal_ntuple()
43 entry->dram_speed_mts = bw_on_fabric / (socbb->num_chans * in get_optimal_ntuple()
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/linux/tools/power/x86/x86_energy_perf_policy/
H A Dx86_energy_perf_policy.81 .\" This page Copyright (C) 2010 - 2015 Len Brown <len.brown@intel.com>
5 x86_energy_perf_policy \- Manage Energy vs. Performance Policy via x86 Model Specific Registers
10 .RB "scope: \-\-cpu\ cpu-list | \-\-pkg\ pkg-list"
12 .RB "cpu-list, pkg-list: # | #,# | #-# | all"
14 .RB "field: \-\-all | \-\-epb | \-\-hwp-epp | \-\-hwp-min | \-\-hwp-max | \-\-hwp-desired"
16 .RB "other: (\-\-force | \-\-hwp-enable | \-\-turbo-enable) value)"
18 .RB "value: # | default | performance | balance-performance | balance-power | power"
21 displays and updates energy-performance policy settings specific to
23 updates, no matter if the Linux cpufreq sub-system is enabled or not.
27 such as how aggressively the hardware enters and exits CPU idle states (C-states)
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/linux/drivers/firmware/arm_scmi/
H A Dpowercap.c1 // SPDX-License-Identifier: GPL-2.0
8 #define pr_fmt(fmt) "SCMI Notifications POWERCAP - " fmt
118 #define THRESH_LOW(p, id) \ argument
119 (lower_32_bits((p)->states[(id)].thresholds))
120 #define THRESH_HIGH(p, id) \ argument
121 (upper_32_bits((p)->states[(id)].thresholds))
129 struct scmi_powercap_state *states; member
148 ret = ph->xops->xfer_get_init(ph, PROTOCOL_ATTRIBUTES, 0, in scmi_powercap_attributes_get()
153 ret = ph->xops->do_xfer(ph, t); in scmi_powercap_attributes_get()
157 attributes = get_unaligned_le32(t->rx.buf); in scmi_powercap_attributes_get()
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/linux/tools/power/cpupower/utils/helpers/
H A Damd.c1 // SPDX-License-Identifier: GPL-2.0
14 /* ACPI P-States Helper Functions for AMD Processors ***************/
101 * cpu -> the cpu that gets evaluated in decode_pstates()
102 * boost_states -> how much boost states the machines support in decode_pstates()
105 * pstates -> in decode_pstates()
129 amd_pci_get_num_boost_states(int * active,int * states) amd_pci_get_num_boost_states() argument
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/linux/drivers/cpufreq/
H A Dacpi-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * acpi-cpufreq.c - ACPI Processor P-States Driver
7 * Copyright (C) 2002 - 2004 Dominik Brodowski <linux@brodo.de>
39 MODULE_DESCRIPTION("ACPI Processor P-States Driver");
67 return per_cpu_ptr(acpi_perf_data, data->acpi_perf_cpu); in to_perf_data()
110 return -EINVAL; in boost_set_msr()
133 on_each_cpu_mask(policy->cpus, boost_set_msr_each, in set_boost()
136 cpumask_pr_args(policy->cpus), str_enabled_disabled(val)); in set_boost()
143 struct acpi_cpufreq_data *data = policy->driver_data; in show_freqdomain_cpus()
146 return -ENODEV; in show_freqdomain_cpus()
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H A Dpowernow-k8.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * (c) 2003-2006 Advanced Micro Devices, Inc.
9 u32 numps; /* number of p-states */
10 u32 batps; /* number of p-states supported on battery */
13 * vid/fid pairings, but are modified during the ->target() call
32 * used to determine valid frequency/vid/fid states */
36 * handle hotplug events - so just point at cpufreq pol->cpus
53 /* Model Specific Registers for p-state transitions. MSRs are 64-bit. For */
54 /* writes (wrmsr - opcode 0f 30), the register number is placed in ecx, and */
55 /* the value to write is placed in edx:eax. For reads (rdmsr - opcode 0f 32), */
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/linux/tools/power/cpupower/bindings/python/
H A Dtest_raw_pylibcpupower.py2 # SPDX-License-Identifier: GPL-2.0-only
4 import raw_pylibcpupower as p namespace
11 cpu_cstates_count = p.cpuidle_state_count(0)
12 if cpu_cstates_count > -1:
13 print(f"CPU 0 has {cpu_cstates_count} c-states")
20 cstate_disabled = p.cpuidle_state_disable(0, 0, 1)
25 case -1:
27 case -2:
29 case -3:
30 print(f"No write access to disable/enable C-states: try using sudo")
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/linux/drivers/gpu/drm/omapdrm/
H A Domap_drv.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
7 #include <linux/dma-mapping.h>
57 if (!new_crtc_state->active) in omap_atomic_wait_for_completion()
63 dev_warn(dev->dev, in omap_atomic_wait_for_completion()
70 struct drm_device *dev = old_state->dev; in omap_atomic_commit_tail()
71 struct omap_drm_private *priv = dev->dev_private; in omap_atomic_commit_tail()
73 dispc_runtime_get(priv->dispc); in omap_atomic_commit_tail()
78 if (priv->omaprev != 0x3430) { in omap_atomic_commit_tail()
98 * OMAP3 DSS seems to have issues with the work-around above, in omap_atomic_commit_tail()
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/linux/drivers/xen/
H A Dxen-acpi-processor.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * https://lore.kernel.org/lkml/1322673664-14642-6-git-send-email-konrad.wilk@oracle.com
35 * - as those shrink to nr_cpu_bits (which is dependent on possible_cpu), which
40 /* Mutex to protect the acpi_ids_done - for CPU hotplug use. */
48 /* Which ACPI P-State dependencies for a enumerated processor */
56 .u.set_pminfo.id = _pr->acpi_id, in push_cxx_to_hypervisor()
64 dst_cx_states = kcalloc(_pr->power.count, in push_cxx_to_hypervisor()
67 return -ENOMEM; in push_cxx_to_hypervisor()
69 for (ok = 0, i = 1; i <= _pr->power.count; i++) { in push_cxx_to_hypervisor()
70 cx = &_pr->power.states[i]; in push_cxx_to_hypervisor()
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/linux/tools/tracing/rtla/src/
H A Dutils.c1 // SPDX-License-Identifier: GPL-2.0
27 * err_msg - print an error message to the stderr
42 * debug_msg - print a debug message to stderr if debug is set
60 * get_llong_from_str - get a long long int from a string
70 return -1; in get_llong_from_str()
76 * get_duration - fill output with a human readable duration since start_time
88 tm_info->tm_yday, in get_duration()
89 tm_info->tm_hour, in get_duration()
90 tm_info->tm_min, in get_duration()
91 tm_info->tm_sec); in get_duration()
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/linux/arch/powerpc/include/asm/
H A D8xx_immap.h10 * functional files.....but anyone else is welcome to try. -- Dan
95 /*-----------------------------------------------------------------------
96 * BR - Memory Controller: Base Register 16-9
107 #define BR_MS_GPCM 0x00000000 /* G.P.C.M. Machine Select */
108 #define BR_MS_UPMA 0x00000080 /* U.P.M.A Machine Select */
109 #define BR_MS_UPMB 0x000000c0 /* U.P.M.B Machine Select */
112 /*-----------------------------------------------------------------------
113 * OR - Memory Controller: Option Register 16-11
127 #define OR_SCY_0_CLK 0x00000000 /* 0 clock cycles wait states */
128 #define OR_SCY_1_CLK 0x00000010 /* 1 clock cycles wait states */
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/linux/Documentation/admin-guide/thermal/
H A Dintel_powerclamp.rst6 - Arjan van de Ven <arjan@linux.intel.com>
7 - Jacob Pan <jacob.jun.pan@linux.intel.com>
12 - Goals and Objectives
15 - Idle Injection
16 - Calibration
19 - Effectiveness and Limitations
20 - Power vs Performance
21 - Scalability
22 - Calibration
23 - Comparison with Alternative Techniques
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/linux/tools/power/cpupower/man/
H A Dcpupower-set.11 .TH CPUPOWER\-SET "1" "22/02/2011" "" "cpupower Manual"
3 cpupower\-set \- Set processor power related kernel or hardware configurations
6 .B cpupower set [ \-b VAL | \-e POLICY | \-m MODE | \-t BOOL ]
15 described in the cpupower(1) manpage in the \-\-cpu option section. Whether an
24 \-\
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/linux/kernel/sched/
H A Dmembarrier.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2010-2017 Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
22 * CPU1 after the IPI-induced memory barrier:
29 * b: send IPI IPI-induced mb
46 * before the IPI-induced memory barrier on CPU1.
68 * b: send IPI IPI-induced mb
80 * after the IPI-induced memory barrier on CPU1.
82 * C) Scheduling userspace thread -> kthread -> userspace thread vs membarrier
89 * b: read rq->curr->mm == NULL
110 * e: current->mm = NULL
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/linux/arch/mips/kernel/
H A Dpm-cps.c1 // SPDX-License-Identifier: GPL-2.0-or-later
13 #include <asm/asm-offsets.h>
17 #include <asm/mips-cps.h>
20 #include <asm/pm-cps.h>
22 #include <asm/smp-cps.h>
26 * cps_nc_entry_fn - type of a generated non-coherent state entry function
28 * @nc_ready_count: pointer to a non-coherent mapping of the core ready_count
30 * The code entering & exiting non-coherent states is generated at runtime
33 * core-specific code particularly for cache routines. If coupled_coherence
34 * is non-zero and this is the entry function for the CPS_PM_NC_WAIT state,
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/linux/net/sunrpc/auth_gss/
H A Dgss_krb5_seal.c4 * Adapted from MIT Kerberos 5-1.2.1 lib/gssapi/krb5/k5seal.c
6 * Copyright (c) 2000-2008 The Regents of the University of Michigan.
40 * Export of this software from the United States of America may require
41 * a specific license from the United States Government. It is the
79 u8 *p, flags = 0x00; in setup_token_v2() local
81 if ((ctx->flags & KRB5_CTX_FLAG_INITIATOR) == 0) in setup_token_v2()
83 if (ctx->flags & KRB5_CTX_FLAG_ACCEPTOR_SUBKEY) in setup_token_v2()
89 krb5_hdr = (u16 *)token->data; in setup_token_v2()
93 p = (u8 *)ptr; in setup_token_v2()
94 *p++ = flags; in setup_token_v2()
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/linux/drivers/pmdomain/
H A Dcore.c1 // SPDX-License-Identifier: GPL-2.0
3 * drivers/base/power/domain.c - Common code related to device power domains.
37 __routine = genpd->dev_ops.callback; \
56 mutex_lock(&genpd->mlock); in genpd_lock_mtx()
62 mutex_lock_nested(&genpd->mlock, depth); in genpd_lock_nested_mtx()
67 return mutex_lock_interruptible(&genpd->mlock); in genpd_lock_interruptible_mtx()
72 return mutex_unlock(&genpd->mlock); in genpd_unlock_mtx()
83 __acquires(&genpd->slock) in genpd_lock_spin()
87 spin_lock_irqsave(&genpd->slock, flags); in genpd_lock_spin()
88 genpd->lock_flags = flags; in genpd_lock_spin()
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/linux/Documentation/tools/rtla/
H A Dcommon_timerlat_options.rst1 **-a**, **--auto** *us*
4 while debugging the system. It is equivalent to use **-T** *us* **-s** *us*
5 **-t**. By default, *timerlat* tracer uses FIFO:95 for *timerlat* threads,
6 thus equilavent to **-P** *f:95*.
8 **-p**, **--period** *us*
12 **-i**, **--irq** *us*
16 **-T**, **--thread** *us*
20 **-s**, **--stack** *us*
25 **-t**, **--trace** \[*file*]
29 **--dma-latency** *us*
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/linux/Documentation/devicetree/bindings/cpufreq/
H A Dapple,cluster-cpufreq.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/cpufreq/apple,cluster-cpufreq.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hector Martin <marcan@marcan.st>
13 Apple SoCs (e.g. M1) have a per-cpu-cluster DVFS controller that is part of
15 operating-points-v2 table to define the CPU performance states, with the
16 opp-level property specifying the hardware p-state index for that level.
21 - items:
22 - enum:
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/linux/drivers/pinctrl/
H A Dcore.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2011 ST-Ericsson SA
6 * Written on behalf of Linaro for ST-Ericsson
14 #include <linux/radix-tree.h>
30 * struct pinctrl_dev - pin control class device
46 * @p: result of pinctrl_get() for this device
68 struct pinctrl *p; member
78 * struct pinctrl - per-device pin control state holder
81 * @states: a list of states for this device
90 struct list_head states; member
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/linux/arch/x86/kernel/
H A Dkvmclock.c1 // SPDX-License-Identifier: GPL-2.0-or-later
36 early_param("no-kvmclock", parse_no_kvmclock);
43 early_param("no-kvmclock-vsyscall", parse_no_kvmclock_vsyscall);
71 return -ENODEV; in kvm_set_wallclock()
91 return pvclock_clocksource_read_nowd(this_cpu_pvti()) - kvm_sched_clock_offset; in kvm_sched_clock_read()
101 pr_info("kvm-clock: using sched offset of %llu cycles", in kvm_sched_clock_init()
105 sizeof(((struct pvclock_vcpu_time_info *)NULL)->system_time)); in kvm_sched_clock_init()
110 * will calibrate under heavy load - thus, getting a lower lpj -
143 if ((src->pvti.flags & PVCLOCK_GUEST_STOPPED) != 0) { in kvm_check_and_clear_guest_paused()
144 src->pvti.flags &= ~PVCLOCK_GUEST_STOPPED; in kvm_check_and_clear_guest_paused()
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