Lines Matching +full:p +full:- +full:states
10 * functional files.....but anyone else is welcome to try. -- Dan
95 /*-----------------------------------------------------------------------
96 * BR - Memory Controller: Base Register 16-9
107 #define BR_MS_GPCM 0x00000000 /* G.P.C.M. Machine Select */
108 #define BR_MS_UPMA 0x00000080 /* U.P.M.A Machine Select */
109 #define BR_MS_UPMB 0x000000c0 /* U.P.M.B Machine Select */
112 /*-----------------------------------------------------------------------
113 * OR - Memory Controller: Option Register 16-11
127 #define OR_SCY_0_CLK 0x00000000 /* 0 clock cycles wait states */
128 #define OR_SCY_1_CLK 0x00000010 /* 1 clock cycles wait states */
129 #define OR_SCY_2_CLK 0x00000020 /* 2 clock cycles wait states */
130 #define OR_SCY_3_CLK 0x00000030 /* 3 clock cycles wait states */
131 #define OR_SCY_4_CLK 0x00000040 /* 4 clock cycles wait states */
132 #define OR_SCY_5_CLK 0x00000050 /* 5 clock cycles wait states */
133 #define OR_SCY_6_CLK 0x00000060 /* 6 clock cycles wait states */
134 #define OR_SCY_7_CLK 0x00000070 /* 7 clock cycles wait states */
135 #define OR_SCY_8_CLK 0x00000080 /* 8 clock cycles wait states */
136 #define OR_SCY_9_CLK 0x00000090 /* 9 clock cycles wait states */
137 #define OR_SCY_10_CLK 0x000000a0 /* 10 clock cycles wait states */
138 #define OR_SCY_11_CLK 0x000000b0 /* 11 clock cycles wait states */
139 #define OR_SCY_12_CLK 0x000000c0 /* 12 clock cycles wait states */
140 #define OR_SCY_13_CLK 0x000000d0 /* 13 clock cycles wait states */
141 #define OR_SCY_14_CLK 0x000000e0 /* 14 clock cycles wait states */
142 #define OR_SCY_15_CLK 0x000000f0 /* 15 clock cycles wait states */
227 /* The key to unlock registers maintained by keep-alive power.
396 uint fec_grp_hash_table_high; /* upper 32-bits of hash table */
397 uint fec_grp_hash_table_low; /* lower 32-bits of hash table */
412 uint fec_r_bound; /* end of RAM (read-only) */
427 * I guess we will never see an 823T :-).
491 /* Port E - MPC87x/88x only.
499 /* Communications Processor Timing Register -