/freebsd/sys/contrib/device-tree/Bindings/display/tegra/ |
H A D | nvidia,tegra20-host1x.txt | 4 - compatible: "nvidia,tegra<chip>-host1x" 5 - reg: Physical base address and length of the controller's registers. 6 For pre-Tegra186, one entry describing the whole register area. 7 For Tegra186, one entry for each entry in reg-names: 8 "vm" - VM region assigned to Linux 9 "hypervisor" - Hypervisor region (only if Linux acts as hypervisor) 10 - interrupts: The interrupt outputs from the controller. 11 - #address-cells: The number of cells used to represent physical base addresses 13 - #size-cells: The number of cells used to represent the size of an address 15 - ranges: The mapping of the host1x address space to the CPU address space. [all …]
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/freebsd/sys/contrib/device-tree/src/arm64/rockchip/ |
H A D | rk3399-t.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd 7 #include "rk3399-base.dtsi" 10 cluster0_opp: opp-table-0 { 11 compatible = "operating-points-v2"; 12 opp-shared; 15 opp-hz = /bits/ 64 <408000000>; 16 opp-microvolt = <875000 875000 1250000>; 17 clock-latency-ns = <40000>; 20 opp-hz = /bits/ 64 <600000000>; [all …]
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H A D | rk3399.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd 6 #include "rk3399-base.dtsi" 9 cluster0_opp: opp-table-0 { 10 compatible = "operating-points-v2"; 11 opp-shared; 14 opp-hz = /bits/ 64 <408000000>; 15 opp-microvolt = <825000 825000 1250000>; 16 clock-latency-ns = <40000>; 19 opp-hz = /bits/ 64 <600000000>; [all …]
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/freebsd/sys/contrib/device-tree/Bindings/opp/ |
H A D | opp-v2-qcom-level.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/opp/opp-v2-qcom-level.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Qualcomm OPP 10 - Niklas Cassel <nks@flawful.org> 13 - $ref: opp-v2-base.yaml# 17 const: operating-points-v2-qcom-level 20 '^opp-?[0-9]+$': 25 opp-level: true [all …]
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H A D | operating-points-v2-ti-cpu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/opp/operating-points-v2-ti-cpu.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: TI CPU OPP (Operating Performance Points) 12 OPP vary based on the silicon variant used. The data sheet sections 18 This document extends the operating-points-v2 binding by providing 22 - Dhruva Gole <d-gole@ti.com> 25 - $ref: opp-v2-base.yaml# 29 const: operating-points-v2-ti-cpu [all …]
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H A D | qcom-opp.txt | 1 Qualcomm OPP bindings to describe OPP nodes 3 The bindings are based on top of the operating-points-v2 bindings 4 described in Documentation/devicetree/bindings/opp/opp-v2-base.yaml 7 * OPP Table Node 10 - compatible: Allow OPPs to express their compatibility. It should be: 11 "operating-points-v2-qcom-level" 13 * OPP Node 16 - qcom,opp-fuse-level: A positive value representing the fuse corner/level 17 associated with this OPP node. Sometimes several corners/levels shares
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H A D | opp-v2-kryo-cpu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/opp/op [all...] |
H A D | opp-v2.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/opp/opp-v2.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Generic OPP (Operating Performance Points) 10 - Viresh Kumar <viresh.kumar@linaro.org> 13 - $ref: opp-v2-base.yaml# 17 const: operating-points-v2 22 - | 24 * Example 1: Single cluster Dual-core ARM cortex A9, switch DVFS states [all …]
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H A D | allwinner,sun50i-h6-operating-points.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/opp/allwinner,sun50i-h6-operating-points.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Allwinner H6 CPU OPP 10 - Chen-Yu Tsai <wens@csie.org> 11 - Maxime Ripard <mripard@kernel.org> 15 OPP varies based on the silicon variant in use. Allwinner Process 20 - $ref: opp-v2-base.yaml# 25 - allwinner,sun50i-h6-operating-points [all …]
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H A D | opp-v2-base.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/opp/opp-v2-base.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Generic OPP (Operating Performance Points) Common Properties 10 - Viresh Kumar <viresh.kumar@linaro.org> 13 Devices work at voltage-current-frequency combinations and some implementations 25 pattern: '^opp-table(-[a-z0-9]+)?$' 27 opp-shared: 29 Indicates that device nodes using this OPP Table Node's phandle switch [all …]
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/freebsd/sys/contrib/device-tree/Bindings/display/msm/ |
H A D | gpu.txt | 4 - compatible: "qcom,adreno-XYZ.W", "qcom,adreno" or 5 "amd,imageon-XYZ.W", "amd,imageon" 6 for example: "qcom,adreno-306.0", "qcom,adreno" 9 with the chip-id. 11 - reg: Physical base address and length of the controller's registers. 12 - interrupts: The interrupt signal from the gpu. 13 - clocks: device clocks (if applicable) 14 See ../clocks/clock-bindings.txt for details. 15 - clock-names: the following clocks are required by a3xx, a4xx and a5xx 22 - qcom,adreno-630.2 [all …]
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/freebsd/sys/contrib/device-tree/Bindings/power/avs/ |
H A D | qcom,cpr.txt | 4 or other device. Each OPP of a device corresponds to a "corner" that has 10 - compatible: 13 Definition: should be "qcom,qcs404-cpr", "qcom,cpr" for qcs404 15 - reg: 17 Value type: <prop-encoded-array> 18 Definition: base address and size of the rbcpr register region 20 - interrupts: 22 Value type: <prop-encoded-array> 25 - clocks: 27 Value type: <prop-encoded-array> [all …]
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H A D | qcom,cpr.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Niklas Cassel <nks@flawful.org> 14 or other device. Each OPP of a device corresponds to a "corner" that has 23 - enum: 24 - qcom,qcs404-cpr 25 - const: qcom,cpr 28 description: Base address and size of the RBCPR register region. 36 - description: Reference clock. [all …]
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/freebsd/sys/contrib/device-tree/Bindings/soc/qcom/ |
H A D | qcom,rpmh-rsc.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only 3 --- 4 $id: http://devicetree.org/schemas/soc/qcom/qcom,rpmh-rsc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Bjorn Andersson <bjorn.andersson@linaro.org> 27 ACTIVE - Triggered by Linux 28 SLEEP - Triggered by F/W 29 WAKE - Triggered by F/W 30 CONTROL - Triggered by F/W 31 See also:: <dt-bindings/soc/qcom,rpmh-rsc.h> [all …]
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/freebsd/sys/contrib/device-tree/src/arm/ti/omap/ |
H A D | omap36xx.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 5 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ 8 #include <dt-bindings/bus/ti-sysc.h> 9 #include <dt-bindings/media/omap3-isp.h> 21 operating-points-v2 = <&cpu0_opp_table>; 23 vbb-supply = <&abb_mpu_iva>; 24 clock-latency = <300000>; /* From omap-cpufreq driver */ 25 #cooling-cells = <2>; 29 cpu0_opp_table: opp-table { 30 compatible = "operating-points-v2-ti-cpu"; [all …]
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/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/fsl/ |
H A D | imx8m-ddrc.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/memory-controllers/fsl/imx8m-ddrc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Peng Fan <peng.fan@nxp.com> 18 switching is implemented by TF-A code which runs from a SRAM area. 22 capabilities through standard Linux mechanism like devfreq and OPP tables. 27 - enum: 28 - fsl,imx8mn-ddrc 29 - fsl,imx8mm-ddrc [all …]
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/freebsd/sys/contrib/device-tree/Bindings/power/ |
H A D | power-domain.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/power/power-domain.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Rafael J. Wysocki <rjw@rjwysocki.net> 11 - Kevi [all...] |
/freebsd/sys/contrib/device-tree/src/arm64/qcom/ |
H A D | msm8996.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. 6 #include <dt-bindings/interrupt-controller/arm-gic.h> 7 #include <dt-bindings/clock/qcom,gcc-msm8996.h> 8 #include <dt-bindings/clock/qcom,mmcc-msm8996.h> 9 #include <dt-bindings/clock/qcom,rpmcc.h> 10 #include <dt-bindings/interconnect/qcom,msm8996.h> 11 #include <dt-bindings/interconnect/qcom,msm8996-cbf.h> 12 #include <dt-bindings/firmware/qcom,scm.h> 13 #include <dt-bindings/gpio/gpio.h> [all …]
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H A D | sc7180.dtsi | 1 // SPDX-License-Identifier: BSD-3-Clause 5 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. 8 #include <dt-bindings/clock/qcom,dispcc-sc7180.h> 9 #include <dt-bindings/clock/qcom,gcc-sc7180.h> 10 #include <dt-bindings/clock/qcom,gpucc-sc7180.h> 11 #include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h> 12 #include <dt-bindings/clock/qcom,rpmh.h> 13 #include <dt-bindings/clock/qcom,videocc-sc7180.h> 14 #include <dt-bindings/firmware/qcom,scm.h> 15 #include <dt-bindings/interconnect/qcom,icc.h> [all …]
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H A D | msm8998.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 4 #include <dt-bindings/interrupt-controller/arm-gic.h> 5 #include <dt-bindings/clock/qcom,gcc-msm8998.h> 6 #include <dt-bindings/clock/qcom,gpucc-msm8998.h> 7 #include <dt-bindings/clock/qcom,mmcc-msm8998.h> 8 #include <dt-bindings/clock/qcom,rpmcc.h> 9 #include <dt-bindings/firmware/qcom,scm.h> 10 #include <dt-bindings/power/qcom-rpmpd.h> 11 #include <dt-bindings/gpio/gpio.h> 14 interrupt-parent = <&intc>; [all …]
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H A D | sdm845.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 8 #include <dt-bindings/clock/qcom,camcc-sdm845.h> 9 #include <dt-bindings/clock/qcom,dispcc-sdm845.h> 10 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 11 #include <dt-bindings/clock/qcom,gpucc-sdm845.h> 12 #include <dt-bindings/clock/qcom,lpass-sdm845.h> 13 #include <dt-bindings/clock/qcom,rpmh.h> 14 #include <dt-bindings/clock/qcom,videocc-sdm845.h> 15 #include <dt-bindings/dma/qcom-gpi.h> 16 #include <dt-bindings/firmware/qcom,scm.h> [all …]
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H A D | sm6115.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 6 #include <dt-bindings/clock/qcom,gcc-sm6115.h> 7 #include <dt-bindings/clock/qcom,sm6115-dispcc.h> 8 #include <dt-bindings/clock/qcom,sm6115-gpucc.h> 9 #include <dt-bindings/clock/qcom,rpmcc.h> 10 #include <dt-bindings/dma/qcom-gpi.h> 11 #include <dt-bindings/firmware/qcom,scm.h> 12 #include <dt-bindings/gpio/gpio.h> 13 #include <dt-bindings/interconnect/qcom,rpm-icc.h> 14 #include <dt-bindings/interconnect/qcom,sm6115.h> [all …]
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H A D | sc7280.dtsi | 1 // SPDX-License-Identifier: BSD-3-Clause 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 7 #include <dt-bindings/clock/qcom,camcc-sc7280.h> 8 #include <dt-bindings/clock/qcom,dispcc-sc7280.h> 9 #include <dt-bindings/clock/qcom,gcc-sc7280.h> 10 #include <dt-bindings/clock/qcom,gpucc-sc7280.h> 11 #include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h> 12 #include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h> 13 #include <dt-bindings/clock/qcom,rpmh.h> 14 #include <dt-bindings/clock/qcom,videocc-sc7280.h> [all …]
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H A D | sm8250.dtsi | 1 // SPDX-License-Identifier: BSD-3-Clause 6 #include <dt-bindings/interrupt-controller/arm-gic.h> 7 #include <dt-bindings/clock/qcom,dispcc-sm8250.h> 8 #include <dt-bindings/clock/qcom,gcc-sm8250.h> 9 #include <dt-bindings/clock/qcom,gpucc-sm8250.h> 10 #include <dt-bindings/clock/qcom,rpmh.h> 11 #include <dt-bindings/dma/qcom-gpi.h> 12 #include <dt-bindings/gpio/gpio.h> 13 #include <dt-bindings/interconnect/qcom,osm-l3.h> 14 #include <dt-bindings/interconnect/qcom,sm8250.h> [all …]
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/freebsd/sys/contrib/device-tree/src/riscv/starfive/ |
H A D | jh7110.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 OR MIT 7 /dts-v1/; 8 #include <dt-bindings/clock/starfive,jh7110-crg.h> 9 #include <dt-bindings/power/starfive,jh7110-pmu.h> 10 #include <dt-bindings/reset/starfive,jh7110-crg.h> 11 #include <dt-bindings/thermal/thermal.h> 15 #address-cells = <2>; 16 #size-cells = <2>; 19 #address-cells = <1>; 20 #size-cells = <0>; [all …]
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