/freebsd/sys/contrib/device-tree/src/arm64/exynos/ |
H A D | exynos5433-bus.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 11 compatible = "samsung,exynos-bus"; 13 clock-names = "bus"; 14 operating-points-v2 = <&bus_g2d_400_opp_table>; 19 compatible = "samsung,exynos-bus"; 21 clock-names = "bus"; 22 operating-points-v2 = <&bus_g2d_266_opp_table>; 27 compatible = "samsung,exynos-bus"; 29 clock-names = "bus"; 30 operating-points-v2 = <&bus_gscl_opp_table>; [all …]
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/freebsd/sys/contrib/device-tree/src/arm/samsung/ |
H A D | exynos5800.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 20 compatible = "samsung,exynos5800-clock", "syscon"; 24 opp-2000000000 { 25 opp-hz = /bits/ 64 <2000000000>; 26 opp-microvolt = <1312500 1312500 1500000>; 27 clock-latency-ns = <140000>; 29 opp-1900000000 { 30 opp-hz = /bits/ 64 <1900000000>; 31 opp-microvolt = <1262500 1262500 1500000>; 32 clock-latency-ns = <140000>; [all …]
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H A D | exynos3250.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 17 #include "exynos4-cpu-thermal.dtsi" 18 #include <dt-bindings/clock/exynos3250.h> 19 #include <dt-bindings/interrupt-controller/arm-gic.h> 20 #include <dt-bindings/interrupt-controller/irq.h> 24 interrupt-parent = <&gic>; 25 #address-cells = <1>; 26 #size-cells = <1>; 46 bus_dmc: bus-dmc { 47 compatible = "samsung,exynos-bus"; [all …]
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H A D | exynos4212.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 23 #address-cells = <1>; 24 #size-cells = <0>; 26 cpu-map { 39 compatible = "arm,cortex-a9"; 42 clock-names = "cpu"; 43 operating-points-v2 = <&cpu0_opp_table>; 44 #cooling-cells = <2>; /* min followed by max */ 49 compatible = "arm,cortex-a9"; 52 clock-names = "cpu"; [all …]
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H A D | exynos4210.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 5 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. 7 * Copyright (c) 2010-2011 Linaro Ltd. 20 #include "exynos4-cpu-thermal.dtsi" 31 bus_acp: bus-acp { 32 compatible = "samsung,exynos-bus"; 34 clock-name [all...] |
H A D | exynos5422-odroid-core.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 * Hardkernel Odroid XU3/XU3-Lite/XU4/HC1 boards core device tree source 6 * Copyright (c) 2013-2017 Samsung Electronics Co., Ltd. 10 #include <dt-bindings/clock/samsung,s2mps11.h> 11 #include <dt-bindings/interrupt-controller/irq.h> 12 #include <dt-bindings/gpio/gpio.h> 14 #include "exynos5422-cpus.dtsi" 27 stdout-path = "serial2:115200n8"; 31 compatible = "samsung,secure-firmware"; 35 fixed-rate-clocks { [all …]
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H A D | exynos4412.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 23 #address-cells = <1>; 24 #size-cells = <0>; 26 cpu-map { 45 compatible = "arm,cortex-a9"; 48 clock-names = "cpu"; 49 operating-points-v2 = <&cpu0_opp_table>; 50 #cooling-cells = <2>; /* min followed by max */ 55 compatible = "arm,cortex-a9"; 58 clock-names = "cpu"; [all …]
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H A D | exynos4x12.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 19 #include "exynos4-cpu-thermal.dtsi" 27 fimc-lite0 = &fimc_lite_0; 28 fimc-lite1 = &fimc_lite_1; 31 bus_acp: bus-acp { 32 compatible = "samsung,exynos-bus"; 34 clock-name [all...] |
/freebsd/sys/contrib/device-tree/Bindings/devfreq/ |
H A D | exynos-bus.txt | 4 and sub-blocks in SoC. Most Exynos SoCs share the common architecture 9 is able to measure the current load of sub-blocks. 11 The Exynos SoC includes the various sub-blocks which have the each AXI bus. 13 power line. The power line might be shared among one more sub-blocks. 14 So, we can divide into two type of device as the role of each sub-block. 16 - parent bus device 17 - passive bus device 26 VDD_xxx |--- A block (parent) 27 |--- B block (passive) 28 |--- C block (passive) [all …]
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/freebsd/sys/contrib/device-tree/Bindings/display/msm/ |
H A D | qcom,sm8450-dpu.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8450-dp [all...] |
H A D | qcom,sm7150-dpu.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/display/msm/qcom,sm7150-dpu.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Danila Tikhonov <danila@jiaxyga.com> 12 $ref: /schemas/display/msm/dpu-common.yaml# 16 const: qcom,sm7150-dpu 20 - description: Address offset and size for mdp register set 21 - description: Address offset and size for vbif register set 23 reg-names: [all …]
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H A D | qcom,sm8550-dpu.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8550-dp [all...] |
H A D | qcom,sm8650-dpu.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8650-dpu.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Neil Armstrong <neil.armstrong@linaro.org> 12 $ref: /schemas/display/msm/dpu-common.yaml# 17 - qcom,sm8650-dpu 18 - qcom,x1e80100-dpu 22 - description: Address offset and size for mdp register set 23 - description: Address offset and size for vbif register set [all …]
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H A D | qcom,sm8350-dpu.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8350-dp [all...] |
H A D | qcom,x1e80100-mdss.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/display/msm/qcom,x1e80100-mdss.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Abel Vesa <abel.vesa@linaro.org> 13 X1E80100 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like 16 $ref: /schemas/display/msm/mdss-common.yaml# 20 const: qcom,x1e80100-mdss 24 - description: Display AHB 25 - description: Display hf AXI [all …]
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H A D | qcom,sm8350-mdss.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8350-mds [all...] |
H A D | qcom,sm8650-mdss.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8650-mdss.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Neil Armstrong <neil.armstrong@linaro.org> 13 SM8650 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like 16 $ref: /schemas/display/msm/mdss-common.yaml# 20 const: qcom,sm8650-mdss 24 - description: Display AHB 25 - description: Display hf AXI [all …]
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H A D | qcom,sm8450-mdss.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8450-mds [all...] |
H A D | qcom,sm8250-mdss.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8250-mds [all...] |
H A D | qcom,sm8550-mdss.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8550-mds [all...] |
H A D | qcom,sm7150-mdss.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/display/msm/qcom,sm7150-mdss.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Danila Tikhonov <danila@jiaxyga.com> 13 SM7150 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like 16 $ref: /schemas/display/msm/mdss-common.yaml# 20 const: qcom,sm7150-mdss 24 - description: Display ahb clock from gcc 25 - description: Display hf axi clock [all …]
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/freebsd/sys/contrib/device-tree/src/arm64/ti/ |
H A D | k3-am625.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only OR MIT 7 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ 10 /dts-v1/; 12 #include "k3-am62.dtsi" 16 #address-cells = <1>; 17 #size-cells = <0>; 19 cpu-map { 40 compatible = "arm,cortex-a53"; 43 enable-method = "psci"; 44 i-cache-size = <0x8000>; [all …]
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/freebsd/sys/contrib/device-tree/src/arm64/rockchip/ |
H A D | rk3568-mecsbc.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 /dts-v1/; 4 #include <dt-bindings/gpio/gpio.h> 5 #include <dt-bindings/leds/common.h> 6 #include <dt-bindings/pinctrl/rockchip.h> 7 #include <dt-bindings/pwm/pwm.h> 20 stdout-path = "serial2:1500000n8"; 23 tas2562-sound { 24 compatible = "simple-audio-card"; 25 simple-audio-card,format = "i2s"; [all …]
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H A D | rk3399-t.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd 7 #include "rk3399-base.dtsi" 10 cluster0_opp: opp-table-0 { 11 compatible = "operating-points-v2"; 12 opp-shared; 15 opp-hz = /bits/ 64 <408000000>; 16 opp-microvolt = <875000 875000 1250000>; 17 clock-latency-ns = <40000>; 20 opp-hz = /bits/ 64 <600000000>; [all …]
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H A D | rk3399-t-opp.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd 8 cluster0_opp: opp-table-0 { 9 compatible = "operating-points-v2"; 10 opp-shared; 13 opp-hz = /bits/ 64 <408000000>; 14 opp-microvolt = <875000 875000 1250000>; 15 clock-latency-ns = <40000>; 18 opp-hz = /bits/ 64 <600000000>; 19 opp-microvolt = <875000 875000 1250000>; [all …]
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