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/freebsd/sys/contrib/device-tree/src/arm/nvidia/
H A Dtegra30-cpu-opp-microvolt.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 cpu0_opp_table: opp-table-cpu0 {
5 opp-51000000-800 {
6 opp-microvolt = <800000 800000 1250000>;
9 opp-51000000-850 {
10 opp-microvolt = <850000 850000 1250000>;
13 opp-51000000-912 {
14 opp-microvolt = <912000 912000 1250000>;
17 opp-102000000-800 {
18 opp-microvolt = <800000 800000 1250000>;
[all …]
H A Dtegra30-cpu-opp.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 cpu0_opp_table: opp-table-cpu0 {
5 compatible = "operating-points-v2";
6 opp-shared;
8 opp-51000000-800 {
9 clock-latency-ns = <100000>;
10 opp-supported-hw = <0x1F 0x31FE>;
11 opp-hz = /bits/ 64 <51000000>;
14 opp-51000000-850 {
15 clock-latency-ns = <100000>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/samsung/
H A Dexynos4212.dtsi1 // SPDX-License-Identifier: GPL-2.0
23 #address-cells = <1>;
24 #size-cells = <0>;
26 cpu-map {
39 compatible = "arm,cortex-a9";
42 clock-names = "cpu";
43 operating-points-v2 = <&cpu0_opp_table>;
44 #cooling-cells = <2>; /* min followed by max */
49 compatible = "arm,cortex-a9";
52 clock-names = "cpu";
[all …]
H A Dexynos4412.dtsi1 // SPDX-License-Identifier: GPL-2.0
23 #address-cells = <1>;
24 #size-cells = <0>;
26 cpu-map {
45 compatible = "arm,cortex-a9";
48 clock-names = "cpu";
49 operating-points-v2 = <&cpu0_opp_table>;
50 #cooling-cells = <2>; /* min followed by max */
55 compatible = "arm,cortex-a9";
58 clock-names = "cpu";
[all …]
H A Dexynos5800.dtsi1 // SPDX-License-Identifier: GPL-2.0
20 compatible = "samsung,exynos5800-clock", "syscon";
24 opp-2000000000 {
25 opp-hz = /bits/ 64 <2000000000>;
26 opp-microvolt = <1312500 1312500 1500000>;
27 clock-latency-ns = <140000>;
29 opp-1900000000 {
30 opp-hz = /bits/ 64 <1900000000>;
31 opp-microvolt = <1262500 1262500 1500000>;
32 clock-latency-ns = <140000>;
[all …]
H A Dexynos5250.dtsi1 // SPDX-License-Identifier: GPL-2.0
17 #include <dt-bindings/clock/exynos5250.h>
19 #include "exynos4-cpu-thermal.dtsi"
20 #include <dt-bindings/clock/exynos-audss-clk.h>
46 #address-cells = <1>;
47 #size-cells = <0>;
49 cpu-map {
62 compatible = "arm,cortex-a15";
65 clock-names = "cpu";
66 operating-points-v2 = <&cpu0_opp_table>;
[all …]
H A Dexynos5420.dtsi1 // SPDX-License-Identifier: GPL-2.0
14 #include <dt-bindings/clock/exynos5420.h>
15 #include <dt-bindings/clock/exynos-audss-clk.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
37 bus_disp1: bus-disp1 {
38 compatible = "samsung,exynos-bus";
40 clock-names = "bus";
44 bus_disp1_fimd: bus-disp1-fimd {
45 compatible = "samsung,exynos-bus";
47 clock-names = "bus";
[all …]
/freebsd/sys/contrib/device-tree/Bindings/cpufreq/
H A Dcpufreq-st.txt5 from the SoC, then supplies the OPP framework with 'prop' and 'supported
10 ----------------------
16 - operating-points : [See: ../power/opp-v1.yaml]
19 --------------
24 operating-points = <1500000 0
32 --------------------------------------------
38 - operating-points-v2 : [See ../power/opp-v2.yaml]
41 ----------------
45 operating-points-v2 = <&cpu0_opp_table>;
50 compatible = "operating-points-v2";
[all …]
/freebsd/sys/contrib/device-tree/src/arm/st/
H A Dstih418-b2264.dts1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
11 compatible = "st,stih418-b2264", "st,stih418";
14 stdout-path = &sbc_serial0;
24 operating-points-v
[all...]
/freebsd/sys/contrib/device-tree/Bindings/opp/
H A Dopp-v2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/opp-v2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic OPP (Operating Performance Points)
10 - Viresh Kumar <viresh.kumar@linaro.org>
13 - $ref: opp-v2-base.yaml#
17 const: operating-points-v2
22 - |
24 * Example 1: Single cluster Dual-core ARM cortex A9, switch DVFS states
[all …]
H A Dopp.txt1 Generic OPP (Operating Performance Points) Bindings
2 ----------------------------------------------------
4 Devices work at voltage-current-frequency combinations and some implementations
10 This document contain multiple versions of OPP binding and only one of them
13 Binding 1: operating-points
16 This binding only supports voltage-frequency pairs.
19 - operating-points: An array of 2-tuples items, and each item consists
20 of frequency and voltage like <freq-kHz vol-uV>.
27 compatible = "arm,cortex-a9";
29 next-level-cache = <&L2>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/amlogic/
H A Dmeson-sm1.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "meson-g12-common.dtsi"
8 #include <dt-bindings/clock/axg-audio-clkc.h>
9 #include <dt-bindings/power/meson-sm1-power.h>
10 #include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
11 #include <dt-bindings/reset/amlogic,meson-g12a-audio-reset.h>
16 tdmif_a: audio-controller-0 {
17 compatible = "amlogic,axg-tdm-iface";
18 #sound-dai-cells = <0>;
19 sound-name-prefix = "TDM_A";
[all …]
/freebsd/sys/contrib/device-tree/src/riscv/starfive/
H A Djh7110.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive,jh7110-crg.h>
9 #include <dt-bindings/power/starfive,jh7110-pmu.h>
10 #include <dt-bindings/reset/starfive,jh7110-cr
[all...]
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8mn.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8mn-clock.h>
7 #include <dt-bindings/power/imx8mn-power.h>
8 #include <dt-bindings/reset/imx8mq-reset.h>
9 #include <dt-binding
[all...]
H A Dimx8mq.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
7 #include <dt-bindings/clock/imx8mq-clock.h>
8 #include <dt-bindings/power/imx8mq-power.h>
9 #include <dt-bindings/reset/imx8mq-rese
[all...]
H A Dimx8mq-librem5.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2020 Purism SPC
6 /dts-v1/;
8 #include "dt-bindings/input/input.h"
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/leds/common.h>
11 #include "dt-binding
[all...]
/freebsd/sys/contrib/device-tree/src/arm64/exynos/
H A Dexynos5433.dtsi1 // SPDX-License-Identifier: GPL-2.0
16 #include <dt-bindings/clock/exynos5433.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
21 #address-cells = <2>;
22 #size-cells = <2>;
24 interrupt-paren
[all...]
/freebsd/sys/contrib/device-tree/src/arm64/mediatek/
H A Dmt8186.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
6 /dts-v1/;
7 #include <dt-binding
[all...]
/freebsd/sys/contrib/device-tree/src/arm64/apple/
H A Dt8103.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/apple-aic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/apple.h>
16 compatible = "apple,t8103", "apple,arm-platform";
18 #address-cells = <2>;
19 #size-cells = <2>;
22 #address-cells = <2>;
23 #size-cells = <0>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Ddra7.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/bus/ti-sysc.h>
9 #include <dt-bindings/clock/dra7.h>
10 #include <dt-bindings/interrupt-controlle
[all...]
/freebsd/sys/contrib/device-tree/src/arm64/rockchip/
H A Drk3399-pinephone-pro.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 * https://files.pine64.org/doc/PinePhonePro/PinephonePro-Schematic-V1.0-20211127.pdf
12 /dts-v1/;
13 #include <dt-bindings/input/gpio-keys.h>
14 #include <dt-bindings/input/linux-event-codes.h>
16 #include "rk3399-opp.dtsi"
20 compatible = "pine64,pinephone-pro", "rockchip,rk3399";
21 chassis-type = "handset";
30 stdout-path = "serial2:115200n8";
33 adc-keys {
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/renesas/
H A Dr8a779g0.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Device Tree Source for the R-Car V4H (R8A779G0) SoC
8 #include <dt-bindings/clock/r8a779g0-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a779g0-sysc.h>
14 #address-cells = <2>;
15 #size-cells = <2>;
17 /* External Audio clock - to be overridden by boards that provide it */
19 compatible = "fixed-clock";
20 #clock-cells = <0>;
[all …]
H A Dr8a77961.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car M3-W+ (R8A77961) SoC
5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
8 #include <dt-bindings/clock/r8a77961-cpg-mssr.h>
9 #include <dt-binding
[all...]
H A Dr8a77960.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car M3-W (R8A77960) SoC
5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
8 #include <dt-bindings/clock/r8a7796-cpg-mssr.h>
9 #include <dt-binding
[all...]
H A Dr8a774a1.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/r8a774a1-cp
[all...]

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