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/freebsd/contrib/processor-trace/libipt/internal/include/
H A Dpti-imm.h30 /*opcode 0x0*/ PTI_0_IMM_WIDTH_CONST_l2,
31 /*opcode 0x1*/ PTI_0_IMM_WIDTH_CONST_l2,
32 /*opcode 0x2*/ PTI_0_IMM_WIDTH_CONST_l2,
33 /*opcode 0x3*/ PTI_0_IMM_WIDTH_CONST_l2,
34 /*opcode 0x4*/ PTI_SIMM8_IMM_WIDTH_CONST_l2,
35 /*opcode 0x5*/ PTI_SIMMz_IMM_WIDTH_OSZ_NONTERM_EOSZ_l2,
36 /*opcode 0x6*/ PTI_0_IMM_WIDTH_CONST_l2,
37 /*opcode 0x7*/ PTI_0_IMM_WIDTH_CONST_l2,
38 /*opcode 0x8*/ PTI_0_IMM_WIDTH_CONST_l2,
39 /*opcode 0x9*/ PTI_0_IMM_WIDTH_CONST_l2,
[all …]
H A Dpti-disp.h30 /*opcode 0x0*/ PTI_PRESERVE_DEFAULT,
31 /*opcode 0x1*/ PTI_PRESERVE_DEFAULT,
32 /*opcode 0x2*/ PTI_PRESERVE_DEFAULT,
33 /*opcode 0x3*/ PTI_PRESERVE_DEFAULT,
34 /*opcode 0x4*/ PTI_PRESERVE_DEFAULT,
35 /*opcode 0x5*/ PTI_PRESERVE_DEFAULT,
36 /*opcode 0x6*/ PTI_PRESERVE_DEFAULT,
37 /*opcode 0x7*/ PTI_PRESERVE_DEFAULT,
38 /*opcode 0x8*/ PTI_PRESERVE_DEFAULT,
39 /*opcode 0x9*/ PTI_PRESERVE_DEFAULT,
[all …]
H A Dpti-modrm.h30 /*opcode 0x0*/ PTI_MODRM_TRUE,
31 /*opcode 0x1*/ PTI_MODRM_TRUE,
32 /*opcode 0x2*/ PTI_MODRM_TRUE,
33 /*opcode 0x3*/ PTI_MODRM_TRUE,
34 /*opcode 0x4*/ PTI_MODRM_FALSE,
35 /*opcode 0x5*/ PTI_MODRM_FALSE,
36 /*opcode 0x6*/ PTI_MODRM_FALSE,
37 /*opcode 0x7*/ PTI_MODRM_FALSE,
38 /*opcode 0x8*/ PTI_MODRM_TRUE,
39 /*opcode 0x9*/ PTI_MODRM_TRUE,
[all …]
/freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM/
H A DEmulateInstructionARM.h128 bool SetInstruction(const Opcode &insn_opcode, const Address &inst_addr,
145 bool ConditionPassed(const uint32_t opcode);
147 uint32_t CurrentCond(const uint32_t opcode);
301 const uint32_t opcode,
310 static ARMOpcode *GetARMOpcodeForInstruction(const uint32_t opcode,
313 static ARMOpcode *GetThumbOpcodeForInstruction(const uint32_t opcode,
317 bool EmulatePUSH(const uint32_t opcode, const ARMEncoding encoding);
320 bool EmulatePOP(const uint32_t opcode, const ARMEncoding encoding);
323 bool EmulateADDRdSPImm(const uint32_t opcode, const ARMEncoding encoding);
326 bool EmulateMOVRdSP(const uint32_t opcode, const ARMEncoding encoding);
[all …]
H A DEmulateInstructionARM.cpp891 bool EmulateInstructionARM::EmulatePUSH(const uint32_t opcode, in EmulatePUSH() argument
921 if (ConditionPassed(opcode)) { in EmulatePUSH()
930 registers = Bits32(opcode, 7, 0); in EmulatePUSH()
932 if (Bit32(opcode, 8)) in EmulatePUSH()
940 registers = Bits32(opcode, 15, 0) & ~0xa000; in EmulatePUSH()
946 Rt = Bits32(opcode, 15, 12); in EmulatePUSH()
953 registers = Bits32(opcode, 15, 0); in EmulatePUSH()
959 Rt = Bits32(opcode, 15, 12); in EmulatePUSH()
1014 bool EmulateInstructionARM::EmulatePOP(const uint32_t opcode, in EmulatePOP() argument
1037 if (ConditionPassed(opcode)) { in EmulatePOP()
[all …]
/freebsd/contrib/llvm-project/lldb/include/lldb/Core/
H A DOpcode.h1 //===-- Opcode.h ------------------------------------------------*- C++ -*-===//
29 class Opcode {
41 Opcode() = default;
43 Opcode(uint8_t inst, lldb::ByteOrder order) in Opcode() function
48 Opcode(uint16_t inst, lldb::ByteOrder order) in Opcode() function
53 Opcode(uint32_t inst, lldb::ByteOrder order) in Opcode() function
58 Opcode(uint64_t inst, lldb::ByteOrder order) in Opcode() function
63 Opcode(uint8_t *bytes, size_t length) in Opcode() function
70 m_type = Opcode::eTypeInvalid; in Clear()
73 Opcode::Type GetType() const { return m_type; } in GetType()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.h104 static BranchPredicate getBranchPredicate(unsigned Opcode);
133 unsigned Opcode) const;
136 unsigned Opcode) const;
139 unsigned Opcode, bool Swap = false) const;
142 unsigned Opcode,
158 unsigned Opcode,
295 // Splits a V_MOV_B64_DPP_PSEUDO opcode into a pair of v_mov_b32_dpp
303 // Returns an opcode that can be used to move a value to a \p DstRC
412 bool isSALU(uint16_t Opcode) const { in isSALU() argument
413 return get(Opcode).TSFlags & SIInstrFlags::SALU; in isSALU()
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/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430InstrFormats.td46 class IForm<bits<4> opcode, DestMode ad, bit bw, SourceMode as, int size,
54 let Inst{15-12} = opcode;
63 class IForm8<bits<4> opcode, DestMode dest, SourceMode src, int size,
65 : IForm<opcode, dest, 1, src, size, outs, ins, asmstr, pattern>;
67 class I8rr<bits<4> opcode,
69 : IForm8<opcode, DstReg, SrcReg, 2, outs, ins, asmstr, pattern> {
73 class I8ri<bits<4> opcode,
75 : IForm8<opcode, DstReg, SrcImm, 4, outs, ins, asmstr, pattern> {
82 class I8rc<bits<4> opcode,
91 let Inst{15-12} = opcode;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrFormats.td13 class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin>
22 let Inst{0-5} = opcode;
124 class IXFormMemOp<bits<6> opcode, dag OOL, dag IOL, string asmstr,
126 :I<opcode, OOL, IOL, asmstr, itin>, XFormMemOp;
129 class IForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr,
131 : I<opcode, OOL, IOL, asmstr, itin> {
141 class BForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr>
142 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
158 class BForm_1<bits<6> opcode, bits<5> bo, bit aa, bit lk, dag OOL, dag IOL,
160 : BForm<opcode, a
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/freebsd/contrib/llvm-project/lldb/source/Core/
H A DOpcode.cpp1 //===-- Opcode.cpp --------------------------------------------------------===//
9 #include "lldb/Core/Opcode.h"
24 int Opcode::Dump(Stream *s, uint32_t min_byte_width) { in Dump()
27 case Opcode::eTypeInvalid: in Dump()
30 case Opcode::eType8: in Dump()
33 case Opcode::eType16: in Dump()
36 case Opcode::eType16_2: in Dump()
37 case Opcode::eType32: in Dump()
41 case Opcode::eType64: in Dump()
45 case Opcode::eTypeBytes: in Dump()
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/freebsd/contrib/llvm-project/clang/lib/AST/Interp/
H A DOpcodes.td1 //===--- Opcodes.td - Opcode defitions for the constexpr VM -----*- C++ -*-===//
129 class Opcode {
140 class AluOpcode : Opcode {
145 class FloatOpcode : Opcode {
149 class IntegerOpcode : Opcode {
158 class JumpOpcode : Opcode {
176 def Ret : Opcode {
184 def RetVoid : Opcode {
190 def RetValue : Opcode {
196 def NoRet : Opcode {}
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/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZInstrFormats.td40 // MemKey identifies a targe reg-mem opcode, while MemType can be either
42 // its corresponding target opcode. See comment at MemFoldPseudo.
2258 class InherentRRE<string mnemonic, bits<16> opcode, RegisterOperand cls,
2260 : InstRRE<opcode, (outs cls:$R1), (ins),
2266 class InherentDualRRE<string mnemonic, bits<16> opcode, RegisterOperand cls>
2267 : InstRRE<opcode, (outs cls:$R1, cls:$R2), (ins),
2270 class InherentVRIa<string mnemonic, bits<16> opcode, bits<16> value>
2271 : InstVRIa<opcode, (outs VR128:$V1), (ins), mnemonic#"\t$V1", []> {
2276 class StoreInherentS<string mnemonic, bits<16> opcode,
2278 : InstS<opcode, (outs), (ins (bdaddr12only $B2, $D2):$BD2),
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFMISimplifyPatchable.cpp63 bool isLoadInst(unsigned Opcode);
77 unsigned Opcode);
97 static bool isST(unsigned Opcode) { in isST() argument
98 return Opcode == BPF::STB_imm || Opcode == BPF::STH_imm || in isST()
99 Opcode == BPF::STW_imm || Opcode == BPF::STD_imm; in isST()
102 static bool isSTX32(unsigned Opcode) { in isSTX32() argument
103 return Opcode == BPF::STB32 || Opcode == BPF::STH32 || Opcode == BPF::STW32; in isSTX32()
106 static bool isSTX64(unsigned Opcode) { in isSTX64() argument
107 return Opcode == BPF::STB || Opcode == BPF::STH || Opcode == BPF::STW || in isSTX64()
108 Opcode == BPF::STD; in isSTX64()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCA/
H A DRISCVCustomBehaviour.cpp169 getEEWAndEMUL(unsigned Opcode, RISCVII::VLMUL LMUL, uint8_t SEW) { in getEEWAndEMUL() argument
171 switch (Opcode) { in getEEWAndEMUL()
199 llvm_unreachable("Could not determine EEW from Opcode"); in getEEWAndEMUL()
208 bool opcodeHasEEWAndEMULInfo(unsigned short Opcode) { in opcodeHasEEWAndEMULInfo() argument
209 return Opcode == RISCV::VLM_V || Opcode == RISCV::VSM_V || in opcodeHasEEWAndEMULInfo()
210 Opcode == RISCV::VLE8_V || Opcode == RISCV::VSE8_V || in opcodeHasEEWAndEMULInfo()
211 Opcode == RISCV::VLE16_V || Opcode == RISCV::VSE16_V || in opcodeHasEEWAndEMULInfo()
212 Opcode == RISCV::VLE32_V || Opcode == RISCV::VSE32_V || in opcodeHasEEWAndEMULInfo()
213 Opcode == RISCV::VLE64_V || Opcode == RISCV::VSE64_V || in opcodeHasEEWAndEMULInfo()
214 Opcode == RISCV::VLSE8_V || Opcode == RISCV::VSSE8_V || in opcodeHasEEWAndEMULInfo()
[all …]
/freebsd/contrib/opencsd/decoder/source/i_dec/
H A Dtrc_i_decode.cpp82 if(inst_ARM_is_indirect_branch(instr_info->opcode, info)) in DecodeA32()
85 instr_info->is_link = inst_ARM_is_branch_and_link(instr_info->opcode, info); in DecodeA32()
87 else if(inst_ARM_is_direct_branch(instr_info->opcode)) in DecodeA32()
89 … inst_ARM_branch_destination((uint32_t)instr_info->instr_addr,instr_info->opcode,&branchAddr); in DecodeA32()
97 instr_info->is_link = inst_ARM_is_branch_and_link(instr_info->opcode, info); in DecodeA32()
99 else if((barrier = inst_ARM_barrier(instr_info->opcode)) != ARM_BARRIER_NONE) in DecodeA32()
116 if (inst_ARM_wfiwfe(instr_info->opcode)) in DecodeA32()
121 instr_info->is_conditional = inst_ARM_is_conditional(instr_info->opcode); in DecodeA32()
136 if(inst_A64_is_indirect_branch_link(instr_info->opcode, &instr_info->is_link, info)) in DecodeA64()
140 else if(inst_A64_is_direct_branch_link(instr_info->opcode, &instr_info->is_link, info)) in DecodeA64()
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/freebsd/contrib/tcpdump/
H A Dprint-zephyr.c49 const char *opcode; member
157 NULL, /* opcode */ in zephyr_print()
201 PARSE_FIELD_STR(z.opcode); in zephyr_print()
229 if (!strcmp(z.opcode, "USER_HIDE")) in zephyr_print()
231 else if (!strcmp(z.opcode, "USER_UNHIDE")) in zephyr_print()
239 ZEPHYR_PRINT(" zephyr-admin ", str_to_lower(z.opcode)); in zephyr_print()
245 if (!strcmp(z.opcode, "SUBSCRIBE") || in zephyr_print()
246 !strcmp(z.opcode, "SUBSCRIBE_NODEFS") || in zephyr_print()
247 !strcmp(z.opcode, "UNSUBSCRIBE")) { in zephyr_print()
249 ND_PRINT(" %ssub%s", strcmp(z.opcode, "SUBSCRIBE") ? "un" : "", in zephyr_print()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrFormatsC.td25 class RVInst16CR<bits<4> funct4, bits<2> opcode, dag outs, dag ins,
34 let Inst{1-0} = opcode;
40 class RVInst16CI<bits<3> funct3, bits<2> opcode, dag outs, dag ins,
49 let Inst{1-0} = opcode;
55 class RVInst16CSS<bits<3> funct3, bits<2> opcode, dag outs, dag ins,
64 let Inst{1-0} = opcode;
67 class RVInst16CIW<bits<3> funct3, bits<2> opcode, dag outs, dag ins,
75 let Inst{1-0} = opcode;
81 class RVInst16CL<bits<3> funct3, bits<2> opcode, dag outs, dag ins,
90 let Inst{1-0} = opcode;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/
H A DVPlanPatternMatch.h111 /// A helper to match an opcode against multiple recipe types.
112 template <unsigned Opcode, typename...> struct MatchRecipeAndOpcode {};
114 template <unsigned Opcode, typename RecipeTy>
115 struct MatchRecipeAndOpcode<Opcode, RecipeTy> {
118 return DefR && DefR->getOpcode() == Opcode;
122 template <unsigned Opcode, typename RecipeTy, typename... RecipeTys>
123 struct MatchRecipeAndOpcode<Opcode, RecipeTy, RecipeTys...> {
125 return MatchRecipeAndOpcode<Opcode, RecipeTy>::match(R) ||
126 MatchRecipeAndOpcode<Opcode, RecipeTys...>::match(R);
131 template <typename Op0_t, unsigned Opcode, typename... RecipeTys>
[all …]
/freebsd/sys/dev/bhnd/nvram/
H A Dbhnd_nvram_data_sprom_subr.c65 uint8_t *opcode);
72 * Initialize SPROM opcode evaluation state.
74 * @param state The opcode state to be initialized.
100 /* Allocate and populate our opcode index */ in bhnd_sprom_opcode_init()
139 /* Make index available to opcode state evaluation */ in bhnd_sprom_opcode_init()
149 * Reset SPROM opcode evaluation state; future evaluation will be performed
150 * starting at the first opcode.
152 * @param state The opcode state to be reset.
174 * @param state An opcode state previously successfully initialized with
226 * @param state The opcode state to be queried.
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetOpcodes.h28 /// Check whether the given Opcode is a generic opcode that is not supposed
30 inline bool isPreISelGenericOpcode(unsigned Opcode) { in isPreISelGenericOpcode() argument
31 return Opcode >= TargetOpcode::PRE_ISEL_GENERIC_OPCODE_START && in isPreISelGenericOpcode()
32 Opcode <= TargetOpcode::PRE_ISEL_GENERIC_OPCODE_END; in isPreISelGenericOpcode()
35 /// Check whether the given Opcode is a target-specific opcode.
36 inline bool isTargetSpecificOpcode(unsigned Opcode) { in isTargetSpecificOpcode() argument
37 return Opcode > TargetOpcode::PRE_ISEL_GENERIC_OPCODE_END; in isTargetSpecificOpcode()
40 /// \returns true if \p Opcode is an optimization hint opcode which is not
42 inline bool isPreISelGenericOptimizationHint(unsigned Opcode) { in isPreISelGenericOptimizationHint() argument
43 return Opcode >= TargetOpcode::PRE_ISEL_GENERIC_OPTIMIZATION_HINT_START && in isPreISelGenericOptimizationHint()
[all …]
/freebsd/crypto/heimdal/kcm/
H A Dprotocol.c56 kcm_operation opcode, in kcm_op_noop() argument
60 KCM_LOG_REQUEST(context, client, opcode); in kcm_op_noop()
75 kcm_operation opcode, in kcm_op_get_name() argument
88 KCM_LOG_REQUEST_NAME(context, client, opcode, name); in kcm_op_get_name()
90 ret = kcm_ccache_resolve_client(context, client, opcode, in kcm_op_get_name()
118 kcm_operation opcode, in kcm_op_gen_new() argument
125 KCM_LOG_REQUEST(context, client, opcode); in kcm_op_gen_new()
149 kcm_operation opcode, in kcm_op_initialize() argument
161 KCM_LOG_REQUEST(context, client, opcode); in kcm_op_initialize()
215 kcm_operation opcode, in kcm_op_destroy() argument
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86AvoidStoreForwardingBlocks.cpp133 static bool isXMMLoadOpcode(unsigned Opcode) { in isXMMLoadOpcode() argument
134 return Opcode == X86::MOVUPSrm || Opcode == X86::MOVAPSrm || in isXMMLoadOpcode()
135 Opcode == X86::VMOVUPSrm || Opcode == X86::VMOVAPSrm || in isXMMLoadOpcode()
136 Opcode == X86::VMOVUPDrm || Opcode == X86::VMOVAPDrm || in isXMMLoadOpcode()
137 Opcode == X86::VMOVDQUrm || Opcode == X86::VMOVDQArm || in isXMMLoadOpcode()
138 Opcode == X86::VMOVUPSZ128rm || Opcode == X86::VMOVAPSZ128rm || in isXMMLoadOpcode()
139 Opcode == X86::VMOVUPDZ128rm || Opcode == X86::VMOVAPDZ128rm || in isXMMLoadOpcode()
140 Opcode == X86::VMOVDQU64Z128rm || Opcode == X86::VMOVDQA64Z128rm || in isXMMLoadOpcode()
141 Opcode == X86::VMOVDQU32Z128rm || Opcode == X86::VMOVDQA32Z128rm; in isXMMLoadOpcode()
143 static bool isYMMLoadOpcode(unsigned Opcode) { in isYMMLoadOpcode() argument
[all …]
/freebsd/sys/dev/mfi/
H A Dmfi_debug.c123 const char *opcode; in mfi_print_dcmd() local
128 switch (dcmd->opcode) { in mfi_print_dcmd()
130 opcode = "CTRL_GETINFO"; in mfi_print_dcmd()
133 opcode = "CTRL_FLUSHCACHE"; in mfi_print_dcmd()
136 opcode = "CTRL_SHUTDOWN"; in mfi_print_dcmd()
139 opcode = "EVENT_GETINFO"; in mfi_print_dcmd()
142 opcode = "EVENT_GET"; in mfi_print_dcmd()
145 opcode = "EVENT_WAIT"; in mfi_print_dcmd()
148 opcode = "LD_GET_LIST"; in mfi_print_dcmd()
151 opcode = "LD_GET_INFO"; in mfi_print_dcmd()
[all …]
/freebsd/contrib/bearssl/T0/
H A DOpcode.cs28 abstract class Opcode { class
30 internal Opcode() in Opcode() method in Opcode
35 * Execute this opcode.
40 * Resolve the target (word reference) for this opcode.
44 throw new Exception("Not a call opcode"); in ResolveTarget()
48 * Resolve the jump offset for this opcode. Displacement is
49 * relative to the address of the opcode that immediately follows
54 throw new Exception("Not a jump opcode"); in ResolveJump()
58 * Get the Word that this opcode references; this can happen
68 * Get the data block that this opcode references; this can happen
[all …]
/freebsd/contrib/llvm-project/llvm/lib/DebugInfo/DWARF/
H A DDWARFExpression.cpp112 static Desc getDescImpl(ArrayRef<Desc> Descriptions, unsigned Opcode) { in getDescImpl() argument
114 if (Opcode >= Descriptions.size()) in getDescImpl()
116 return Descriptions[Opcode]; in getDescImpl()
119 static Desc getOpDesc(unsigned Opcode) { in getOpDesc() argument
121 return getDescImpl(Descriptions, Opcode); in getOpDesc()
135 static Desc getSubOpDesc(unsigned Opcode, unsigned SubOpcode) { in getSubOpDesc() argument
136 assert(Opcode == DW_OP_LLVM_user); in getSubOpDesc()
145 Opcode = Data.getU8(&Offset); in extract()
147 Desc = getOpDesc(Opcode); in extract()
161 Desc = getSubOpDesc(Opcode, Operands[Operand]); in extract()
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