| /freebsd/share/man/man4/ |
| H A D | attimer.4 | 30 .Nd i8254 Programmable Interval Timer (AT Timer) driver
36 .Bl -ohang
45 controls support for the time counter functionality.
53 The same value is also available at run-time via the
58 This driver uses i8254 Programmable Interval Timer (AT Timer) hardware
59 to supply the kernel with one timecounter and one event timer, and to generate
63 platform-dependent frequency.
65 one-shot.
66 The output of each channel has platform-defined wiring: one channel is wired
67 to the interrupt controller and may be used as event timer, one channel is
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| /freebsd/lib/libpmc/ |
| H A D | pmc.atomsilvermont.3 | 45 .Bl -tag -width "Li PMC_CLASS_IAP"
47 Fixed-function counters that count only one hardware event per counter.
49 Programmable counters that may be configured to count one of a defined
54 determined at run time by calling
59 .%B "Intel 64 and IA-32 Intel(R) Architecture Software Developer's Manual"
61 .%N "Order Number 325462-050US"
68 .Ss ATOM SILVERMONT PROGRAMMABLE PMCS
69 The programmable PMCs support the following capabilities:
70 .Bl -column "PMC_CAP_INTERRUPT" "Support"
87 .Bl -tag -width indent
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| H A D | pmc.sandybridgeuc.3 | 45 .Bl -tag -width "Li PMC_CLASS_UCP"
47 Fixed-function counters that count only one hardware event per counter.
49 Programmable counters that may be configured to count one of a defined
54 determined at run time by calling
59 .%B "Intel(R) 64 and IA-32 Architectures Software Developers Manual"
61 .%N "Order Number: 253669-039US"
68 Not all CPUs in this family implement fixed-function counters.
69 .Ss SANDYBRIDGE UNCORE PROGRAMMABLE PMCS
70 The programmable PMCs support the following capabilities:
71 .Bl -column "PMC_CAP_INTERRUPT" "Support"
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| H A D | pmc.haswelluc.3 | 45 .Bl -tag -width "Li PMC_CLASS_UCP"
47 Fixed-function counters that count only one hardware event per counter.
49 Programmable counters that may be configured to count one of a defined
54 determined at run time by calling
59 .%B "Intel(R) 64 and IA-32 Architectures Software Developers Manual"
61 .%N "Order Number: 325462-045US"
68 Not all CPUs in this family implement fixed-function counters.
69 .Ss HASWELL UNCORE PROGRAMMABLE PMCS
70 The programmable PMCs support the following capabilities:
71 .Bl -column "PMC_CAP_INTERRUPT" "Support"
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| H A D | pmc.3 | 1 .\" Copyright (c) 2003-2008 Joseph Koshy. All rights reserved.
40 The library is implemented using the lower-level facilities offered by
50 .Bl -bullet
53 These PMCs measure events in a whole-system manner, i.e., independent
57 Non-privileged process are allowed to allocate system scope PMCs if the
61 is non-zero.
70 Orthogonal to PMC scope, PMCs may be allocated in one of two
72 .Bl -bullet
86 PMC allocation time.
90 The library uses human-readable strings to name the event being
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| H A D | pmc.haswell.3 | 45 .Bl -tag -width "Li PMC_CLASS_IAP"
47 Fixed-function counters that count only one hardware event per counter.
49 Programmable counters that may be configured to count one of a defined
54 determined at run time by calling
59 .%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual"
61 .%N "Order Number: 325462-045US"
68 .Ss HASWELL PROGRAMMABLE PMCS
69 The programmable PMCs support the following capabilities:
70 .Bl -column "PMC_CAP_INTERRUPT" "Support"
87 .Bl -tag -width indent
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| H A D | pmc.haswellxeon.3 | 46 .Bl -tag -width "Li PMC_CLASS_IAP"
48 Fixed-function counters that count only one hardware event per counter.
50 Programmable counters that may be configured to count one of a defined
55 determined at run time by calling
60 .%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual"
62 .%N "Order Number: 325462-052US"
69 .Ss HASWELL PROGRAMMABLE PMCS
70 The programmable PMCs support the following capabilities:
71 .Bl -column "PMC_CAP_INTERRUPT" "Support"
88 .Bl -tag -width indent
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|
| H A D | pmc.sandybridge.3 | 45 .Bl -tag -width "Li PMC_CLASS_IAP"
47 Fixed-function counters that count only one hardware event per counter.
49 Programmable counters that may be configured to count one of a defined
57 determined at run time by calling
62 .%B "Intel(R) 64 and IA-32 Architectures Software Developers Manual"
64 .%N "Order Number: 253669-039US"
71 .Ss SANDY BRIDGE PROGRAMMABLE PMCS
72 The programmable PMCs support the following capabilities:
73 .Bl -column "PMC_CAP_INTERRUPT" "Support"
90 .Bl -tag -width indent
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|
| H A D | pmc.sandybridgexeon.3 | 45 .Bl -tag -width "Li PMC_CLASS_IAP"
47 Fixed-function counters that count only one hardware event per counter.
49 Programmable counters that may be configured to count one of a defined
54 determined at run time by calling
59 .%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual"
61 .%N "Order Number: 253669-043US"
68 .Ss SANDYBRIDGE XEON PROGRAMMABLE PMCS
69 The programmable PMCs support the following capabilities:
70 .Bl -column "PMC_CAP_INTERRUPT" "Support"
87 .Bl -tag -width indent
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|
| H A D | pmc.ivybridgexeon.3 | 45 .Bl -tag -width "Li PMC_CLASS_IAP"
47 Fixed-function counters that count only one hardware event per counter.
49 Programmable counters that may be configured to count one of a defined
54 determined at run time by calling
59 .%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual"
60 .%N "Order Number: 325462-045US"
67 .Ss IVYBRIDGE PROGRAMMABLE PMCS
68 The programmable PMCs support the following capabilities:
69 .Bl -column "PMC_CAP_INTERRUPT" "Support"
86 .Bl -tag -width indent
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| /freebsd/sys/contrib/device-tree/Bindings/iio/dac/ |
| H A D | ad5758.txt | 4 - compatible: Must be "adi,ad5758"
5 - reg: SPI chip select number for the device
6 - spi-max-frequency: Max SPI frequency to use (< 50000000)
7 - spi-cpha: is the only mode that is supported
11 - adi,dc-dc-mode: Mode of operation of the dc-to-dc converter
18 Programmable Power Control (PPC)
19 In this mode, the VDPC+ voltage is user-programmable to
24 current or voltage output at the VIOUT pin. Only one mode
25 can be enabled at any one time.
32 Depending on the selected output mode (voltage or current) one of the
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| H A D | adi,ad5758.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michae
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| /freebsd/sys/contrib/device-tree/Bindings/soc/ti/ |
| H A D | ti,pruss.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 TI Programmable Real-Time Unit and Industrial Communication Subsystem
11 - Suman Anna <s-anna@ti.com>
15 The Programmable Real-Time Unit and Industrial Communication Subsystem
16 (PRU-ICSS a.k.a. PRUSS) is present on various TI SoCs such as AM335x, AM437x,
17 Keystone 66AK2G, OMAP-L138/DA850 etc. A PRUSS consists of dual 32-bit RISC
18 cores (Programmable Real-Time Units, or PRUs), shared RAM, data and
22 The programmable nature of the PRUs provide flexibility to implement custom
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| /freebsd/sys/contrib/device-tree/Bindings/leds/ |
| H A D | leds-lm3532.txt | 1 * Texas Instruments - lm3532 White LED driver with ambient light sensing
4 The LM3532 provides the 3 high-voltage, low-side current sinks. The device is
5 programmable over an I2C-compatible interface and has independent
11 each with 32 internal voltage setting resistors, 8-bit logarithmic and linear
13 1000:1 dimming ratio with programmable fade in and fade out settings.
16 - compatible : "ti,lm3532"
17 - reg : I2C slave address
18 - #address-cells : 1
19 - #size-cells : 0
22 - enable-gpios : gpio pin to enable (active high)/disable the device.
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| /freebsd/sys/dev/isci/scil/ |
| H A D | scic_sgpio.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause OR GPL-2.0
9 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
22 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
28 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
70 //Programmable Blink Pattern Durations
113 * @param]in] vendor_specific_sequence - Vendor specific sequence set in the
123 * @brief Use this to set both programmable blink patterns A & B in the
124 * SGPBR(Programmable Blink Register). Will set identical patterns
128 * @param[in] pattern_a_high - High(LED on) duration time for pattern A
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| /freebsd/sys/arm/freescale/ |
| H A D | fsl_ocotp.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
31 * Access to the Freescale i.MX6 On-Chip One-Time-Programmable Memory
73 if ((root = OF_finddevice("/")) == -1) in fsl_ocotp_devmap()
75 if ((child = fdt_depth_search_compatible(root, "fsl,imx6q-ocotp", 0)) == 0) in fsl_ocotp_devmap()
102 return (bus_read_4(sc->mem_res, off)); in RD4()
120 sc->dev = dev; in ocotp_attach()
124 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, in ocotp_attach()
126 if (sc->mem_res == NULL) { in ocotp_attach()
154 if (ofw_bus_is_compatible(dev, "fsl,imx6q-ocotp") == 0) in ocotp_probe()
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| /freebsd/sys/contrib/device-tree/Bindings/mfd/ |
| H A D | max77620.txt | 4 -------------------
5 - compatible: Must be one of
9 - reg: I2C device address.
12 -------------------
13 - interrupts: The interrupt on the parent the controller is
15 - interrupt-controller: Marks the device node as an interrupt controller.
16 - #interrupt-cells: is <2> and their usage is compliant to the 2 cells
17 variant of <../interrupt-controller/interrupts.txt>
19 are defined at dt-bindings/mfd/max77620.h.
21 - system-power-controller: Indicates that this PMIC is controlling the
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| /freebsd/sys/contrib/device-tree/Bindings/nvmem/ |
| H A D | rockchip-otp.txt | 1 Rockchip internal OTP (One Time Programmable) memory device tree bindings
4 - compatible: Should be one of the following.
5 - "rockchip,px30-otp" - for PX30 SoCs.
6 - "rockchip,rk3308-otp" - for RK3308 SoCs.
7 - reg: Should contain the registers location and size
8 - clocks: Must contain an entry for each entry in clock-names.
9 - clock-names: Should be "otp", "apb_pclk" and "phy".
10 - resets: Must contain an entry for each entry in reset-names.
12 - reset-names: Should be "phy".
18 compatible = "rockchip,px30-otp";
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| H A D | lpc1850-otp.txt | 3 Internal OTP (One Time Programmable) memory for NXP LPC18xx/43xx devices.
6 - compatible: Should be "nxp,lpc1850-otp"
7 - reg: Must contain an entry with the physical base address and length
8 for each entry in reg-names.
9 - address-cells: must be set to 1.
10 - size-cells: must be set to 1.
16 compatible = "nxp,lpc1850-otp";
18 #address-cells = <1>;
19 #size-cells = <1>;
|
| /freebsd/sys/contrib/device-tree/Bindings/fuse/ |
| H A D | renesas,rcar-otp.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fuse/renesas,rcar-otp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: R-Car E-FUSE connected to OTP_MEM
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 The E-FUSE is a type of non-volatile memory, which is accessible through the
14 One-Time Programmable Memory (OTP_MEM) module on some R-Car Gen4 SoCs.
19 - renesas,r8a779g0-otp # R-CarV4H
20 - renesas,r8a779h0-otp # R-CarV4M
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| /freebsd/lib/libpmc/pmu-events/arch/x86/silvermont/ |
| H A D | pipeline.json | 108 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp…
117 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp…
127 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp…
137 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp…
147 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp…
157 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp…
165 …time to time. For this reason this event may have a changing ratio with regards to time. In system…
174 …e core frequency may change from time to time. For this reason this event may have a changing rati…
182 …ange from time. This event is not affected by core frequency changes but counts as if the core is …
190 …time. This event is not affected by core frequency changes but counts as if the core is running at…
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| /freebsd/sys/contrib/device-tree/Bindings/sound/ |
| H A D | renesas,idt821034.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Herve Codina <herve.codina@bootlin.com>
14 programmable gain setting.
16 The time-slots used by the codec must be set and so, the properties
17 'dai-tdm-slot-num', 'dai-tdm-slot-width', 'dai-tdm-slot-tx-mask' and
18 'dai-tdm-slot-rx-mask' must be present in the ALSA sound card node for
19 sub-nodes that involve the codec. The codec uses one 8bit time-slot per
21 'dai-tdm-tdm-slot-with' must be set to 8.
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| H A D | infineon,peb2466.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Herve Codina <herve.codina@bootlin.com>
13 The Infineon PEB2466 codec is a programmable DSP-based four channels codec
16 The time-slots used by the codec must be set and so, the properties
17 'dai-tdm-slot-num', 'dai-tdm-slot-width', 'dai-tdm-slot-tx-mask' and
18 'dai-tdm-slot-rx-mask' must be present in the sound card node for sub-nodes
19 that involve the codec. The codec uses one 8bit time-slot per channel.
20 'dai-tdm-tdm-slot-with' must be set to 8.
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| /freebsd/share/man/man9/ |
| H A D | eventtimers.9 | 2 .\" Copyright (c) 2011-2013 Alexander Motin <mav@FreeBSD.org>
33 .Bd -literal
86 Event timers are responsible for generating interrupts at specified time
87 or periodically, to run different time-based events.
89 .Bl -tag -width "Consumers"
91 Manage hardware to generate requested time events.
99 time events.
110 .Bl -tag -width Va
115 .Bl -tag -width "ET_FLAGS_PERIODIC" -compact
119 One-shot mode supported.
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| /freebsd/sys/contrib/device-tree/Bindings/display/ |
| H A D | atmel,lcdc-display.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/atmel,lcdc-display.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nicolas Ferre <nicolas.ferre@microchip.com>
11 - Dharma Balasubiramani <dharma.b@microchip.com>
15 from an external display buffer to a TFT LCD panel. The LCDC has one display
17 interface and a look-up table to allow palletized display configurations. The
18 LCDC is programmable on a per layer basis, and supports different LCD
26 - required: [ 'atmel,dmacon' ]
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|