| /freebsd/sys/contrib/device-tree/Bindings/mmc/ |
| H A D | renesas,sdhi.txt | 4 - compatible: should contain one or more of the following:
5 "renesas,sdhi-sh73a0" - SDHI IP on SH73A0 SoC
6 "renesas,sdhi-r7s72100" - SDHI IP on R7S72100 SoC
7 "renesas,sdhi-r7s9210" - SDHI IP on R7S9210 SoC
8 "renesas,sdhi-r8a73a4" - SDHI IP on R8A73A4 SoC
9 "renesas,sdhi-r8a7740" - SDHI IP on R8A7740 SoC
10 "renesas,sdhi-r8a7742" - SDHI IP on R8A7742 SoC
11 "renesas,sdhi-r8a7743" - SDHI IP on R8A7743 SoC
12 "renesas,sdhi-r8a7744" - SDHI IP on R8A7744 SoC
13 "renesas,sdhi-r8a7745" - SDHI IP on R8A7745 SoC
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/arm/ti/ |
| H A D | k3.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Texas Instruments K3 Multicore SoC architectur
[all...] |
| /freebsd/sys/contrib/device-tree/Bindings/clock/ |
| H A D | mvebu-core-clock.txt | 4 reading the Sample-At-Reset (SAR) register. The core clock consumer should
7 The following is a list of provided IDs and clock names on Armada 370/XP:
14 The following is a list of provided IDs and clock names on Armada 375:
20 The following is a list of provided IDs and clock names on Armada 380/385:
26 The following is a list of provided IDs and clock names on Armada 39x:
34 The following is a list of provided IDs and clock names on 98dx3236:
40 The following is a list of provided IDs and clock names on Kirkwood and Dove:
46 The following is a list of provided IDs and clock names on Orion5x:
52 - compatible : shall be one of the following:
53 "marvell,armada-370-core-clock" - For Armada 370 SoC core clocks
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/pwm/ |
| H A D | pwm-mediatek.txt | 4 - compatible: should be "mediatek,<name>-pwm":
5 - "mediatek,mt2712-pwm": found on mt2712 SoC.
6 - "mediatek,mt6795-pwm": found on mt6795 SoC.
7 - "mediatek,mt7622-pwm": found on mt7622 SoC.
8 - "mediatek,mt7623-pwm": found on mt7623 SoC.
9 - "mediatek,mt7628-pwm": found on mt7628 SoC.
10 - "mediatek,mt7629-pwm": found on mt7629 SoC.
11 - "mediatek,mt8183-pwm": found on mt8183 SoC.
12 - "mediatek,mt8195-pwm", "mediatek,mt8183-pwm": found on mt8195 SoC.
13 - "mediatek,mt8365-pwm": found on mt8365 SoC.
[all …]
|
| H A D | pwm-mtk-disp.txt | 4 - compatible: should be "mediatek,<name>-disp-pwm":
5 - "mediatek,mt2701-disp-pwm": found on mt2701 SoC.
6 - "mediatek,mt6595-disp-pwm": found on mt6595 SoC.
7 - "mediatek,mt8167-disp-pwm", "mediatek,mt8173-disp-pwm": found on mt8167 SoC.
8 - "mediatek,mt8173-disp-pwm": found on mt8173 SoC.
9 - "mediatek,mt8183-disp-pwm": found on mt8183 SoC.$
10 - reg: physical base address and length of the controller's registers.
11 - #pwm-cells: must be 2. See pwm.yaml in this directory for a description of
13 - clocks: phandle and clock specifier of the PWM reference clock.
14 - clock-names: must contain the following:
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/net/ |
| H A D | renesas,ravb.txt | 3 This file provides information on what the device node for the Ethernet AVB
7 - compatible: Must contain one or more of the following:
8 - "renesas,etheravb-r8a7742" for the R8A7742 SoC.
9 - "renesas,etheravb-r8a7743" for the R8A7743 SoC.
10 - "renesas,etheravb-r8a7744" for the R8A7744 SoC.
11 - "renesas,etheravb-r8a7745" for the R8A7745 SoC.
12 - "renesas,etheravb-r8a77470" for the R8A77470 SoC.
13 - "renesas,etheravb-r8a7790" for the R8A7790 SoC.
14 - "renesas,etheravb-r8a7791" for the R8A7791 SoC.
15 - "renesas,etheravb-r8a7792" for the R8A7792 SoC.
[all …]
|
| H A D | cdns,macb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nicolas Ferre <nicolas.ferre@microchip.com>
11 - Claudiu Beznea <claudiu.beznea@microchip.com>
16 - items:
17 - enum:
18 - cdns,at91rm9200-emac # Atmel at91rm9200 SoC
19 - const: cdns,emac # Generic
21 - items:
[all …]
|
| H A D | macb.txt | 4 - compatible: Should be "cdns,[<chip>-]{macb|gem}"
5 Use "cdns,at91rm9200-emac" Atmel at91rm9200 SoC.
6 Use "cdns,at91sam9260-macb" for Atmel at91sam9 SoCs.
7 Use "cdns,sam9x60-macb" for Microchip sam9x60 SoC.
8 Use "cdns,np4-macb" for NP4 SoC devices.
9 Use "cdns,at32ap7000-macb" for other 10/100 usage or use the generic form: "cdns,macb".
10 Use "atmel,sama5d2-gem" for the GEM IP (10/100) available on Atmel sama5d2 SoCs.
11 Use "atmel,sama5d29-gem" for GEM XL IP (10/100) available on Atmel sama5d29 SoCs.
12 Use "atmel,sama5d3-macb" for the 10/100Mbit IP available on Atmel sama5d3 SoCs.
13 Use "atmel,sama5d3-gem" for the Gigabit IP available on Atmel sama5d3 SoCs.
[all …]
|
| H A D | renesas,ether.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: ethernet-controller.yaml#
13 - Serge
[all...] |
| /freebsd/sys/contrib/device-tree/Bindings/arm/ |
| H A D | apple.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hector Martin <marcan@marcan.st>
15 This currently includes devices based on the "M1" SoC:
17 - Mac mini (M1, 2020)
18 - MacBook Pro (13-inch, M1, 2020)
19 - MacBook Air (M1, 2020)
20 - iMac (24-inch, M1, 2021)
22 Devices based on the "M2" SoC:
[all …]
|
| H A D | gemini.txt | 3 The Gemini SoC is the project name for an ARMv4 FA525-based SoC originally
9 Storm Semiconductor was acquired by Cortina Systems in 2008 and the SoC was
13 Many of the IP blocks used in the SoC comes from Faraday Technology.
20 - soc: the SoC should be represented by a simple bus encompassing all the
21 onchip devices, this is referred to as the soc bus node.
23 - syscon: the soc bus node must have a system controller node pointing to the
25 "cortina,gemini-syscon", "syscon";
27 Required properties on the syscon:
28 - reg: syscon register location and size.
29 - #clock-cells: should be set to <1> - the system controller is also a
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/mips/ |
| H A D | ralink.txt | 1 Ralink MIPS SoC device tree bindings
5 Each device tree must specify a compatible value for the Ralink SoC
9 ralink,rt2880-soc
10 ralink,rt3050-soc
11 ralink,rt3052-soc
12 ralink,rt3350-soc
13 ralink,rt3352-soc
14 ralink,rt3883-soc
15 ralink,rt5350-soc
16 ralink,mt7620a-soc
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/serial/ |
| H A D | fsl-lpuart.txt | 4 - compatible :
5 - "fsl,vf610-lpuart" for lpuart compatible with the one integrated
6 on Vybrid vf610 SoC with 8-bit register organization
7 - "fsl,ls1021a-lpuart" for lpuart compatible with the one integrated
8 on LS1021A SoC with 32-bit big-endian register organization
9 - "fsl,ls1028a-lpuart" for lpuart compatible with the one integrated
10 on LS1028A SoC with 32-bit little-endian register organization
11 - "fsl,imx7ulp-lpuart" for lpuart compatible with the one integrated
12 on i.MX7ULP SoC with 32-bit little-endian register organization
13 - "fsl,imx8qxp-lpuart" for lpuart compatible with the one integrated
[all …]
|
| /freebsd/sys/arm/freescale/imx/ |
| H A D | imx6_machdep.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
67 * interrupt controller, which is for use when the chip is in deep-sleep mode.
68 * We don't support deep sleep or have a GPC-PIC driver; we need all interrupts
72 * parent for the soc node and letting that get inherited by all other devices
74 * set the world right by just changing the interrupt-parent property of the soc
78 * 2020/11/25: The tempmon and pmu nodes are siblings (not children) of the soc
80 * for the soc node.
83 * - SOC node exists and has GPC as its interrupt parent.
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/mtd/ |
| H A D | gpmi-nand.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/gpmi-nand.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale General-Purpose Media Interface (GPMI)
10 - Han Xu <han.xu@nxp.com>
14 flash chips. The device tree may optionally contain sub-nodes
21 - enum:
22 - fsl,imx23-gpmi-nand
23 - fsl,imx28-gpmi-nand
[all …]
|
| H A D | brcm,brcmnand.txt | 3 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
4 flash chips. It has a memory-mapped register interface for both control
5 registers and for its data input/output buffer. On some SoCs, this controller is
10 available on a variety of Broadcom SoCs, including some BCM3xxx, BCM63xx, and
15 - compatible : May contain an SoC-specific compatibility string (see below)
16 to account for any SoC-specific hardware bits that may be
17 added on top of the base core controller.
21 string, like "brcm,brcmnand-v7.0"
23 brcm,brcmnand-v2.1
24 brcm,brcmnand-v2.2
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/rtc/ |
| H A D | isil,isl12057.txt | 8 ("wakeup-source") to handle the specific use-case found
9 on at least three in-tree users of the chip (NETGEAR ReadyNAS 102, 104
10 and 2120 ARM-based NAS); On those devices, the IRQ#2 pin of the chip
12 to the SoC but to a PMIC. It allows the device to be powered up when
15 be set when the IRQ#2 pin of the chip is not connected to the SoC but
20 - "compatible": must be "isil,isl12057"
21 - "reg": I2C bus address of the device
25 - "wakeup-source": mark the chip as a wakeup source, independently of
26 the availability of an IRQ line connected to the SoC.
37 Example isl12057 node with IRQ#2 pin connected to main SoC via MPP6 (note
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/soc/socionext/ |
| H A D | socionext,uniphier-soc-glue-debug.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-soc-glue-debug.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier SoC-glue logic debug part
10 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
13 SoC-glue logic debug part implemented on Socionext UniPhier SoCs is
20 - enum:
21 - socionext,uniphier-ld4-soc-glue-debug
22 - socionext,uniphier-pro4-soc-glue-debug
[all …]
|
| H A D | socionext,uniphier-soc-glue.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-soc-glue.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier SoC-glue logic
10 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
13 SoC-glue logic implemented on Socionext UniPhier SoCs is a collection of
19 - enum:
20 - socionext,uniphier-ld4-soc-glue
21 - socionext,uniphier-pro4-soc-glue
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/arm/keystone/ |
| H A D | ti,sci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
[all...] |
| /freebsd/sys/contrib/device-tree/Bindings/soc/ti/ |
| H A D | wkup-m3-ipc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/ti/wkup-m3-ipc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dave Gerlach <d-gerlach@ti.com>
11 - Drew Fustini <dfustini@baylibre.com>
14 The TI AM33xx and AM43xx family of devices use a small Cortex M3 co-processor
17 C-states for CPU Idle. Once the wkup_m3_ipc driver uses the wkup_m3_rproc driver
19 present in the SoC's control module and a mailbox. The wkup_m3_ipc exposes an
20 API to allow the SoC PM code to execute specific PM tasks.
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/dma/ |
| H A D | fsl-edma.txt | 3 The eDMA channels have multiplex capability by programmble memory-mapped
10 - compatible :
11 - "fsl,vf610-edma" for eDMA used similar to that on Vybrid vf610 SoC
12 - "fsl,imx7ulp-edma" for eDMA2 used similar to that on i.mx7ulp
13 - "fsl,ls1028a-edma" followed by "fsl,vf610-edma" for eDMA used on the
14 LS1028A SoC.
15 - reg : Specifies base physical address(s) and size of the eDMA registers.
19 - interrupts : A list of interrupt-specifiers, one for each entry in
20 interrupt-names on vf610 similar SoC. But for i.mx7ulp per channel
22 error interrupt(located in the last), no interrupt-names list on
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/pinctrl/ |
| H A D | fsl,imx-pinctrl.txt | 10 Please refer to pinctrl-bindings.txt in this directory for details of the
17 mode) this pin can work on and the 'config' configures various pad settings
18 such as pull-up, open drain, drive strength, etc.
21 - compatible: "fsl,<soc>-iomuxc"
22 Please refer to each fsl,<soc>-pinctrl.txt binding doc for supported SoCs.
25 - fsl,pins: each entry consists of 6 integers and represents the mux and config
28 imx*-pinfunc.h under device tree source folder. The last integer CONFIG is
29 the pad setting value like pull-up on this pin. And that's why fsl,pins entry
35 SION(1 << 30): Software Input On Field.
41 Please refer to each fsl,<soc>-pinctrl,txt binding doc for SoC specific part
[all …]
|
| H A D | sprd,pinctrl.txt | 8 pad driving level, system control select and so on ("domain pad
9 driving level": One pin can output 3.0v or 1.8v, depending on the
13 have several systems (AP/CP/CM4) on one SoC.).
16 of them, so we can not make every Spreadtrum-special configuration
32 Now we have 4 systems for sleep mode on SC9860 SoC: AP system,
35 - input-enable
36 - inpu
[all...] |
| /freebsd/sys/contrib/device-tree/Bindings/spi/ |
| H A D | spi-davinci.txt | 3 Links on DM:
4 Keystone 2 - https://www.ti.com/lit/ug/sprugp2a/sprugp2a.pdf
5 dm644x - https://www.ti.com/lit/ug/sprue32a/sprue32a.pdf
6 OMAP-L138/da830 - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
9 - #address-cells: number of cells required to define a chip select
10 address on the SPI bus. Should be set to 1.
11 - #size-cells: should be zero.
12 - compatible:
13 - "ti,dm6441-spi" for SPI used similar to that on DM644x SoC family
14 - "ti,da830-spi" for SPI used similar to that on DA8xx SoC family
[all …]
|