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/linux/drivers/net/ethernet/marvell/octeontx2/af/
H A Dmcs_reg.h15 u64 offset; \
17 offset = 0x408ull; \
19 offset = 0xa28ull; \
20 offset += (a) * 0x8ull; \
21 offset; })
25 u64 offset; \
27 offset = 0x808ull; \
29 offset = 0xa68ull; \
30 offset += (a) * 0x8ull; \
31 offset; })
[all …]
/linux/drivers/gpu/drm/amd/include/
H A Dv11_structs.h28 uint32_t shadow_base_lo; // offset: 0 (0x0)
29 uint32_t shadow_base_hi; // offset: 1 (0x1)
30 uint32_t gds_bkup_base_lo; // offset: 2 (0x2)
31 uint32_t gds_bkup_base_hi; // offset: 3 (0x3)
32 uint32_t fw_work_area_base_lo; // offset: 4 (0x4)
33 uint32_t fw_work_area_base_hi; // offset: 5 (0x5)
34 uint32_t shadow_initialized; // offset: 6 (0x6)
35 uint32_t ib_vmid; // offset: 7 (0x7)
36 uint32_t reserved_8; // offset: 8 (0x8)
37 uint32_t reserved_9; // offset: 9 (0x9)
[all …]
H A Dv12_structs.h28 uint32_t shadow_base_lo; // offset: 0 (0x0)
29 uint32_t shadow_base_hi; // offset: 1 (0x1)
30 uint32_t reserved_2; // offset: 2 (0x2)
31 uint32_t reserved_3; // offset: 3 (0x3)
32 uint32_t fw_work_area_base_lo; // offset: 4 (0x4)
33 uint32_t fw_work_area_base_hi; // offset: 5 (0x5)
34 uint32_t shadow_initialized; // offset: 6 (0x6)
35 uint32_t ib_vmid; // offset: 7 (0x7)
36 uint32_t reserved_8; // offset: 8 (0x8)
37 uint32_t reserved_9; // offset: 9 (0x9)
[all …]
H A Dv10_structs.h28 uint32_t reserved_0; // offset: 0 (0x0)
29 uint32_t reserved_1; // offset: 1 (0x1)
30 uint32_t reserved_2; // offset: 2 (0x2)
31 uint32_t reserved_3; // offset: 3 (0x3)
32 uint32_t reserved_4; // offset: 4 (0x4)
33 uint32_t reserved_5; // offset: 5 (0x5)
34 uint32_t reserved_6; // offset: 6 (0x6)
35 uint32_t reserved_7; // offset: 7 (0x7)
36 uint32_t reserved_8; // offset: 8 (0x8)
37 uint32_t reserved_9; // offset: 9 (0x9)
[all …]
/linux/drivers/gpu/drm/msm/registers/display/
H A Ddsi_phy_7nm.xml8 <reg32 offset="0x00000" name="REVISION_ID0"/>
9 <reg32 offset="0x00004" name="REVISION_ID1"/>
10 <reg32 offset="0x00008" name="REVISION_ID2"/>
11 <reg32 offset="0x0000c" name="REVISION_ID3"/>
12 <reg32 offset="0x00010" name="CLK_CFG0"/>
13 <reg32 offset="0x00014" name="CLK_CFG1"/>
14 <reg32 offset="0x00018" name="GLBL_CTRL"/>
15 <reg32 offset="0x0001c" name="RBUF_CTRL"/>
16 <reg32 offset="0x00020" name="VREG_CTRL_0"/>
17 <reg32 offset="0x00024" name="CTRL_0"/>
[all …]
H A Dhdmi.xml42 <reg32 offset="0x00000" name="CTRL">
47 <reg32 offset="0x00020" name="AUDIO_PKT_CTRL1">
50 <reg32 offset="0x00024" name="ACR_PKT_CTRL">
67 <reg32 offset="0x0028" name="VBI_PKT_CTRL">
87 <reg32 offset="0x0002c" name="INFOFRAME_CTRL0">
104 <reg32 offset="0x00030" name="INFOFRAME_CTRL1">
110 <reg32 offset="0x00034" name="GEN_PKT_CTRL">
140 <reg32 offset="0x00040" name="GC">
143 <reg32 offset="0x00044" name="AUDIO_PKT_CTRL2">
152 <reg32 offset="0x0006c" name="AVI_INFO" stride="4" length="4"/>
[all …]
H A Ddsi_phy_10nm.xml8 <reg32 offset="0x00000" name="REVISION_ID0"/>
9 <reg32 offset="0x00004" name="REVISION_ID1"/>
10 <reg32 offset="0x00008" name="REVISION_ID2"/>
11 <reg32 offset="0x0000c" name="REVISION_ID3"/>
12 <reg32 offset="0x00010" name="CLK_CFG0"/>
13 <reg32 offset="0x00014" name="CLK_CFG1"/>
14 <reg32 offset="0x00018" name="GLBL_CTRL"/>
15 <reg32 offset="0x0001c" name="RBUF_CTRL"/>
16 <reg32 offset="0x00020" name="VREG_CTRL"/>
17 <reg32 offset="0x00024" name="CTRL_0"/>
[all …]
H A Ddsi_phy_28nm.xml8 <array offset="0x00000" name="LN" length="4" stride="0x40">
9 <reg32 offset="0x00" name="CFG_0"/>
10 <reg32 offset="0x04" name="CFG_1"/>
11 <reg32 offset="0x08" name="CFG_2"/>
12 <reg32 offset="0x0c" name="CFG_3"/>
13 <reg32 offset="0x10" name="CFG_4"/>
14 <reg32 offset="0x14" name="TEST_DATAPATH"/>
15 <reg32 offset="0x18" name="DEBUG_SEL"/>
16 <reg32 offset="0x1c" name="TEST_STR_0"/>
17 <reg32 offset="0x20" name="TEST_STR_1"/>
[all …]
H A Ddsi_phy_14nm.xml8 <reg32 offset="0x00000" name="REVISION_ID0"/>
9 <reg32 offset="0x00004" name="REVISION_ID1"/>
10 <reg32 offset="0x00008" name="REVISION_ID2"/>
11 <reg32 offset="0x0000c" name="REVISION_ID3"/>
12 <reg32 offset="0x00010" name="CLK_CFG0">
16 <reg32 offset="0x00014" name="CLK_CFG1">
19 <reg32 offset="0x00018" name="GLBL_TEST_CTRL">
22 <reg32 offset="0x0001C" name="CTRL_0"/>
23 <reg32 offset="0x00020" name="CTRL_1">
25 <reg32 offset="0x00024" name="HW_TRIGGER"/>
[all …]
H A Ddsi_phy_28nm_8960.xml9 <array offset="0x00000" name="LN" length="4" stride="0x40">
10 <reg32 offset="0x00" name="CFG_0"/>
11 <reg32 offset="0x04" name="CFG_1"/>
12 <reg32 offset="0x08" name="CFG_2"/>
13 <reg32 offset="0x0c" name="TEST_DATAPATH"/>
14 <reg32 offset="0x14" name="TEST_STR_0"/>
15 <reg32 offset="0x18" name="TEST_STR_1"/>
18 <reg32 offset="0x00100" name="LNCK_CFG_0"/>
19 <reg32 offset="0x00104" name="LNCK_CFG_1"/>
20 <reg32 offset="0x00108" name="LNCK_CFG_2"/>
[all …]
H A Dmdp4.xml102 <reg32 offset="0x00000" name="VERSION">
111 <reg32 offset="0x00004" name="OVLP0_KICK"/>
112 <reg32 offset="0x00008" name="OVLP1_KICK"/>
113 <reg32 offset="0x000d0" name="OVLP2_KICK"/>
114 <reg32 offset="0x0000c" name="DMA_P_KICK"/>
115 <reg32 offset="0x00010" name="DMA_S_KICK"/>
116 <reg32 offset="0x00014" name="DMA_E_KICK"/>
117 <reg32 offset="0x00018" name="DISP_STATUS"/>
119 <reg32 offset="0x00038" name="DISP_INTF_SEL">
126 <reg32 offset="0x0003c" name="RESET_STATUS"/> <!-- only mdp4 >v2.1 -->
[all …]
H A Ddsi_phy_20nm.xml8 <array offset="0x00000" name="LN" length="4" stride="0x40">
9 <reg32 offset="0x00" name="CFG_0"/>
10 <reg32 offset="0x04" name="CFG_1"/>
11 <reg32 offset="0x08" name="CFG_2"/>
12 <reg32 offset="0x0c" name="CFG_3"/>
13 <reg32 offset="0x10" name="CFG_4"/>
14 <reg32 offset="0x14" name="TEST_DATAPATH"/>
15 <reg32 offset="0x18" name="DEBUG_SEL"/>
16 <reg32 offset="0x1c" name="TEST_STR_0"/>
17 <reg32 offset="0x20" name="TEST_STR_1"/>
[all …]
/linux/arch/s390/kernel/
H A Dasm-offsets.c21 OFFSET(__TASK_stack, task_struct, stack); in main()
22 OFFSET(__TASK_thread, task_struct, thread); in main()
23 OFFSET(__TASK_pid, task_struct, pid); in main()
26 OFFSET(__THREAD_ksp, thread_struct, ksp); in main()
29 OFFSET(__TI_flags, task_struct, thread_info.flags); in main()
30 OFFSET(__TI_sie, task_struct, thread_info.sie); in main()
33 OFFSET(__PT_PSW, pt_regs, psw); in main()
34 OFFSET(__PT_GPRS, pt_regs, gprs); in main()
35 OFFSET(__PT_R0, pt_regs, gprs[0]); in main()
36 OFFSET(__PT_R1, pt_regs, gprs[1]); in main()
[all …]
/linux/arch/mips/kernel/
H A Dasm-offsets.c30 OFFSET(PT_R0, pt_regs, regs[0]); in output_ptreg_defines()
31 OFFSET(PT_R1, pt_regs, regs[1]); in output_ptreg_defines()
32 OFFSET(PT_R2, pt_regs, regs[2]); in output_ptreg_defines()
33 OFFSET(PT_R3, pt_regs, regs[3]); in output_ptreg_defines()
34 OFFSET(PT_R4, pt_regs, regs[4]); in output_ptreg_defines()
35 OFFSET(PT_R5, pt_regs, regs[5]); in output_ptreg_defines()
36 OFFSET(PT_R6, pt_regs, regs[6]); in output_ptreg_defines()
37 OFFSET(PT_R7, pt_regs, regs[7]); in output_ptreg_defines()
38 OFFSET(PT_R8, pt_regs, regs[8]); in output_ptreg_defines()
39 OFFSET(PT_R9, pt_regs, regs[9]); in output_ptreg_defines()
[all …]
/linux/drivers/gpu/drm/msm/registers/adreno/
H A Da6xx_gmu.xml43 <reg32 offset="0x80" name="GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL"/>
44 <reg32 offset="0x81" name="GMU_GX_SPTPRAC_POWER_CONTROL"/>
45 <reg32 offset="0xc00" name="GMU_CM3_ITCM_START"/>
46 <reg32 offset="0x1c00" name="GMU_CM3_DTCM_START"/>
47 <reg32 offset="0x23f0" name="GMU_NMI_CONTROL_STATUS"/>
48 <reg32 offset="0x23f8" name="GMU_BOOT_SLUMBER_OPTION"/>
49 <reg32 offset="0x23f9" name="GMU_GX_VOTE_IDX"/>
50 <reg32 offset="0x23fa" name="GMU_MX_VOTE_IDX"/>
51 <reg32 offset="0x23fc" name="GMU_DCVS_ACK_OPTION"/>
52 <reg32 offset="0x23fd" name="GMU_DCVS_PERF_SETTING"/>
[all …]
H A Da5xx.xml862 <reg32 offset="0x0800" name="CP_RB_BASE"/>
863 <reg32 offset="0x0801" name="CP_RB_BASE_HI"/>
864 <reg32 offset="0x0802" name="CP_RB_CNTL"/>
865 <reg32 offset="0x0804" name="CP_RB_RPTR_ADDR"/>
866 <reg32 offset="0x0805" name="CP_RB_RPTR_ADDR_HI"/>
867 <reg32 offset="0x0806" name="CP_RB_RPTR"/>
868 <reg32 offset="0x0807" name="CP_RB_WPTR"/>
869 <reg32 offset="0x0808" name="CP_PFP_STAT_ADDR"/>
870 <reg32 offset="0x0809" name="CP_PFP_STAT_DATA"/>
871 <reg32 offset="0x080b" name="CP_DRAW_STATE_ADDR"/>
[all …]
H A Da4xx.xml865 <reg32 offset="0x0cc0" name="RB_GMEM_BASE_ADDR"/>
866 <reg32 offset="0x0cc7" name="RB_PERFCTR_RB_SEL_0" type="a4xx_rb_perfcounter_select"/>
867 <reg32 offset="0x0cc8" name="RB_PERFCTR_RB_SEL_1" type="a4xx_rb_perfcounter_select"/>
868 <reg32 offset="0x0cc9" name="RB_PERFCTR_RB_SEL_2" type="a4xx_rb_perfcounter_select"/>
869 <reg32 offset="0x0cca" name="RB_PERFCTR_RB_SEL_3" type="a4xx_rb_perfcounter_select"/>
870 <reg32 offset="0x0ccb" name="RB_PERFCTR_RB_SEL_4" type="a4xx_rb_perfcounter_select"/>
871 <reg32 offset="0x0ccc" name="RB_PERFCTR_RB_SEL_5" type="a4xx_rb_perfcounter_select"/>
872 <reg32 offset="0x0ccd" name="RB_PERFCTR_RB_SEL_6" type="a4xx_rb_perfcounter_select"/>
873 <reg32 offset="0x0cce" name="RB_PERFCTR_RB_SEL_7" type="a4xx_rb_perfcounter_select"/>
874 <reg32 offset="0x0ccf" name="RB_PERFCTR_CCU_SEL_0" type="a4xx_ccu_perfcounter_select"/>
[all …]
/linux/arch/riscv/kernel/
H A Dasm-offsets.c23 OFFSET(TASK_THREAD_RA, task_struct, thread.ra); in asm_offsets()
24 OFFSET(TASK_THREAD_SP, task_struct, thread.sp); in asm_offsets()
25 OFFSET(TASK_THREAD_S0, task_struct, thread.s[0]); in asm_offsets()
26 OFFSET(TASK_THREAD_S1, task_struct, thread.s[1]); in asm_offsets()
27 OFFSET(TASK_THREAD_S2, task_struct, thread.s[2]); in asm_offsets()
28 OFFSET(TASK_THREAD_S3, task_struct, thread.s[3]); in asm_offsets()
29 OFFSET(TASK_THREAD_S4, task_struct, thread.s[4]); in asm_offsets()
30 OFFSET(TASK_THREAD_S5, task_struct, thread.s[5]); in asm_offsets()
31 OFFSET(TASK_THREAD_S6, task_struct, thread.s[6]); in asm_offsets()
32 OFFSET(TASK_THREAD_S7, task_struct, thread.s[7]); in asm_offsets()
[all …]
/linux/drivers/net/ethernet/microchip/vcap/
H A Dvcap_model_kunit.c20 .offset = 0,
25 .offset = 2,
30 .offset = 3,
35 .offset = 10,
40 .offset = 13,
45 .offset = 16,
50 .offset = 19,
55 .offset = 20,
60 .offset = 32,
65 .offset = 35,
[all …]
/linux/include/video/
H A Dmach64.h20 #define CRTC_H_TOTAL_DISP 0x0000 /* Dword offset 0_00 */
21 #define CRTC2_H_TOTAL_DISP 0x0000 /* Dword offset 0_00 */
22 #define CRTC_H_SYNC_STRT_WID 0x0004 /* Dword offset 0_01 */
23 #define CRTC2_H_SYNC_STRT_WID 0x0004 /* Dword offset 0_01 */
30 #define CRTC_V_TOTAL_DISP 0x0008 /* Dword offset 0_02 */
31 #define CRTC2_V_TOTAL_DISP 0x0008 /* Dword offset 0_02 */
36 #define CRTC_V_SYNC_STRT_WID 0x000C /* Dword offset 0_03 */
37 #define CRTC2_V_SYNC_STRT_WID 0x000C /* Dword offset 0_03 */
42 #define CRTC_VLINE_CRNT_VLINE 0x0010 /* Dword offset 0_04 */
43 #define CRTC2_VLINE_CRNT_VLINE 0x0010 /* Dword offset 0_04 */
[all …]
/linux/drivers/clk/meson/
H A Dgxbb.h17 #define SCR 0x2C /* 0x0b offset in data sheet */
18 #define TIMEOUT_VALUE 0x3c /* 0x0f offset in data sheet */
20 #define HHI_GP0_PLL_CNTL 0x40 /* 0x10 offset in data sheet */
21 #define HHI_GP0_PLL_CNTL2 0x44 /* 0x11 offset in data sheet */
22 #define HHI_GP0_PLL_CNTL3 0x48 /* 0x12 offset in data sheet */
23 #define HHI_GP0_PLL_CNTL4 0x4c /* 0x13 offset in data sheet */
24 #define HHI_GP0_PLL_CNTL5 0x50 /* 0x14 offset in data sheet */
25 #define HHI_GP0_PLL_CNTL1 0x58 /* 0x16 offset in data sheet */
27 #define HHI_XTAL_DIVN_CNTL 0xbc /* 0x2f offset in data sheet */
28 #define HHI_TIMER90K 0xec /* 0x3b offset in data sheet */
[all …]
/linux/drivers/net/ethernet/microchip/sparx5/
H A Dsparx5_vcap_ag_api.c20 .offset = 0,
25 .offset = 1,
30 .offset = 2,
35 .offset = 4,
40 .offset = 16,
45 .offset = 18,
50 .offset = 83,
55 .offset = 84,
60 .offset = 85,
65 .offset = 88,
[all …]
/linux/drivers/net/ethernet/microchip/sparx5/lan969x/
H A Dlan969x_vcap_ag_api.c19 .offset = 0,
24 .offset = 1,
29 .offset = 2,
34 .offset = 4,
39 .offset = 14,
44 .offset = 16,
49 .offset = 81,
54 .offset = 82,
59 .offset = 83,
64 .offset = 86,
[all …]
/linux/drivers/net/ethernet/microchip/lan966x/
H A Dlan966x_vcap_ag_api.c12 .offset = 0,
17 .offset = 1,
22 .offset = 3,
27 .offset = 12,
32 .offset = 13,
37 .offset = 14,
42 .offset = 15,
47 .offset = 16,
52 .offset = 17,
57 .offset = 18,
[all …]
/linux/arch/x86/kernel/
H A Dasm-offsets.c37 OFFSET(TASK_threadsp, task_struct, thread.sp); in common()
39 OFFSET(TASK_stack_canary, task_struct, stack_canary); in common()
43 OFFSET(pbe_address, pbe, address); in common()
44 OFFSET(pbe_orig_address, pbe, orig_address); in common()
45 OFFSET(pbe_next, pbe, next); in common()
49 OFFSET(IA32_SIGCONTEXT_ax, sigcontext_32, ax); in common()
50 OFFSET(IA32_SIGCONTEXT_bx, sigcontext_32, bx); in common()
51 OFFSET(IA32_SIGCONTEXT_cx, sigcontext_32, cx); in common()
52 OFFSET(IA32_SIGCONTEXT_dx, sigcontext_32, dx); in common()
53 OFFSET(IA32_SIGCONTEXT_si, sigcontext_32, si); in common()
[all …]

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