Lines Matching full:offset
143 static void sprd_eic_update(struct gpio_chip *chip, unsigned int offset, in sprd_eic_update() argument
148 sprd_eic_offset_base(sprd_eic, offset / SPRD_EIC_PER_BANK_NR); in sprd_eic_update()
156 tmp |= BIT(SPRD_EIC_BIT(offset)); in sprd_eic_update()
158 tmp &= ~BIT(SPRD_EIC_BIT(offset)); in sprd_eic_update()
164 static int sprd_eic_read(struct gpio_chip *chip, unsigned int offset, u16 reg) in sprd_eic_read() argument
168 sprd_eic_offset_base(sprd_eic, offset / SPRD_EIC_PER_BANK_NR); in sprd_eic_read()
170 return !!(readl_relaxed(base + reg) & BIT(SPRD_EIC_BIT(offset))); in sprd_eic_read()
173 static int sprd_eic_request(struct gpio_chip *chip, unsigned int offset) in sprd_eic_request() argument
175 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_DMSK, 1); in sprd_eic_request()
179 static void sprd_eic_free(struct gpio_chip *chip, unsigned int offset) in sprd_eic_free() argument
181 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_DMSK, 0); in sprd_eic_free()
184 static int sprd_eic_get(struct gpio_chip *chip, unsigned int offset) in sprd_eic_get() argument
190 return sprd_eic_read(chip, offset, SPRD_EIC_DBNC_DATA); in sprd_eic_get()
192 return sprd_eic_read(chip, offset, SPRD_EIC_ASYNC_DATA); in sprd_eic_get()
194 return sprd_eic_read(chip, offset, SPRD_EIC_SYNC_DATA); in sprd_eic_get()
200 static int sprd_eic_direction_input(struct gpio_chip *chip, unsigned int offset) in sprd_eic_direction_input() argument
206 static int sprd_eic_set(struct gpio_chip *chip, unsigned int offset, int value) in sprd_eic_set() argument
212 static int sprd_eic_set_debounce(struct gpio_chip *chip, unsigned int offset, in sprd_eic_set_debounce() argument
217 sprd_eic_offset_base(sprd_eic, offset / SPRD_EIC_PER_BANK_NR); in sprd_eic_set_debounce()
218 u32 reg = SPRD_EIC_DBNC_CTRL0 + SPRD_EIC_BIT(offset) * 0x4; in sprd_eic_set_debounce()
227 static int sprd_eic_set_config(struct gpio_chip *chip, unsigned int offset, in sprd_eic_set_config() argument
234 return sprd_eic_set_debounce(chip, offset, arg); in sprd_eic_set_config()
243 u32 offset = irqd_to_hwirq(data); in sprd_eic_irq_mask() local
247 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IE, 0); in sprd_eic_irq_mask()
248 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_TRIG, 0); in sprd_eic_irq_mask()
251 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTEN, 0); in sprd_eic_irq_mask()
254 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTIE, 0); in sprd_eic_irq_mask()
257 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTIE, 0); in sprd_eic_irq_mask()
263 gpiochip_disable_irq(chip, offset); in sprd_eic_irq_mask()
270 u32 offset = irqd_to_hwirq(data); in sprd_eic_irq_unmask() local
272 gpiochip_enable_irq(chip, offset); in sprd_eic_irq_unmask()
276 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IE, 1); in sprd_eic_irq_unmask()
277 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_TRIG, 1); in sprd_eic_irq_unmask()
280 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTEN, 1); in sprd_eic_irq_unmask()
283 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTIE, 1); in sprd_eic_irq_unmask()
286 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTIE, 1); in sprd_eic_irq_unmask()
297 u32 offset = irqd_to_hwirq(data); in sprd_eic_irq_ack() local
301 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IC, 1); in sprd_eic_irq_ack()
304 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTCLR, 1); in sprd_eic_irq_ack()
307 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1); in sprd_eic_irq_ack()
310 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1); in sprd_eic_irq_ack()
321 u32 offset = irqd_to_hwirq(data); in sprd_eic_irq_set_type() local
328 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 1); in sprd_eic_irq_set_type()
329 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IC, 1); in sprd_eic_irq_set_type()
332 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 0); in sprd_eic_irq_set_type()
333 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IC, 1); in sprd_eic_irq_set_type()
338 state = sprd_eic_get(chip, offset); in sprd_eic_irq_set_type()
340 sprd_eic_update(chip, offset, in sprd_eic_irq_set_type()
342 sprd_eic_update(chip, offset, in sprd_eic_irq_set_type()
345 sprd_eic_update(chip, offset, in sprd_eic_irq_set_type()
347 sprd_eic_update(chip, offset, in sprd_eic_irq_set_type()
360 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 0); in sprd_eic_irq_set_type()
361 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTCLR, 1); in sprd_eic_irq_set_type()
364 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 1); in sprd_eic_irq_set_type()
365 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTCLR, 1); in sprd_eic_irq_set_type()
370 state = sprd_eic_get(chip, offset); in sprd_eic_irq_set_type()
372 sprd_eic_update(chip, offset, in sprd_eic_irq_set_type()
374 sprd_eic_update(chip, offset, in sprd_eic_irq_set_type()
377 sprd_eic_update(chip, offset, in sprd_eic_irq_set_type()
379 sprd_eic_update(chip, offset, in sprd_eic_irq_set_type()
392 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0); in sprd_eic_irq_set_type()
393 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0); in sprd_eic_irq_set_type()
394 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 1); in sprd_eic_irq_set_type()
395 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1); in sprd_eic_irq_set_type()
399 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0); in sprd_eic_irq_set_type()
400 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0); in sprd_eic_irq_set_type()
401 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 0); in sprd_eic_irq_set_type()
402 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1); in sprd_eic_irq_set_type()
406 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0); in sprd_eic_irq_set_type()
407 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 1); in sprd_eic_irq_set_type()
408 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1); in sprd_eic_irq_set_type()
412 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0); in sprd_eic_irq_set_type()
413 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 1); in sprd_eic_irq_set_type()
414 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 1); in sprd_eic_irq_set_type()
415 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1); in sprd_eic_irq_set_type()
419 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0); in sprd_eic_irq_set_type()
420 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 1); in sprd_eic_irq_set_type()
421 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 0); in sprd_eic_irq_set_type()
422 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1); in sprd_eic_irq_set_type()
432 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0); in sprd_eic_irq_set_type()
433 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0); in sprd_eic_irq_set_type()
434 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 1); in sprd_eic_irq_set_type()
435 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1); in sprd_eic_irq_set_type()
439 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0); in sprd_eic_irq_set_type()
440 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0); in sprd_eic_irq_set_type()
441 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 0); in sprd_eic_irq_set_type()
442 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1); in sprd_eic_irq_set_type()
446 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0); in sprd_eic_irq_set_type()
447 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 1); in sprd_eic_irq_set_type()
448 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1); in sprd_eic_irq_set_type()
452 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0); in sprd_eic_irq_set_type()
453 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 1); in sprd_eic_irq_set_type()
454 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 1); in sprd_eic_irq_set_type()
455 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1); in sprd_eic_irq_set_type()
459 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0); in sprd_eic_irq_set_type()
460 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 1); in sprd_eic_irq_set_type()
461 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 0); in sprd_eic_irq_set_type()
462 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1); in sprd_eic_irq_set_type()
478 unsigned int offset) in sprd_eic_toggle_trigger() argument
495 state = sprd_eic_get(chip, offset); in sprd_eic_toggle_trigger()
501 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 0); in sprd_eic_toggle_trigger()
503 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 1); in sprd_eic_toggle_trigger()
507 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 0); in sprd_eic_toggle_trigger()
509 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 1); in sprd_eic_toggle_trigger()
516 post_state = sprd_eic_get(chip, offset); in sprd_eic_toggle_trigger()
558 u32 offset = bank * SPRD_EIC_PER_BANK_NR + n; in sprd_eic_handle_one_type() local
560 girq = irq_find_mapping(chip->irq.domain, offset); in sprd_eic_handle_one_type()
563 sprd_eic_toggle_trigger(chip, girq, offset); in sprd_eic_handle_one_type()