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Searched +full:nr +full:- +full:irqs (Results 1 – 17 of 17) sorted by relevance

/freebsd/sys/contrib/device-tree/src/arm/marvell/
H A Dmmp3.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
6 #include <dt-bindings/clock/marvell,mmp2.h>
7 #include <dt-bindings/power/marvell,mmp2.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
17 enable-method = "marvell,mmp3-smp";
22 next-level-cache = <&l2>;
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H A Dmmp2.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/clock/marvell,mmp2.h>
8 #include <dt-bindings/power/marvell,mmp2.h>
9 #include <dt-bindings/clock/marvell,mmp2-audio.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
25 #address-cells = <1>;
26 #size-cells = <1>;
27 compatible = "simple-bus";
28 interrupt-parent = <&intc>;
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H A Dpxa910.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/clock/marvell,pxa910.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
22 #address-cells = <1>;
23 #size-cells = <1>;
24 compatible = "simple-bu
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H A Dpxa168.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/clock/marvell,pxa168.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
22 #address-cells = <1>;
23 #size-cells = <1>;
24 compatible = "simple-bu
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/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dmrvl,intc.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/mrvl,intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Gregory Clement <gregory.clement@bootlin.com>
14 - if:
19 const: marvell,orion-intc
22 - mrvl,intc-nr-irqs
23 - if:
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H A Dmrvl,intc.txt4 - compatible : Should be
5 "mrvl,mmp-intc" on Marvel MMP,
6 "mrvl,mmp2-intc" along with "mrvl,mmp2-mux-intc" on MMP2 or
7 "marvell,mmp3-intc" with "mrvl,mmp2-mux-intc" on MMP3
8 - reg : Address and length of the register set of the interrupt controller.
10 of the whole interrupt controller. The "marvell,mmp3-intc" controller
12 controller is mux-intc, address and length means one register. Since
13 address of mux-intc is in the range of intc. mux-intc is secondary
15 - reg-names : Name of the register set of the interrupt controller. It's
16 only required in mux-intc interrupt controller.
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/freebsd/sys/contrib/device-tree/Bindings/gpio/
H A Dgpio-xgene-sb.txt1 APM X-Gene Standby GPIO controller bindings
6 +---------
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H A Dapm,xgene-gpio-sb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/apm,xgene-gpio-sb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: APM X-Gene Standby GPIO controller
10 - Khuong Dinh <khuong@os.amperecomputing.com>
16 +-----------------+
17 | X-Gene standby |
18 | GPIO controller +------ GPIO_0
19 +------------+ | | ...
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/freebsd/sys/arm/ti/
H A Dti_pruss.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
175 { -1, 0, 0 }
177 CTASSERT(TI_PRUSS_HOST_IRQS == nitems(ti_pruss_irq_spec) - 1);
182 struct ctl* irqs; in ti_pruss_irq_open() local
184 sc = dev->si_drv1; in ti_pruss_irq_open()
186 irqs = malloc(sizeof(struct ctl), M_DEVBUF, M_WAITOK); in ti_pruss_irq_open()
187 irqs->cnt = sc->tstamps.ctl.cnt; in ti_pruss_irq_open()
188 irqs->idx = sc->tstamps.ctl.idx; in ti_pruss_irq_open()
190 return devfs_set_cdevpriv(irqs, ti_pruss_privdtor); in ti_pruss_irq_open()
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/freebsd/sys/contrib/device-tree/src/arm/intel/pxa/
H A Dpxa25x.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include "dt-bindings/clock/pxa-clock.h"
17 #address-cells = <1>;
18 #size-cells = <1>;
22 compatible = "marvell,pxa250-core-clocks";
23 #clock-cells = <1>;
29 compatible = "fixed-clock";
30 #clock-cells = <0>;
31 clock-frequency = <3686400>;
32 clock-output-names = "ostimer";
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H A Dpxa2xx.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * pxa2xx.dtsi - Device Tree Include file for Marvell PXA2xx family SoC
8 #include "dt-bindings/clock/pxa-clock.h"
12 mux- ## func { \
17 mux- ## func { \
20 low-power-disable; \
23 mux- ## func { \
26 low-power-enable; \
30 #address-cells = <1>;
31 #size-cells = <1>;
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H A Dpxa27x.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include "dt-bindings/clock/pxa-clock.h"
11 pdma: dma-controller@40000000 {
12 compatible = "marvell,pdma-1.0";
15 #dma-cells = <2>;
17 #dma-channels = <32>;
18 dma-channels = <32>;
19 #dma-requests = <75>;
20 dma-requests = <75>;
24 pxairq: interrupt-controller@40d00000 {
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H A Dpxa3xx.dtsi1 // SPDX-License-Identifier: GPL-2.0
7 (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) : \
8 (gpio <= 98) ? (0x0400 + 4 * (gpio - 27)) : \
9 (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \
18 (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) : \
19 (gpio <= 29) ? (0x0400 + 4 * (gpio - 27)) : \
20 (gpio <= 98) ? (0x0418 + 4 * (gpio - 30)) : \
21 (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \
23 (gpio <= 268) ? (0x052c + 4 * (gpio - 263)) : \
33 (gpio <= 9) ? (0x028c + 4 * (gpio - 5)) : \
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/freebsd/sys/arm/mv/
H A Dmv_ap806_gicp.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
50 #include <dt-bindings/interrupt-controller/irq.h>
69 ssize_t msi_bitmap_size; /* Nr of bits in the bitmap. */
74 {"marvell,ap806-gicp", 1},
78 #define RD4(sc, reg) bus_read_4((sc)->res, (reg))
79 #define WR4(sc, reg, val) bus_write_4((sc)->res, (reg), (val))
92 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) in mv_ap806_gicp_probe()
107 sc->dev = dev; in mv_ap806_gicp_attach()
116 if ((sc->parent = OF_device_from_xref(intr_parent)) == NULL) { in mv_ap806_gicp_attach()
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/freebsd/sys/contrib/device-tree/src/arm64/apm/
H A Dapm-shadowcat.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * dts file for AppliedMicro (APM) X-Gene Shadowcat SOC
9 compatible = "apm,xgene-shadowcat";
10 interrupt-parent = <&gic>;
11 #address-cells = <2>;
12 #size-cells = <2>;
15 #address-cells = <2>;
16 #size-cells = <0>;
22 enable-method = "spin-table";
23 cpu-release-addr = <0x1 0x0000fff8>;
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/freebsd/sys/dev/ixgbe/
H A Dif_ix.c3 Copyright (c) 2001-2017, Intel Corporation
48 static const char ixgbe_driver_version[] = "5.0.1-k";
93 "Intel(R) X520-T 82599 LOM"),
105 "Intel(R) X520-1 82599EN (SFP+)"),
107 "Intel(R) X520-4 82599 (Quad SFP+)"),
109 "Intel(R) X520-Q1 82599 (QSFP+)"),
111 "Intel(R) X540-AT2"),
112 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1, "Intel(R) X540-T1"),
113 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T, "Intel(R) X550-T2"),
114 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1, "Intel(R) X550-T1"),
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/freebsd/sys/dev/bxe/
H A Dbxe.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2007-2014 QLogic Corporation. All rights reserved.
64 * FLR Support - bxe_pf_flr_clnup() is called during nic_load in the per
241 static int load_count[2][3] = { {0} }; /* per-path: 0-common, 1-port0, 2-port1 */
253 /* Interrupt Mode: 0 (IRQ), 1 (MSI/IRQ), and 2 (MSI-X/MSI/IRQ) */
256 &bxe_interrupt_mode, 0, "Interrupt (MSI-X/MSI/INTx) mode");
261 &bxe_queue_count, 0, "Multi-Queue queue count");
288 /* PCI MRRS: -1 (Auto), 0 (128B), 1 (256B), 2 (512B), 3 (1KB) */
289 static int bxe_mrrs = -1;
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