| /freebsd/lib/libpmc/ |
| H A D | pmc.haswelluc.3 | 45 .Bl -tag -width "Li PMC_CLASS_UCP"
47 Fixed-function counters that count only one hardware event per counter.
49 Programmable counters that may be configured to count one of a defined
59 .%B "Intel(R) 64 and IA-32 Architectures Software Developers Manual"
61 .%N "Order Number: 325462-045US"
68 Not all CPUs in this family implement fixed-function counters.
69 .Ss HASWELL UNCORE PROGRAMMABLE PMCS
70 The programmable PMCs support the following capabilities:
71 .Bl -column "PMC_CAP_INTERRUPT" "Support"
88 .Bl -tag -width indent
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| H A D | pmc.3 | 1 .\" Copyright (c) 2003-2008 Joseph Koshy. All rights reserved.
40 The library is implemented using the lower-level facilities offered by
50 .Bl -bullet
53 These PMCs measure events in a whole-system manner, i.e., independent
57 Non-privileged process are allowed to allocate system scope PMCs if the
61 is non-zero.
72 .Bl -bullet
90 The library uses human-readable strings to name the event being
99 Additionally, process-scope PMCs have to be attached to one or more
101 A process-scope PMC may be attached to those target processes
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| H A D | pmc.atomsilvermont.3 | 45 .Bl -tag -width "Li PMC_CLASS_IAP"
47 Fixed-function counters that count only one hardware event per counter.
49 Programmable counters that may be configured to count one of a defined
59 .%B "Intel 64 and IA-32 Intel(R) Architecture Software Developer's Manual"
61 .%N "Order Number 325462-050US"
68 .Ss ATOM SILVERMONT PROGRAMMABLE PMCS
69 The programmable PMCs support the following capabilities:
70 .Bl -column "PMC_CAP_INTERRUPT" "Support"
87 .Bl -tag -width indent
95 Configure the PMC to count the number of de-asserted to asserted
[all …]
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| H A D | pmc.atom.3 | 44 .Bl -tag -width "Li PMC_CLASS_IAP"
46 Fixed-function counters that count only one hardware event per counter.
48 Programmable counters that may be configured to count one of a defined
58 .%B "IA-32 Intel(R) Architecture Software Developer's Manual"
60 .%N "Order Number 253669-027US"
67 .Ss ATOM PROGRAMMABLE PMCS
68 The programmable PMCs support the following capabilities:
69 .Bl -column "PMC_CAP_INTERRUPT" "Support"
86 .Bl -tag -width indent
94 Configure the PMC to count the number of de-asserted to asserted
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| H A D | pmc.core2.3 | 44 .Bl -tag -width "Li PMC_CLASS_IAP"
46 Fixed-function counters that count only one hardware event per counter.
48 Programmable counters that may be configured to count one of a defined
58 .%B "IA-32 Intel(R) Architecture Software Developer's Manual"
60 .%N "Order Number 253669-027US"
67 Not all CPUs in this family implement fixed-function counters.
68 .Ss CORE2 PROGRAMMABLE PMCS
69 The programmable PMCs support the following capabilities:
70 .Bl -column "PMC_CAP_INTERRUPT" "Support"
87 .Bl -tag -width indent
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| H A D | pmc.haswell.3 | 45 .Bl -tag -width "Li PMC_CLASS_IAP"
47 Fixed-function counters that count only one hardware event per counter.
49 Programmable counters that may be configured to count one of a defined
59 .%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual"
61 .%N "Order Number: 325462-045US"
68 .Ss HASWELL PROGRAMMABLE PMCS
69 The programmable PMCs support the following capabilities:
70 .Bl -column "PMC_CAP_INTERRUPT" "Support"
87 .Bl -tag -width indent
89 Configure the Off-core Response bits.
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| H A D | pmc.ivybridgexeon.3 | 45 .Bl -tag -width "Li PMC_CLASS_IAP"
47 Fixed-function counters that count only one hardware event per counter.
49 Programmable counters that may be configured to count one of a defined
59 .%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual"
60 .%N "Order Number: 325462-045US"
67 .Ss IVYBRIDGE PROGRAMMABLE PMCS
68 The programmable PMCs support the following capabilities:
69 .Bl -column "PMC_CAP_INTERRUPT" "Support"
86 .Bl -tag -width indent
88 Configure the Off-core Response bits.
[all …]
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| H A D | pmc.haswellxeon.3 | 46 .Bl -tag -width "Li PMC_CLASS_IAP"
48 Fixed-function counters that count only one hardware event per counter.
50 Programmable counters that may be configured to count one of a defined
60 .%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual"
62 .%N "Order Number: 325462-052US"
69 .Ss HASWELL PROGRAMMABLE PMCS
70 The programmable PMCs support the following capabilities:
71 .Bl -column "PMC_CAP_INTERRUPT" "Support"
88 .Bl -tag -width indent
90 Configure the Off-core Response bits.
[all …]
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| H A D | pmc.ivybridge.3 | 44 .Bl -tag -width "Li PMC_CLASS_IAP"
46 Fixed-function counters that count only one hardware event per counter.
48 Programmable counters that may be configured to count one of a defined
58 .%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual"
60 .%N "Order Number: 253669-043US"
67 .Ss IVYBRIDGE PROGRAMMABLE PMCS
68 The programmable PMCs support the following capabilities:
69 .Bl -column "PMC_CAP_INTERRUPT" "Support"
86 .Bl -tag -width indent
88 Configure the Off-core Response bits.
[all …]
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| H A D | pmc.corei7uc.3 | 44 .Bl -tag -width "Li PMC_CLASS_UCP"
46 Fixed-function counters that count only one hardware event per counter.
48 Programmable counters that may be configured to count one of a defined
58 .%B "Intel(R) 64 and IA-32 Architectures Software Developes Manual"
60 .%N "Order Number: 253669-033US"
67 .Ss COREI7 AND XEON 5500 UNCORE PROGRAMMABLE PMCS
68 The programmable PMCs support the following capabilities:
69 .Bl -column "PMC_CAP_INTERRUPT" "Support"
86 .Bl -tag -width indent
92 Configure the PMC to count the number of de-asserted to asserted
[all …]
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| H A D | pmc.corei7.3 | 44 .Bl -tag -width "Li PMC_CLASS_IAP"
46 Fixed-function counters that count only one hardware event per counter.
48 Programmable counters that may be configured to count one of a defined
58 .%B "Intel(R) 64 and IA-32 Architectures Software Developes Manual"
60 .%N "Order Number: 253669-033US"
67 Not all CPUs in this family implement fixed-function counters.
68 .Ss COREI7 AND XEON 5500 PROGRAMMABLE PMCS
69 The programmable PMCs support the following capabilities:
70 .Bl -column "PMC_CAP_INTERRUPT" "Support"
87 .Bl -tag -width indent
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| H A D | pmc.sandybridge.3 | 45 .Bl -tag -width "Li PMC_CLASS_IAP"
47 Fixed-function counters that count only one hardware event per counter.
49 Programmable counters that may be configured to count one of a defined
62 .%B "Intel(R) 64 and IA-32 Architectures Software Developers Manual"
64 .%N "Order Number: 253669-039US"
71 .Ss SANDY BRIDGE PROGRAMMABLE PMCS
72 The programmable PMCs support the following capabilities:
73 .Bl -column "PMC_CAP_INTERRUPT" "Support"
90 .Bl -tag -width indent
92 Configure the Off-core Response bits.
[all …]
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| H A D | pmc.sandybridgexeon.3 | 45 .Bl -tag -width "Li PMC_CLASS_IAP"
47 Fixed-function counters that count only one hardware event per counter.
49 Programmable counters that may be configured to count one of a defined
59 .%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual"
61 .%N "Order Number: 253669-043US"
68 .Ss SANDYBRIDGE XEON PROGRAMMABLE PMCS
69 The programmable PMCs support the following capabilities:
70 .Bl -column "PMC_CAP_INTERRUPT" "Support"
87 .Bl -tag -width indent
89 Configure the Off-core Response bits.
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| /freebsd/sys/contrib/device-tree/Bindings/display/bridge/ |
| H A D | simple-bridge.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/simple-bridge.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Transparent non-programmable DRM bridges
10 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
11 - Maxime Ripard <mripard@kernel.org>
14 This binding supports transparent non-programmable bridges that don't require
20 - items:
21 - enum:
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| /freebsd/sys/contrib/device-tree/Bindings/display/xlnx/ |
| H A D | xlnx,zynqmp-dpsub.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/xlnx/xlnx,zynqmp-dpsub.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 +------------------------------------------------------------+
15 +--------+ | +----------------+ +-----------+ |
16 | DPDMA | --->| | --> | Video | Video +-------------+ |
17 | 4x vid | | | | | Rendering | -+--> | | | +------+
18 | 2x aud | | | Audio/Video | --> | Pipeline | | | DisplayPort |---> | PHY0 |
19 +--------+ | | Buffer Manager | +-----------+ | | Source | | +------+
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| /freebsd/share/man/man4/ |
| H A D | ow_temp.4 | 1 .\"-
2 .\" SPDX-License-Identifier: BSD-2-Clause
31 .Nd Dallas Semiconductor 1-Wire Temperature sensor
37 module supports many of the 1-Wire temperature sensors.
47 .Bl -column "DS18S20" "Econo 1-Wire Digital Thermometer" -compact
48 .It DS1820 Ta 1-Wire Digital Thermometer
49 .It DS18S20 Ta High-Precision 1-Wire Digital Thermometer
50 .It DS18B20 Ta Programmable Resolution 1-Wire Digital Thermometer
51 .It DS1822 Ta Econo 1-Wire Digital Thermometer
52 .It DS1825 Ta Programmable Resolution 1-Wire Digital Thermometer with 4-bit ID
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| /freebsd/sys/contrib/device-tree/Bindings/iio/adc/ |
| H A D | aspeed,ast2600-adc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/aspeed,ast2600-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Billy Tsai <billy_tsai@aspeedtech.com>
13 • 10-bits resolution for 16 voltage channels.
16 • Channel scanning can be non-continuous.
17 • Programmable ADC clock frequency.
18 • Programmable upper and lower threshold for each channels.
21 • Built-in a compensating method.
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| /freebsd/sys/contrib/device-tree/Bindings/arm/ |
| H A D | arm,coresight-cti.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/arm/arm,coresight-ct
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| H A D | coresight-cti.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/arm/coresight-cti.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
13 a star topology via the Cross Trigger Matrix (CTM), which is not programmable.
26 programmable channels, usually 4, but again implementation defined and
29 programmable.
38 indicate this feature (arm,coresight-cti-v8-arch).
53 constants defined in <dt-bindings/arm/coresight-cti-dt.h>
60 Note that some hardware trigger signals can be connected to non-CoreSight
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| H A D | coresight.txt | 11 * Required properties for all components *except* non-configurable replicators
12 and non-configurable funnels:
16 - Embedded Trace Buffer (version 1.0):
17 "arm,coresight-etb10", "arm,primecell";
19 - Trace Port Interface Unit:
20 "arm,coresight-tpiu", "arm,primecell";
22 - Trace Memory Controller, used for Embedded Trace Buffer(ETB),
26 "arm,coresight-tmc", "arm,primecell";
28 - Trace Programmable Funnel:
29 "arm,coresight-dynamic-funnel", "arm,primecell";
[all …]
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| /freebsd/sys/dev/isci/scil/ |
| H A D | scic_sgpio.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause OR GPL-2.0
9 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
22 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
28 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
70 //Programmable Blink Pattern Durations
113 * @param]in] vendor_specific_sequence - Vendor specific sequence set in the
123 * @brief Use this to set both programmable blink patterns A & B in the
124 * SGPBR(Programmable Blink Register). Will set identical patterns
128 * @param[in] pattern_a_high - High(LED on) duration time for pattern A
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| /freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/ |
| H A D | opencores,or1k-pic.txt | 1 OpenRISC 1000 Programmable Interrupt Controller
5 - compatible : should be "opencores,or1k-pic-level" for variants with
6 level triggered interrupt lines, "opencores,or1k-pic-edge" for variants with
7 edge triggered interrupt lines or "opencores,or1200-pic" for machines
8 with the non-spec compliant or1200 type implementation.
10 "opencores,or1k-pic" is also provided as an alias to "opencores,or1200-pic",
13 - interrupt-controller : Identifies the node as an interrupt controller
14 - #interrupt-cells : Specifies the number of cells needed to encode an
19 intc: interrupt-controller {
20 compatible = "opencores,or1k-pic-level";
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| /freebsd/sys/contrib/device-tree/Bindings/fuse/ |
| H A D | renesas,rcar-otp.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fuse/renesas,rcar-otp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: R-Car E-FUSE connected to OTP_MEM
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 The E-FUSE is a type of non-volatile memory, which is accessible through the
14 One-Time Programmable Memory (OTP_MEM) module on some R-Car Gen4 SoCs.
19 - renesas,r8a779g0-otp # R-CarV4H
20 - renesas,r8a779h0-otp # R-CarV4M
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| /freebsd/sys/contrib/device-tree/Bindings/media/i2c/ |
| H A D | tc358743.txt | 1 * Toshiba TC358743 HDMI-RX to MIPI CSI2-TX Bridge
3 The Toshiba TC358743 HDMI-RX to MIPI CSI2-TX (H2C) is a bridge that converts
4 a HDMI stream to MIPI CSI-2 TX. It is programmable through I2C.
8 - compatible: value should be "toshiba,tc358743"
9 - clocks, clock-names: should contain a phandle link to the reference clock
14 - reset-gpios: gpio phandle GPIO connected to the reset pin
15 - interrupts: GPIO connected to the interrupt pin
16 - data-lanes: should be <1 2 3 4> for four-lane operation,
17 or <1 2> for two-lane operation
18 - clock-lanes: should be <0>
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| /freebsd/lib/libpmc/pmu-events/arch/x86/nehalemex/ |
| H A D | pipeline.json | 107 "BriefDescription": "Indirect non call branches executed"
123 "BriefDescription": "All non call branches executed"
198 "BriefDescription": "Mispredicted non call branches executed"
214 "BriefDescription": "Mispredicted indirect non call branches executed"
230 "BriefDescription": "Mispredicted non call branches executed"
271 …cription": "Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)"
287 "BriefDescription": "Cycles when thread is not halted (programmable counter)"
378 "BriefDescription": "Instructions retired (Programmable counter and Precise Event)"
407 "BriefDescription": "Retired floating-point operations (Precise Event)"
466 "BriefDescription": "Self-Modifying Code detected"
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