xref: /freebsd/lib/libpmc/pmu-events/arch/x86/nehalemex/pipeline.json (revision 959826ca1bb0a42ddd624bf1803ae2957a3282f3)
1*959826caSMatt Macy[
2*959826caSMatt Macy    {
3*959826caSMatt Macy        "EventCode": "0x14",
4*959826caSMatt Macy        "Counter": "0,1,2,3",
5*959826caSMatt Macy        "UMask": "0x1",
6*959826caSMatt Macy        "EventName": "ARITH.CYCLES_DIV_BUSY",
7*959826caSMatt Macy        "SampleAfterValue": "2000000",
8*959826caSMatt Macy        "BriefDescription": "Cycles the divider is busy"
9*959826caSMatt Macy    },
10*959826caSMatt Macy    {
11*959826caSMatt Macy        "EventCode": "0x14",
12*959826caSMatt Macy        "Invert": "1",
13*959826caSMatt Macy        "Counter": "0,1,2,3",
14*959826caSMatt Macy        "UMask": "0x1",
15*959826caSMatt Macy        "EventName": "ARITH.DIV",
16*959826caSMatt Macy        "SampleAfterValue": "2000000",
17*959826caSMatt Macy        "BriefDescription": "Divide Operations executed",
18*959826caSMatt Macy        "CounterMask": "1",
19*959826caSMatt Macy        "EdgeDetect": "1"
20*959826caSMatt Macy    },
21*959826caSMatt Macy    {
22*959826caSMatt Macy        "EventCode": "0x14",
23*959826caSMatt Macy        "Counter": "0,1,2,3",
24*959826caSMatt Macy        "UMask": "0x2",
25*959826caSMatt Macy        "EventName": "ARITH.MUL",
26*959826caSMatt Macy        "SampleAfterValue": "2000000",
27*959826caSMatt Macy        "BriefDescription": "Multiply operations executed"
28*959826caSMatt Macy    },
29*959826caSMatt Macy    {
30*959826caSMatt Macy        "EventCode": "0xE6",
31*959826caSMatt Macy        "Counter": "0,1,2,3",
32*959826caSMatt Macy        "UMask": "0x2",
33*959826caSMatt Macy        "EventName": "BACLEAR.BAD_TARGET",
34*959826caSMatt Macy        "SampleAfterValue": "2000000",
35*959826caSMatt Macy        "BriefDescription": "BACLEAR asserted with bad target address"
36*959826caSMatt Macy    },
37*959826caSMatt Macy    {
38*959826caSMatt Macy        "EventCode": "0xE6",
39*959826caSMatt Macy        "Counter": "0,1,2,3",
40*959826caSMatt Macy        "UMask": "0x1",
41*959826caSMatt Macy        "EventName": "BACLEAR.CLEAR",
42*959826caSMatt Macy        "SampleAfterValue": "2000000",
43*959826caSMatt Macy        "BriefDescription": "BACLEAR asserted, regardless of cause "
44*959826caSMatt Macy    },
45*959826caSMatt Macy    {
46*959826caSMatt Macy        "EventCode": "0xA7",
47*959826caSMatt Macy        "Counter": "0,1,2,3",
48*959826caSMatt Macy        "UMask": "0x1",
49*959826caSMatt Macy        "EventName": "BACLEAR_FORCE_IQ",
50*959826caSMatt Macy        "SampleAfterValue": "2000000",
51*959826caSMatt Macy        "BriefDescription": "Instruction queue forced BACLEAR"
52*959826caSMatt Macy    },
53*959826caSMatt Macy    {
54*959826caSMatt Macy        "EventCode": "0xE0",
55*959826caSMatt Macy        "Counter": "0,1,2,3",
56*959826caSMatt Macy        "UMask": "0x1",
57*959826caSMatt Macy        "EventName": "BR_INST_DECODED",
58*959826caSMatt Macy        "SampleAfterValue": "2000000",
59*959826caSMatt Macy        "BriefDescription": "Branch instructions decoded"
60*959826caSMatt Macy    },
61*959826caSMatt Macy    {
62*959826caSMatt Macy        "EventCode": "0x88",
63*959826caSMatt Macy        "Counter": "0,1,2,3",
64*959826caSMatt Macy        "UMask": "0x7f",
65*959826caSMatt Macy        "EventName": "BR_INST_EXEC.ANY",
66*959826caSMatt Macy        "SampleAfterValue": "200000",
67*959826caSMatt Macy        "BriefDescription": "Branch instructions executed"
68*959826caSMatt Macy    },
69*959826caSMatt Macy    {
70*959826caSMatt Macy        "EventCode": "0x88",
71*959826caSMatt Macy        "Counter": "0,1,2,3",
72*959826caSMatt Macy        "UMask": "0x1",
73*959826caSMatt Macy        "EventName": "BR_INST_EXEC.COND",
74*959826caSMatt Macy        "SampleAfterValue": "200000",
75*959826caSMatt Macy        "BriefDescription": "Conditional branch instructions executed"
76*959826caSMatt Macy    },
77*959826caSMatt Macy    {
78*959826caSMatt Macy        "EventCode": "0x88",
79*959826caSMatt Macy        "Counter": "0,1,2,3",
80*959826caSMatt Macy        "UMask": "0x2",
81*959826caSMatt Macy        "EventName": "BR_INST_EXEC.DIRECT",
82*959826caSMatt Macy        "SampleAfterValue": "200000",
83*959826caSMatt Macy        "BriefDescription": "Unconditional branches executed"
84*959826caSMatt Macy    },
85*959826caSMatt Macy    {
86*959826caSMatt Macy        "EventCode": "0x88",
87*959826caSMatt Macy        "Counter": "0,1,2,3",
88*959826caSMatt Macy        "UMask": "0x10",
89*959826caSMatt Macy        "EventName": "BR_INST_EXEC.DIRECT_NEAR_CALL",
90*959826caSMatt Macy        "SampleAfterValue": "20000",
91*959826caSMatt Macy        "BriefDescription": "Unconditional call branches executed"
92*959826caSMatt Macy    },
93*959826caSMatt Macy    {
94*959826caSMatt Macy        "EventCode": "0x88",
95*959826caSMatt Macy        "Counter": "0,1,2,3",
96*959826caSMatt Macy        "UMask": "0x20",
97*959826caSMatt Macy        "EventName": "BR_INST_EXEC.INDIRECT_NEAR_CALL",
98*959826caSMatt Macy        "SampleAfterValue": "20000",
99*959826caSMatt Macy        "BriefDescription": "Indirect call branches executed"
100*959826caSMatt Macy    },
101*959826caSMatt Macy    {
102*959826caSMatt Macy        "EventCode": "0x88",
103*959826caSMatt Macy        "Counter": "0,1,2,3",
104*959826caSMatt Macy        "UMask": "0x4",
105*959826caSMatt Macy        "EventName": "BR_INST_EXEC.INDIRECT_NON_CALL",
106*959826caSMatt Macy        "SampleAfterValue": "20000",
107*959826caSMatt Macy        "BriefDescription": "Indirect non call branches executed"
108*959826caSMatt Macy    },
109*959826caSMatt Macy    {
110*959826caSMatt Macy        "EventCode": "0x88",
111*959826caSMatt Macy        "Counter": "0,1,2,3",
112*959826caSMatt Macy        "UMask": "0x30",
113*959826caSMatt Macy        "EventName": "BR_INST_EXEC.NEAR_CALLS",
114*959826caSMatt Macy        "SampleAfterValue": "20000",
115*959826caSMatt Macy        "BriefDescription": "Call branches executed"
116*959826caSMatt Macy    },
117*959826caSMatt Macy    {
118*959826caSMatt Macy        "EventCode": "0x88",
119*959826caSMatt Macy        "Counter": "0,1,2,3",
120*959826caSMatt Macy        "UMask": "0x7",
121*959826caSMatt Macy        "EventName": "BR_INST_EXEC.NON_CALLS",
122*959826caSMatt Macy        "SampleAfterValue": "200000",
123*959826caSMatt Macy        "BriefDescription": "All non call branches executed"
124*959826caSMatt Macy    },
125*959826caSMatt Macy    {
126*959826caSMatt Macy        "EventCode": "0x88",
127*959826caSMatt Macy        "Counter": "0,1,2,3",
128*959826caSMatt Macy        "UMask": "0x8",
129*959826caSMatt Macy        "EventName": "BR_INST_EXEC.RETURN_NEAR",
130*959826caSMatt Macy        "SampleAfterValue": "20000",
131*959826caSMatt Macy        "BriefDescription": "Indirect return branches executed"
132*959826caSMatt Macy    },
133*959826caSMatt Macy    {
134*959826caSMatt Macy        "EventCode": "0x88",
135*959826caSMatt Macy        "Counter": "0,1,2,3",
136*959826caSMatt Macy        "UMask": "0x40",
137*959826caSMatt Macy        "EventName": "BR_INST_EXEC.TAKEN",
138*959826caSMatt Macy        "SampleAfterValue": "200000",
139*959826caSMatt Macy        "BriefDescription": "Taken branches executed"
140*959826caSMatt Macy    },
141*959826caSMatt Macy    {
142*959826caSMatt Macy        "PEBS": "1",
143*959826caSMatt Macy        "EventCode": "0xC4",
144*959826caSMatt Macy        "Counter": "0,1,2,3",
145*959826caSMatt Macy        "UMask": "0x4",
146*959826caSMatt Macy        "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
147*959826caSMatt Macy        "SampleAfterValue": "200000",
148*959826caSMatt Macy        "BriefDescription": "Retired branch instructions (Precise Event)"
149*959826caSMatt Macy    },
150*959826caSMatt Macy    {
151*959826caSMatt Macy        "PEBS": "1",
152*959826caSMatt Macy        "EventCode": "0xC4",
153*959826caSMatt Macy        "Counter": "0,1,2,3",
154*959826caSMatt Macy        "UMask": "0x1",
155*959826caSMatt Macy        "EventName": "BR_INST_RETIRED.CONDITIONAL",
156*959826caSMatt Macy        "SampleAfterValue": "200000",
157*959826caSMatt Macy        "BriefDescription": "Retired conditional branch instructions (Precise Event)"
158*959826caSMatt Macy    },
159*959826caSMatt Macy    {
160*959826caSMatt Macy        "PEBS": "1",
161*959826caSMatt Macy        "EventCode": "0xC4",
162*959826caSMatt Macy        "Counter": "0,1,2,3",
163*959826caSMatt Macy        "UMask": "0x2",
164*959826caSMatt Macy        "EventName": "BR_INST_RETIRED.NEAR_CALL",
165*959826caSMatt Macy        "SampleAfterValue": "20000",
166*959826caSMatt Macy        "BriefDescription": "Retired near call instructions (Precise Event)"
167*959826caSMatt Macy    },
168*959826caSMatt Macy    {
169*959826caSMatt Macy        "EventCode": "0x89",
170*959826caSMatt Macy        "Counter": "0,1,2,3",
171*959826caSMatt Macy        "UMask": "0x7f",
172*959826caSMatt Macy        "EventName": "BR_MISP_EXEC.ANY",
173*959826caSMatt Macy        "SampleAfterValue": "20000",
174*959826caSMatt Macy        "BriefDescription": "Mispredicted branches executed"
175*959826caSMatt Macy    },
176*959826caSMatt Macy    {
177*959826caSMatt Macy        "EventCode": "0x89",
178*959826caSMatt Macy        "Counter": "0,1,2,3",
179*959826caSMatt Macy        "UMask": "0x1",
180*959826caSMatt Macy        "EventName": "BR_MISP_EXEC.COND",
181*959826caSMatt Macy        "SampleAfterValue": "20000",
182*959826caSMatt Macy        "BriefDescription": "Mispredicted conditional branches executed"
183*959826caSMatt Macy    },
184*959826caSMatt Macy    {
185*959826caSMatt Macy        "EventCode": "0x89",
186*959826caSMatt Macy        "Counter": "0,1,2,3",
187*959826caSMatt Macy        "UMask": "0x2",
188*959826caSMatt Macy        "EventName": "BR_MISP_EXEC.DIRECT",
189*959826caSMatt Macy        "SampleAfterValue": "20000",
190*959826caSMatt Macy        "BriefDescription": "Mispredicted unconditional branches executed"
191*959826caSMatt Macy    },
192*959826caSMatt Macy    {
193*959826caSMatt Macy        "EventCode": "0x89",
194*959826caSMatt Macy        "Counter": "0,1,2,3",
195*959826caSMatt Macy        "UMask": "0x10",
196*959826caSMatt Macy        "EventName": "BR_MISP_EXEC.DIRECT_NEAR_CALL",
197*959826caSMatt Macy        "SampleAfterValue": "2000",
198*959826caSMatt Macy        "BriefDescription": "Mispredicted non call branches executed"
199*959826caSMatt Macy    },
200*959826caSMatt Macy    {
201*959826caSMatt Macy        "EventCode": "0x89",
202*959826caSMatt Macy        "Counter": "0,1,2,3",
203*959826caSMatt Macy        "UMask": "0x20",
204*959826caSMatt Macy        "EventName": "BR_MISP_EXEC.INDIRECT_NEAR_CALL",
205*959826caSMatt Macy        "SampleAfterValue": "2000",
206*959826caSMatt Macy        "BriefDescription": "Mispredicted indirect call branches executed"
207*959826caSMatt Macy    },
208*959826caSMatt Macy    {
209*959826caSMatt Macy        "EventCode": "0x89",
210*959826caSMatt Macy        "Counter": "0,1,2,3",
211*959826caSMatt Macy        "UMask": "0x4",
212*959826caSMatt Macy        "EventName": "BR_MISP_EXEC.INDIRECT_NON_CALL",
213*959826caSMatt Macy        "SampleAfterValue": "2000",
214*959826caSMatt Macy        "BriefDescription": "Mispredicted indirect non call branches executed"
215*959826caSMatt Macy    },
216*959826caSMatt Macy    {
217*959826caSMatt Macy        "EventCode": "0x89",
218*959826caSMatt Macy        "Counter": "0,1,2,3",
219*959826caSMatt Macy        "UMask": "0x30",
220*959826caSMatt Macy        "EventName": "BR_MISP_EXEC.NEAR_CALLS",
221*959826caSMatt Macy        "SampleAfterValue": "2000",
222*959826caSMatt Macy        "BriefDescription": "Mispredicted call branches executed"
223*959826caSMatt Macy    },
224*959826caSMatt Macy    {
225*959826caSMatt Macy        "EventCode": "0x89",
226*959826caSMatt Macy        "Counter": "0,1,2,3",
227*959826caSMatt Macy        "UMask": "0x7",
228*959826caSMatt Macy        "EventName": "BR_MISP_EXEC.NON_CALLS",
229*959826caSMatt Macy        "SampleAfterValue": "20000",
230*959826caSMatt Macy        "BriefDescription": "Mispredicted non call branches executed"
231*959826caSMatt Macy    },
232*959826caSMatt Macy    {
233*959826caSMatt Macy        "EventCode": "0x89",
234*959826caSMatt Macy        "Counter": "0,1,2,3",
235*959826caSMatt Macy        "UMask": "0x8",
236*959826caSMatt Macy        "EventName": "BR_MISP_EXEC.RETURN_NEAR",
237*959826caSMatt Macy        "SampleAfterValue": "2000",
238*959826caSMatt Macy        "BriefDescription": "Mispredicted return branches executed"
239*959826caSMatt Macy    },
240*959826caSMatt Macy    {
241*959826caSMatt Macy        "EventCode": "0x89",
242*959826caSMatt Macy        "Counter": "0,1,2,3",
243*959826caSMatt Macy        "UMask": "0x40",
244*959826caSMatt Macy        "EventName": "BR_MISP_EXEC.TAKEN",
245*959826caSMatt Macy        "SampleAfterValue": "20000",
246*959826caSMatt Macy        "BriefDescription": "Mispredicted taken branches executed"
247*959826caSMatt Macy    },
248*959826caSMatt Macy    {
249*959826caSMatt Macy        "PEBS": "1",
250*959826caSMatt Macy        "EventCode": "0xC5",
251*959826caSMatt Macy        "Counter": "0,1,2,3",
252*959826caSMatt Macy        "UMask": "0x2",
253*959826caSMatt Macy        "EventName": "BR_MISP_RETIRED.NEAR_CALL",
254*959826caSMatt Macy        "SampleAfterValue": "2000",
255*959826caSMatt Macy        "BriefDescription": "Mispredicted near retired calls (Precise Event)"
256*959826caSMatt Macy    },
257*959826caSMatt Macy    {
258*959826caSMatt Macy        "EventCode": "0x0",
259*959826caSMatt Macy        "Counter": "Fixed counter 3",
260*959826caSMatt Macy        "UMask": "0x0",
261*959826caSMatt Macy        "EventName": "CPU_CLK_UNHALTED.REF",
262*959826caSMatt Macy        "SampleAfterValue": "2000000",
263*959826caSMatt Macy        "BriefDescription": "Reference cycles when thread is not halted (fixed counter)"
264*959826caSMatt Macy    },
265*959826caSMatt Macy    {
266*959826caSMatt Macy        "EventCode": "0x3C",
267*959826caSMatt Macy        "Counter": "0,1,2,3",
268*959826caSMatt Macy        "UMask": "0x1",
269*959826caSMatt Macy        "EventName": "CPU_CLK_UNHALTED.REF_P",
270*959826caSMatt Macy        "SampleAfterValue": "100000",
271*959826caSMatt Macy        "BriefDescription": "Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)"
272*959826caSMatt Macy    },
273*959826caSMatt Macy    {
274*959826caSMatt Macy        "EventCode": "0x0",
275*959826caSMatt Macy        "Counter": "Fixed counter 2",
276*959826caSMatt Macy        "UMask": "0x0",
277*959826caSMatt Macy        "EventName": "CPU_CLK_UNHALTED.THREAD",
278*959826caSMatt Macy        "SampleAfterValue": "2000000",
279*959826caSMatt Macy        "BriefDescription": "Cycles when thread is not halted (fixed counter)"
280*959826caSMatt Macy    },
281*959826caSMatt Macy    {
282*959826caSMatt Macy        "EventCode": "0x3C",
283*959826caSMatt Macy        "Counter": "0,1,2,3",
284*959826caSMatt Macy        "UMask": "0x0",
285*959826caSMatt Macy        "EventName": "CPU_CLK_UNHALTED.THREAD_P",
286*959826caSMatt Macy        "SampleAfterValue": "2000000",
287*959826caSMatt Macy        "BriefDescription": "Cycles when thread is not halted (programmable counter)"
288*959826caSMatt Macy    },
289*959826caSMatt Macy    {
290*959826caSMatt Macy        "EventCode": "0x3C",
291*959826caSMatt Macy        "Invert": "1",
292*959826caSMatt Macy        "Counter": "0,1,2,3",
293*959826caSMatt Macy        "UMask": "0x0",
294*959826caSMatt Macy        "EventName": "CPU_CLK_UNHALTED.TOTAL_CYCLES",
295*959826caSMatt Macy        "SampleAfterValue": "2000000",
296*959826caSMatt Macy        "BriefDescription": "Total CPU cycles",
297*959826caSMatt Macy        "CounterMask": "2"
298*959826caSMatt Macy    },
299*959826caSMatt Macy    {
300*959826caSMatt Macy        "EventCode": "0x87",
301*959826caSMatt Macy        "Counter": "0,1,2,3",
302*959826caSMatt Macy        "UMask": "0xf",
303*959826caSMatt Macy        "EventName": "ILD_STALL.ANY",
304*959826caSMatt Macy        "SampleAfterValue": "2000000",
305*959826caSMatt Macy        "BriefDescription": "Any Instruction Length Decoder stall cycles"
306*959826caSMatt Macy    },
307*959826caSMatt Macy    {
308*959826caSMatt Macy        "EventCode": "0x87",
309*959826caSMatt Macy        "Counter": "0,1,2,3",
310*959826caSMatt Macy        "UMask": "0x4",
311*959826caSMatt Macy        "EventName": "ILD_STALL.IQ_FULL",
312*959826caSMatt Macy        "SampleAfterValue": "2000000",
313*959826caSMatt Macy        "BriefDescription": "Instruction Queue full stall cycles"
314*959826caSMatt Macy    },
315*959826caSMatt Macy    {
316*959826caSMatt Macy        "EventCode": "0x87",
317*959826caSMatt Macy        "Counter": "0,1,2,3",
318*959826caSMatt Macy        "UMask": "0x1",
319*959826caSMatt Macy        "EventName": "ILD_STALL.LCP",
320*959826caSMatt Macy        "SampleAfterValue": "2000000",
321*959826caSMatt Macy        "BriefDescription": "Length Change Prefix stall cycles"
322*959826caSMatt Macy    },
323*959826caSMatt Macy    {
324*959826caSMatt Macy        "EventCode": "0x87",
325*959826caSMatt Macy        "Counter": "0,1,2,3",
326*959826caSMatt Macy        "UMask": "0x2",
327*959826caSMatt Macy        "EventName": "ILD_STALL.MRU",
328*959826caSMatt Macy        "SampleAfterValue": "2000000",
329*959826caSMatt Macy        "BriefDescription": "Stall cycles due to BPU MRU bypass"
330*959826caSMatt Macy    },
331*959826caSMatt Macy    {
332*959826caSMatt Macy        "EventCode": "0x87",
333*959826caSMatt Macy        "Counter": "0,1,2,3",
334*959826caSMatt Macy        "UMask": "0x8",
335*959826caSMatt Macy        "EventName": "ILD_STALL.REGEN",
336*959826caSMatt Macy        "SampleAfterValue": "2000000",
337*959826caSMatt Macy        "BriefDescription": "Regen stall cycles"
338*959826caSMatt Macy    },
339*959826caSMatt Macy    {
340*959826caSMatt Macy        "EventCode": "0x18",
341*959826caSMatt Macy        "Counter": "0,1,2,3",
342*959826caSMatt Macy        "UMask": "0x1",
343*959826caSMatt Macy        "EventName": "INST_DECODED.DEC0",
344*959826caSMatt Macy        "SampleAfterValue": "2000000",
345*959826caSMatt Macy        "BriefDescription": "Instructions that must be decoded by decoder 0"
346*959826caSMatt Macy    },
347*959826caSMatt Macy    {
348*959826caSMatt Macy        "EventCode": "0x1E",
349*959826caSMatt Macy        "Counter": "0,1,2,3",
350*959826caSMatt Macy        "UMask": "0x1",
351*959826caSMatt Macy        "EventName": "INST_QUEUE_WRITE_CYCLES",
352*959826caSMatt Macy        "SampleAfterValue": "2000000",
353*959826caSMatt Macy        "BriefDescription": "Cycles instructions are written to the instruction queue"
354*959826caSMatt Macy    },
355*959826caSMatt Macy    {
356*959826caSMatt Macy        "EventCode": "0x17",
357*959826caSMatt Macy        "Counter": "0,1,2,3",
358*959826caSMatt Macy        "UMask": "0x1",
359*959826caSMatt Macy        "EventName": "INST_QUEUE_WRITES",
360*959826caSMatt Macy        "SampleAfterValue": "2000000",
361*959826caSMatt Macy        "BriefDescription": "Instructions written to instruction queue."
362*959826caSMatt Macy    },
363*959826caSMatt Macy    {
364*959826caSMatt Macy        "EventCode": "0x0",
365*959826caSMatt Macy        "Counter": "Fixed counter 1",
366*959826caSMatt Macy        "UMask": "0x0",
367*959826caSMatt Macy        "EventName": "INST_RETIRED.ANY",
368*959826caSMatt Macy        "SampleAfterValue": "2000000",
369*959826caSMatt Macy        "BriefDescription": "Instructions retired (fixed counter)"
370*959826caSMatt Macy    },
371*959826caSMatt Macy    {
372*959826caSMatt Macy        "PEBS": "1",
373*959826caSMatt Macy        "EventCode": "0xC0",
374*959826caSMatt Macy        "Counter": "0,1,2,3",
375*959826caSMatt Macy        "UMask": "0x1",
376*959826caSMatt Macy        "EventName": "INST_RETIRED.ANY_P",
377*959826caSMatt Macy        "SampleAfterValue": "2000000",
378*959826caSMatt Macy        "BriefDescription": "Instructions retired (Programmable counter and Precise Event)"
379*959826caSMatt Macy    },
380*959826caSMatt Macy    {
381*959826caSMatt Macy        "PEBS": "1",
382*959826caSMatt Macy        "EventCode": "0xC0",
383*959826caSMatt Macy        "Counter": "0,1,2,3",
384*959826caSMatt Macy        "UMask": "0x4",
385*959826caSMatt Macy        "EventName": "INST_RETIRED.MMX",
386*959826caSMatt Macy        "SampleAfterValue": "2000000",
387*959826caSMatt Macy        "BriefDescription": "Retired MMX instructions (Precise Event)"
388*959826caSMatt Macy    },
389*959826caSMatt Macy    {
390*959826caSMatt Macy        "PEBS": "1",
391*959826caSMatt Macy        "EventCode": "0xC0",
392*959826caSMatt Macy        "Invert": "1",
393*959826caSMatt Macy        "Counter": "0,1,2,3",
394*959826caSMatt Macy        "UMask": "0x1",
395*959826caSMatt Macy        "EventName": "INST_RETIRED.TOTAL_CYCLES",
396*959826caSMatt Macy        "SampleAfterValue": "2000000",
397*959826caSMatt Macy        "BriefDescription": "Total cycles (Precise Event)",
398*959826caSMatt Macy        "CounterMask": "16"
399*959826caSMatt Macy    },
400*959826caSMatt Macy    {
401*959826caSMatt Macy        "PEBS": "1",
402*959826caSMatt Macy        "EventCode": "0xC0",
403*959826caSMatt Macy        "Counter": "0,1,2,3",
404*959826caSMatt Macy        "UMask": "0x2",
405*959826caSMatt Macy        "EventName": "INST_RETIRED.X87",
406*959826caSMatt Macy        "SampleAfterValue": "2000000",
407*959826caSMatt Macy        "BriefDescription": "Retired floating-point operations (Precise Event)"
408*959826caSMatt Macy    },
409*959826caSMatt Macy    {
410*959826caSMatt Macy        "EventCode": "0x4C",
411*959826caSMatt Macy        "Counter": "0,1",
412*959826caSMatt Macy        "UMask": "0x1",
413*959826caSMatt Macy        "EventName": "LOAD_HIT_PRE",
414*959826caSMatt Macy        "SampleAfterValue": "200000",
415*959826caSMatt Macy        "BriefDescription": "Load operations conflicting with software prefetches"
416*959826caSMatt Macy    },
417*959826caSMatt Macy    {
418*959826caSMatt Macy        "EventCode": "0xA8",
419*959826caSMatt Macy        "Counter": "0,1,2,3",
420*959826caSMatt Macy        "UMask": "0x1",
421*959826caSMatt Macy        "EventName": "LSD.ACTIVE",
422*959826caSMatt Macy        "SampleAfterValue": "2000000",
423*959826caSMatt Macy        "BriefDescription": "Cycles when uops were delivered by the LSD",
424*959826caSMatt Macy        "CounterMask": "1"
425*959826caSMatt Macy    },
426*959826caSMatt Macy    {
427*959826caSMatt Macy        "EventCode": "0xA8",
428*959826caSMatt Macy        "Invert": "1",
429*959826caSMatt Macy        "Counter": "0,1,2,3",
430*959826caSMatt Macy        "UMask": "0x1",
431*959826caSMatt Macy        "EventName": "LSD.INACTIVE",
432*959826caSMatt Macy        "SampleAfterValue": "2000000",
433*959826caSMatt Macy        "BriefDescription": "Cycles no uops were delivered by the LSD",
434*959826caSMatt Macy        "CounterMask": "1"
435*959826caSMatt Macy    },
436*959826caSMatt Macy    {
437*959826caSMatt Macy        "EventCode": "0x20",
438*959826caSMatt Macy        "Counter": "0,1,2,3",
439*959826caSMatt Macy        "UMask": "0x1",
440*959826caSMatt Macy        "EventName": "LSD_OVERFLOW",
441*959826caSMatt Macy        "SampleAfterValue": "2000000",
442*959826caSMatt Macy        "BriefDescription": "Loops that can't stream from the instruction queue"
443*959826caSMatt Macy    },
444*959826caSMatt Macy    {
445*959826caSMatt Macy        "EventCode": "0xC3",
446*959826caSMatt Macy        "Counter": "0,1,2,3",
447*959826caSMatt Macy        "UMask": "0x1",
448*959826caSMatt Macy        "EventName": "MACHINE_CLEARS.CYCLES",
449*959826caSMatt Macy        "SampleAfterValue": "20000",
450*959826caSMatt Macy        "BriefDescription": "Cycles machine clear asserted"
451*959826caSMatt Macy    },
452*959826caSMatt Macy    {
453*959826caSMatt Macy        "EventCode": "0xC3",
454*959826caSMatt Macy        "Counter": "0,1,2,3",
455*959826caSMatt Macy        "UMask": "0x2",
456*959826caSMatt Macy        "EventName": "MACHINE_CLEARS.MEM_ORDER",
457*959826caSMatt Macy        "SampleAfterValue": "20000",
458*959826caSMatt Macy        "BriefDescription": "Execution pipeline restart due to Memory ordering conflicts"
459*959826caSMatt Macy    },
460*959826caSMatt Macy    {
461*959826caSMatt Macy        "EventCode": "0xC3",
462*959826caSMatt Macy        "Counter": "0,1,2,3",
463*959826caSMatt Macy        "UMask": "0x4",
464*959826caSMatt Macy        "EventName": "MACHINE_CLEARS.SMC",
465*959826caSMatt Macy        "SampleAfterValue": "20000",
466*959826caSMatt Macy        "BriefDescription": "Self-Modifying Code detected"
467*959826caSMatt Macy    },
468*959826caSMatt Macy    {
469*959826caSMatt Macy        "EventCode": "0xA2",
470*959826caSMatt Macy        "Counter": "0,1,2,3",
471*959826caSMatt Macy        "UMask": "0x1",
472*959826caSMatt Macy        "EventName": "RESOURCE_STALLS.ANY",
473*959826caSMatt Macy        "SampleAfterValue": "2000000",
474*959826caSMatt Macy        "BriefDescription": "Resource related stall cycles"
475*959826caSMatt Macy    },
476*959826caSMatt Macy    {
477*959826caSMatt Macy        "EventCode": "0xA2",
478*959826caSMatt Macy        "Counter": "0,1,2,3",
479*959826caSMatt Macy        "UMask": "0x20",
480*959826caSMatt Macy        "EventName": "RESOURCE_STALLS.FPCW",
481*959826caSMatt Macy        "SampleAfterValue": "2000000",
482*959826caSMatt Macy        "BriefDescription": "FPU control word write stall cycles"
483*959826caSMatt Macy    },
484*959826caSMatt Macy    {
485*959826caSMatt Macy        "EventCode": "0xA2",
486*959826caSMatt Macy        "Counter": "0,1,2,3",
487*959826caSMatt Macy        "UMask": "0x2",
488*959826caSMatt Macy        "EventName": "RESOURCE_STALLS.LOAD",
489*959826caSMatt Macy        "SampleAfterValue": "2000000",
490*959826caSMatt Macy        "BriefDescription": "Load buffer stall cycles"
491*959826caSMatt Macy    },
492*959826caSMatt Macy    {
493*959826caSMatt Macy        "EventCode": "0xA2",
494*959826caSMatt Macy        "Counter": "0,1,2,3",
495*959826caSMatt Macy        "UMask": "0x40",
496*959826caSMatt Macy        "EventName": "RESOURCE_STALLS.MXCSR",
497*959826caSMatt Macy        "SampleAfterValue": "2000000",
498*959826caSMatt Macy        "BriefDescription": "MXCSR rename stall cycles"
499*959826caSMatt Macy    },
500*959826caSMatt Macy    {
501*959826caSMatt Macy        "EventCode": "0xA2",
502*959826caSMatt Macy        "Counter": "0,1,2,3",
503*959826caSMatt Macy        "UMask": "0x80",
504*959826caSMatt Macy        "EventName": "RESOURCE_STALLS.OTHER",
505*959826caSMatt Macy        "SampleAfterValue": "2000000",
506*959826caSMatt Macy        "BriefDescription": "Other Resource related stall cycles"
507*959826caSMatt Macy    },
508*959826caSMatt Macy    {
509*959826caSMatt Macy        "EventCode": "0xA2",
510*959826caSMatt Macy        "Counter": "0,1,2,3",
511*959826caSMatt Macy        "UMask": "0x10",
512*959826caSMatt Macy        "EventName": "RESOURCE_STALLS.ROB_FULL",
513*959826caSMatt Macy        "SampleAfterValue": "2000000",
514*959826caSMatt Macy        "BriefDescription": "ROB full stall cycles"
515*959826caSMatt Macy    },
516*959826caSMatt Macy    {
517*959826caSMatt Macy        "EventCode": "0xA2",
518*959826caSMatt Macy        "Counter": "0,1,2,3",
519*959826caSMatt Macy        "UMask": "0x4",
520*959826caSMatt Macy        "EventName": "RESOURCE_STALLS.RS_FULL",
521*959826caSMatt Macy        "SampleAfterValue": "2000000",
522*959826caSMatt Macy        "BriefDescription": "Reservation Station full stall cycles"
523*959826caSMatt Macy    },
524*959826caSMatt Macy    {
525*959826caSMatt Macy        "EventCode": "0xA2",
526*959826caSMatt Macy        "Counter": "0,1,2,3",
527*959826caSMatt Macy        "UMask": "0x8",
528*959826caSMatt Macy        "EventName": "RESOURCE_STALLS.STORE",
529*959826caSMatt Macy        "SampleAfterValue": "2000000",
530*959826caSMatt Macy        "BriefDescription": "Store buffer stall cycles"
531*959826caSMatt Macy    },
532*959826caSMatt Macy    {
533*959826caSMatt Macy        "PEBS": "1",
534*959826caSMatt Macy        "EventCode": "0xC7",
535*959826caSMatt Macy        "Counter": "0,1,2,3",
536*959826caSMatt Macy        "UMask": "0x4",
537*959826caSMatt Macy        "EventName": "SSEX_UOPS_RETIRED.PACKED_DOUBLE",
538*959826caSMatt Macy        "SampleAfterValue": "200000",
539*959826caSMatt Macy        "BriefDescription": "SIMD Packed-Double Uops retired (Precise Event)"
540*959826caSMatt Macy    },
541*959826caSMatt Macy    {
542*959826caSMatt Macy        "PEBS": "1",
543*959826caSMatt Macy        "EventCode": "0xC7",
544*959826caSMatt Macy        "Counter": "0,1,2,3",
545*959826caSMatt Macy        "UMask": "0x1",
546*959826caSMatt Macy        "EventName": "SSEX_UOPS_RETIRED.PACKED_SINGLE",
547*959826caSMatt Macy        "SampleAfterValue": "200000",
548*959826caSMatt Macy        "BriefDescription": "SIMD Packed-Single Uops retired (Precise Event)"
549*959826caSMatt Macy    },
550*959826caSMatt Macy    {
551*959826caSMatt Macy        "PEBS": "1",
552*959826caSMatt Macy        "EventCode": "0xC7",
553*959826caSMatt Macy        "Counter": "0,1,2,3",
554*959826caSMatt Macy        "UMask": "0x8",
555*959826caSMatt Macy        "EventName": "SSEX_UOPS_RETIRED.SCALAR_DOUBLE",
556*959826caSMatt Macy        "SampleAfterValue": "200000",
557*959826caSMatt Macy        "BriefDescription": "SIMD Scalar-Double Uops retired (Precise Event)"
558*959826caSMatt Macy    },
559*959826caSMatt Macy    {
560*959826caSMatt Macy        "PEBS": "1",
561*959826caSMatt Macy        "EventCode": "0xC7",
562*959826caSMatt Macy        "Counter": "0,1,2,3",
563*959826caSMatt Macy        "UMask": "0x2",
564*959826caSMatt Macy        "EventName": "SSEX_UOPS_RETIRED.SCALAR_SINGLE",
565*959826caSMatt Macy        "SampleAfterValue": "200000",
566*959826caSMatt Macy        "BriefDescription": "SIMD Scalar-Single Uops retired (Precise Event)"
567*959826caSMatt Macy    },
568*959826caSMatt Macy    {
569*959826caSMatt Macy        "PEBS": "1",
570*959826caSMatt Macy        "EventCode": "0xC7",
571*959826caSMatt Macy        "Counter": "0,1,2,3",
572*959826caSMatt Macy        "UMask": "0x10",
573*959826caSMatt Macy        "EventName": "SSEX_UOPS_RETIRED.VECTOR_INTEGER",
574*959826caSMatt Macy        "SampleAfterValue": "200000",
575*959826caSMatt Macy        "BriefDescription": "SIMD Vector Integer Uops retired (Precise Event)"
576*959826caSMatt Macy    },
577*959826caSMatt Macy    {
578*959826caSMatt Macy        "EventCode": "0xDB",
579*959826caSMatt Macy        "Counter": "0,1,2,3",
580*959826caSMatt Macy        "UMask": "0x1",
581*959826caSMatt Macy        "EventName": "UOP_UNFUSION",
582*959826caSMatt Macy        "SampleAfterValue": "2000000",
583*959826caSMatt Macy        "BriefDescription": "Uop unfusions due to FP exceptions"
584*959826caSMatt Macy    },
585*959826caSMatt Macy    {
586*959826caSMatt Macy        "EventCode": "0xD1",
587*959826caSMatt Macy        "Counter": "0,1,2,3",
588*959826caSMatt Macy        "UMask": "0x4",
589*959826caSMatt Macy        "EventName": "UOPS_DECODED.ESP_FOLDING",
590*959826caSMatt Macy        "SampleAfterValue": "2000000",
591*959826caSMatt Macy        "BriefDescription": "Stack pointer instructions decoded"
592*959826caSMatt Macy    },
593*959826caSMatt Macy    {
594*959826caSMatt Macy        "EventCode": "0xD1",
595*959826caSMatt Macy        "Counter": "0,1,2,3",
596*959826caSMatt Macy        "UMask": "0x8",
597*959826caSMatt Macy        "EventName": "UOPS_DECODED.ESP_SYNC",
598*959826caSMatt Macy        "SampleAfterValue": "2000000",
599*959826caSMatt Macy        "BriefDescription": "Stack pointer sync operations"
600*959826caSMatt Macy    },
601*959826caSMatt Macy    {
602*959826caSMatt Macy        "EventCode": "0xD1",
603*959826caSMatt Macy        "Counter": "0,1,2,3",
604*959826caSMatt Macy        "UMask": "0x2",
605*959826caSMatt Macy        "EventName": "UOPS_DECODED.MS_CYCLES_ACTIVE",
606*959826caSMatt Macy        "SampleAfterValue": "2000000",
607*959826caSMatt Macy        "BriefDescription": "Uops decoded by Microcode Sequencer",
608*959826caSMatt Macy        "CounterMask": "1"
609*959826caSMatt Macy    },
610*959826caSMatt Macy    {
611*959826caSMatt Macy        "EventCode": "0xD1",
612*959826caSMatt Macy        "Invert": "1",
613*959826caSMatt Macy        "Counter": "0,1,2,3",
614*959826caSMatt Macy        "UMask": "0x1",
615*959826caSMatt Macy        "EventName": "UOPS_DECODED.STALL_CYCLES",
616*959826caSMatt Macy        "SampleAfterValue": "2000000",
617*959826caSMatt Macy        "BriefDescription": "Cycles no Uops are decoded",
618*959826caSMatt Macy        "CounterMask": "1"
619*959826caSMatt Macy    },
620*959826caSMatt Macy    {
621*959826caSMatt Macy        "EventCode": "0xB1",
622*959826caSMatt Macy        "Counter": "0,1,2,3",
623*959826caSMatt Macy        "UMask": "0x3f",
624*959826caSMatt Macy        "AnyThread": "1",
625*959826caSMatt Macy        "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES",
626*959826caSMatt Macy        "SampleAfterValue": "2000000",
627*959826caSMatt Macy        "BriefDescription": "Cycles Uops executed on any port (core count)",
628*959826caSMatt Macy        "CounterMask": "1"
629*959826caSMatt Macy    },
630*959826caSMatt Macy    {
631*959826caSMatt Macy        "EventCode": "0xB1",
632*959826caSMatt Macy        "Counter": "0,1,2,3",
633*959826caSMatt Macy        "UMask": "0x1f",
634*959826caSMatt Macy        "AnyThread": "1",
635*959826caSMatt Macy        "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5",
636*959826caSMatt Macy        "SampleAfterValue": "2000000",
637*959826caSMatt Macy        "BriefDescription": "Cycles Uops executed on ports 0-4 (core count)",
638*959826caSMatt Macy        "CounterMask": "1"
639*959826caSMatt Macy    },
640*959826caSMatt Macy    {
641*959826caSMatt Macy        "EventCode": "0xB1",
642*959826caSMatt Macy        "Invert": "1",
643*959826caSMatt Macy        "Counter": "0,1,2,3",
644*959826caSMatt Macy        "UMask": "0x3f",
645*959826caSMatt Macy        "AnyThread": "1",
646*959826caSMatt Macy        "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT",
647*959826caSMatt Macy        "SampleAfterValue": "2000000",
648*959826caSMatt Macy        "BriefDescription": "Uops executed on any port (core count)",
649*959826caSMatt Macy        "CounterMask": "1",
650*959826caSMatt Macy        "EdgeDetect": "1"
651*959826caSMatt Macy    },
652*959826caSMatt Macy    {
653*959826caSMatt Macy        "EventCode": "0xB1",
654*959826caSMatt Macy        "Invert": "1",
655*959826caSMatt Macy        "Counter": "0,1,2,3",
656*959826caSMatt Macy        "UMask": "0x1f",
657*959826caSMatt Macy        "AnyThread": "1",
658*959826caSMatt Macy        "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT_NO_PORT5",
659*959826caSMatt Macy        "SampleAfterValue": "2000000",
660*959826caSMatt Macy        "BriefDescription": "Uops executed on ports 0-4 (core count)",
661*959826caSMatt Macy        "CounterMask": "1",
662*959826caSMatt Macy        "EdgeDetect": "1"
663*959826caSMatt Macy    },
664*959826caSMatt Macy    {
665*959826caSMatt Macy        "EventCode": "0xB1",
666*959826caSMatt Macy        "Invert": "1",
667*959826caSMatt Macy        "Counter": "0,1,2,3",
668*959826caSMatt Macy        "UMask": "0x3f",
669*959826caSMatt Macy        "AnyThread": "1",
670*959826caSMatt Macy        "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES",
671*959826caSMatt Macy        "SampleAfterValue": "2000000",
672*959826caSMatt Macy        "BriefDescription": "Cycles no Uops issued on any port (core count)",
673*959826caSMatt Macy        "CounterMask": "1"
674*959826caSMatt Macy    },
675*959826caSMatt Macy    {
676*959826caSMatt Macy        "EventCode": "0xB1",
677*959826caSMatt Macy        "Invert": "1",
678*959826caSMatt Macy        "Counter": "0,1,2,3",
679*959826caSMatt Macy        "UMask": "0x1f",
680*959826caSMatt Macy        "AnyThread": "1",
681*959826caSMatt Macy        "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5",
682*959826caSMatt Macy        "SampleAfterValue": "2000000",
683*959826caSMatt Macy        "BriefDescription": "Cycles no Uops issued on ports 0-4 (core count)",
684*959826caSMatt Macy        "CounterMask": "1"
685*959826caSMatt Macy    },
686*959826caSMatt Macy    {
687*959826caSMatt Macy        "EventCode": "0xB1",
688*959826caSMatt Macy        "Counter": "0,1,2,3",
689*959826caSMatt Macy        "UMask": "0x1",
690*959826caSMatt Macy        "EventName": "UOPS_EXECUTED.PORT0",
691*959826caSMatt Macy        "SampleAfterValue": "2000000",
692*959826caSMatt Macy        "BriefDescription": "Uops executed on port 0"
693*959826caSMatt Macy    },
694*959826caSMatt Macy    {
695*959826caSMatt Macy        "EventCode": "0xB1",
696*959826caSMatt Macy        "Counter": "0,1,2,3",
697*959826caSMatt Macy        "UMask": "0x40",
698*959826caSMatt Macy        "EventName": "UOPS_EXECUTED.PORT015",
699*959826caSMatt Macy        "SampleAfterValue": "2000000",
700*959826caSMatt Macy        "BriefDescription": "Uops issued on ports 0, 1 or 5"
701*959826caSMatt Macy    },
702*959826caSMatt Macy    {
703*959826caSMatt Macy        "EventCode": "0xB1",
704*959826caSMatt Macy        "Invert": "1",
705*959826caSMatt Macy        "Counter": "0,1,2,3",
706*959826caSMatt Macy        "UMask": "0x40",
707*959826caSMatt Macy        "EventName": "UOPS_EXECUTED.PORT015_STALL_CYCLES",
708*959826caSMatt Macy        "SampleAfterValue": "2000000",
709*959826caSMatt Macy        "BriefDescription": "Cycles no Uops issued on ports 0, 1 or 5",
710*959826caSMatt Macy        "CounterMask": "1"
711*959826caSMatt Macy    },
712*959826caSMatt Macy    {
713*959826caSMatt Macy        "EventCode": "0xB1",
714*959826caSMatt Macy        "Counter": "0,1,2,3",
715*959826caSMatt Macy        "UMask": "0x2",
716*959826caSMatt Macy        "EventName": "UOPS_EXECUTED.PORT1",
717*959826caSMatt Macy        "SampleAfterValue": "2000000",
718*959826caSMatt Macy        "BriefDescription": "Uops executed on port 1"
719*959826caSMatt Macy    },
720*959826caSMatt Macy    {
721*959826caSMatt Macy        "EventCode": "0xB1",
722*959826caSMatt Macy        "Counter": "0,1,2,3",
723*959826caSMatt Macy        "UMask": "0x4",
724*959826caSMatt Macy        "AnyThread": "1",
725*959826caSMatt Macy        "EventName": "UOPS_EXECUTED.PORT2_CORE",
726*959826caSMatt Macy        "SampleAfterValue": "2000000",
727*959826caSMatt Macy        "BriefDescription": "Uops executed on port 2 (core count)"
728*959826caSMatt Macy    },
729*959826caSMatt Macy    {
730*959826caSMatt Macy        "EventCode": "0xB1",
731*959826caSMatt Macy        "Counter": "0,1,2,3",
732*959826caSMatt Macy        "UMask": "0x80",
733*959826caSMatt Macy        "AnyThread": "1",
734*959826caSMatt Macy        "EventName": "UOPS_EXECUTED.PORT234_CORE",
735*959826caSMatt Macy        "SampleAfterValue": "2000000",
736*959826caSMatt Macy        "BriefDescription": "Uops issued on ports 2, 3 or 4"
737*959826caSMatt Macy    },
738*959826caSMatt Macy    {
739*959826caSMatt Macy        "EventCode": "0xB1",
740*959826caSMatt Macy        "Counter": "0,1,2,3",
741*959826caSMatt Macy        "UMask": "0x8",
742*959826caSMatt Macy        "AnyThread": "1",
743*959826caSMatt Macy        "EventName": "UOPS_EXECUTED.PORT3_CORE",
744*959826caSMatt Macy        "SampleAfterValue": "2000000",
745*959826caSMatt Macy        "BriefDescription": "Uops executed on port 3 (core count)"
746*959826caSMatt Macy    },
747*959826caSMatt Macy    {
748*959826caSMatt Macy        "EventCode": "0xB1",
749*959826caSMatt Macy        "Counter": "0,1,2,3",
750*959826caSMatt Macy        "UMask": "0x10",
751*959826caSMatt Macy        "AnyThread": "1",
752*959826caSMatt Macy        "EventName": "UOPS_EXECUTED.PORT4_CORE",
753*959826caSMatt Macy        "SampleAfterValue": "2000000",
754*959826caSMatt Macy        "BriefDescription": "Uops executed on port 4 (core count)"
755*959826caSMatt Macy    },
756*959826caSMatt Macy    {
757*959826caSMatt Macy        "EventCode": "0xB1",
758*959826caSMatt Macy        "Counter": "0,1,2,3",
759*959826caSMatt Macy        "UMask": "0x20",
760*959826caSMatt Macy        "EventName": "UOPS_EXECUTED.PORT5",
761*959826caSMatt Macy        "SampleAfterValue": "2000000",
762*959826caSMatt Macy        "BriefDescription": "Uops executed on port 5"
763*959826caSMatt Macy    },
764*959826caSMatt Macy    {
765*959826caSMatt Macy        "EventCode": "0xE",
766*959826caSMatt Macy        "Counter": "0,1,2,3",
767*959826caSMatt Macy        "UMask": "0x1",
768*959826caSMatt Macy        "EventName": "UOPS_ISSUED.ANY",
769*959826caSMatt Macy        "SampleAfterValue": "2000000",
770*959826caSMatt Macy        "BriefDescription": "Uops issued"
771*959826caSMatt Macy    },
772*959826caSMatt Macy    {
773*959826caSMatt Macy        "EventCode": "0xE",
774*959826caSMatt Macy        "Invert": "1",
775*959826caSMatt Macy        "Counter": "0,1,2,3",
776*959826caSMatt Macy        "UMask": "0x1",
777*959826caSMatt Macy        "AnyThread": "1",
778*959826caSMatt Macy        "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES",
779*959826caSMatt Macy        "SampleAfterValue": "2000000",
780*959826caSMatt Macy        "BriefDescription": "Cycles no Uops were issued on any thread",
781*959826caSMatt Macy        "CounterMask": "1"
782*959826caSMatt Macy    },
783*959826caSMatt Macy    {
784*959826caSMatt Macy        "EventCode": "0xE",
785*959826caSMatt Macy        "Counter": "0,1,2,3",
786*959826caSMatt Macy        "UMask": "0x1",
787*959826caSMatt Macy        "AnyThread": "1",
788*959826caSMatt Macy        "EventName": "UOPS_ISSUED.CYCLES_ALL_THREADS",
789*959826caSMatt Macy        "SampleAfterValue": "2000000",
790*959826caSMatt Macy        "BriefDescription": "Cycles Uops were issued on either thread",
791*959826caSMatt Macy        "CounterMask": "1"
792*959826caSMatt Macy    },
793*959826caSMatt Macy    {
794*959826caSMatt Macy        "EventCode": "0xE",
795*959826caSMatt Macy        "Counter": "0,1,2,3",
796*959826caSMatt Macy        "UMask": "0x2",
797*959826caSMatt Macy        "EventName": "UOPS_ISSUED.FUSED",
798*959826caSMatt Macy        "SampleAfterValue": "2000000",
799*959826caSMatt Macy        "BriefDescription": "Fused Uops issued"
800*959826caSMatt Macy    },
801*959826caSMatt Macy    {
802*959826caSMatt Macy        "EventCode": "0xE",
803*959826caSMatt Macy        "Invert": "1",
804*959826caSMatt Macy        "Counter": "0,1,2,3",
805*959826caSMatt Macy        "UMask": "0x1",
806*959826caSMatt Macy        "EventName": "UOPS_ISSUED.STALL_CYCLES",
807*959826caSMatt Macy        "SampleAfterValue": "2000000",
808*959826caSMatt Macy        "BriefDescription": "Cycles no Uops were issued",
809*959826caSMatt Macy        "CounterMask": "1"
810*959826caSMatt Macy    },
811*959826caSMatt Macy    {
812*959826caSMatt Macy        "PEBS": "1",
813*959826caSMatt Macy        "EventCode": "0xC2",
814*959826caSMatt Macy        "Counter": "0,1,2,3",
815*959826caSMatt Macy        "UMask": "0x1",
816*959826caSMatt Macy        "EventName": "UOPS_RETIRED.ACTIVE_CYCLES",
817*959826caSMatt Macy        "SampleAfterValue": "2000000",
818*959826caSMatt Macy        "BriefDescription": "Cycles Uops are being retired",
819*959826caSMatt Macy        "CounterMask": "1"
820*959826caSMatt Macy    },
821*959826caSMatt Macy    {
822*959826caSMatt Macy        "PEBS": "1",
823*959826caSMatt Macy        "EventCode": "0xC2",
824*959826caSMatt Macy        "Counter": "0,1,2,3",
825*959826caSMatt Macy        "UMask": "0x1",
826*959826caSMatt Macy        "EventName": "UOPS_RETIRED.ANY",
827*959826caSMatt Macy        "SampleAfterValue": "2000000",
828*959826caSMatt Macy        "BriefDescription": "Uops retired (Precise Event)"
829*959826caSMatt Macy    },
830*959826caSMatt Macy    {
831*959826caSMatt Macy        "PEBS": "1",
832*959826caSMatt Macy        "EventCode": "0xC2",
833*959826caSMatt Macy        "Counter": "0,1,2,3",
834*959826caSMatt Macy        "UMask": "0x4",
835*959826caSMatt Macy        "EventName": "UOPS_RETIRED.MACRO_FUSED",
836*959826caSMatt Macy        "SampleAfterValue": "2000000",
837*959826caSMatt Macy        "BriefDescription": "Macro-fused Uops retired (Precise Event)"
838*959826caSMatt Macy    },
839*959826caSMatt Macy    {
840*959826caSMatt Macy        "PEBS": "1",
841*959826caSMatt Macy        "EventCode": "0xC2",
842*959826caSMatt Macy        "Counter": "0,1,2,3",
843*959826caSMatt Macy        "UMask": "0x2",
844*959826caSMatt Macy        "EventName": "UOPS_RETIRED.RETIRE_SLOTS",
845*959826caSMatt Macy        "SampleAfterValue": "2000000",
846*959826caSMatt Macy        "BriefDescription": "Retirement slots used (Precise Event)"
847*959826caSMatt Macy    },
848*959826caSMatt Macy    {
849*959826caSMatt Macy        "PEBS": "1",
850*959826caSMatt Macy        "EventCode": "0xC2",
851*959826caSMatt Macy        "Invert": "1",
852*959826caSMatt Macy        "Counter": "0,1,2,3",
853*959826caSMatt Macy        "UMask": "0x1",
854*959826caSMatt Macy        "EventName": "UOPS_RETIRED.STALL_CYCLES",
855*959826caSMatt Macy        "SampleAfterValue": "2000000",
856*959826caSMatt Macy        "BriefDescription": "Cycles Uops are not retiring (Precise Event)",
857*959826caSMatt Macy        "CounterMask": "1"
858*959826caSMatt Macy    },
859*959826caSMatt Macy    {
860*959826caSMatt Macy        "PEBS": "1",
861*959826caSMatt Macy        "EventCode": "0xC2",
862*959826caSMatt Macy        "Invert": "1",
863*959826caSMatt Macy        "Counter": "0,1,2,3",
864*959826caSMatt Macy        "UMask": "0x1",
865*959826caSMatt Macy        "EventName": "UOPS_RETIRED.TOTAL_CYCLES",
866*959826caSMatt Macy        "SampleAfterValue": "2000000",
867*959826caSMatt Macy        "BriefDescription": "Total cycles using precise uop retired event (Precise Event)",
868*959826caSMatt Macy        "CounterMask": "16"
869*959826caSMatt Macy    },
870*959826caSMatt Macy    {
871*959826caSMatt Macy        "PEBS": "2",
872*959826caSMatt Macy        "EventCode": "0xC0",
873*959826caSMatt Macy        "Invert": "1",
874*959826caSMatt Macy        "Counter": "0,1,2,3",
875*959826caSMatt Macy        "UMask": "0x1",
876*959826caSMatt Macy        "EventName": "INST_RETIRED.TOTAL_CYCLES_PS",
877*959826caSMatt Macy        "SampleAfterValue": "2000000",
878*959826caSMatt Macy        "BriefDescription": "Total cycles (Precise Event)",
879*959826caSMatt Macy        "CounterMask": "16"
880*959826caSMatt Macy    }
881*959826caSMatt Macy]