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/linux/Documentation/admin-guide/mm/
H A Dnuma_memory_policy.rst10 supported platforms with Non-Uniform Memory Access architectures since 2.4.?.
16 (``Documentation/admin-guide/cgroup-v1/cpusets.rst``)
19 programming interface that a NUMA-aware application can take advantage of. When
28 ------------------------
39 up, the system default policy will be set to interleave
41 not to overload the initial boot node with boot-time
45 this is an optional, per-task policy. When defined for a
61 In a multi-threaded task, task policies apply only to the thread
98 mapping-- i.e., at Copy-On-Write.
101 virtual address space--a.k.a. threads--independent of when
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/linux/drivers/mtd/chips/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
13 support any device that is CFI-compliant, you need to enable this
18 tristate "Detect non-CFI AMD/JEDEC-compatible flash chips"
22 This option enables JEDEC-style probing of flash chips which are not
24 CFI-targeted flash drivers for any chips which are identified which
26 covers most AMD/Fujitsu-compatible chips and also non-CFI
53 are expected to be wired to the CPU in 'host-endian' form.
85 bool "Support 8-bit buswidth" if MTD_CFI_GEOMETRY
92 bool "Support 16-bit buswidth" if MTD_CFI_GEOMETRY
99 bool "Support 32-bit buswidth" if MTD_CFI_GEOMETRY
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H A Dcfi_util.c1 // SPDX-License-Identifier: GPL-2.0
43 unsigned interleave = cfi_interleave(cfi); in cfi_build_cmd_addr() local
44 unsigned type = cfi->device_type; in cfi_build_cmd_addr()
47 addr = (cmd_ofs * type) * interleave; in cfi_build_cmd_addr()
54 if (((type * interleave) > bankwidth) && ((cmd_ofs & 0xff) == 0xaa)) in cfi_build_cmd_addr()
55 addr |= (type >> 1)*interleave; in cfi_build_cmd_addr()
62 * Transforms the CFI command for the given geometry (bus width & interleave).
88 /* First, determine what the bit-pattern should be for a single in cfi_build_cmd()
122 /* And finally, for the multi-word case, replicate it in cfi_build_cmd()
178 /* Last, determine what the bit-pattern should be for a single in cfi_merge_status()
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H A Dcfi_cmdset_0020.c1 // SPDX-License-Identifier: GPL-2.0
9 * - completely revamped method functions so they are aware and
10 * independent of the flash geometry (buswidth, interleave, etc.)
11 * - scalability vs code size is completely set at compile-time
13 * - optimized write buffer method
14 * 06/21/2002 Joern Engel <joern@wh.fh-wedel.de> and others
15 * - modified Intel Command Set 0x0001 to support ST Advanced Architecture
17 * - added a writev function
18 * 07/13/2005 Joern Engel <joern@wh.fh-wedel.de>
19 * - Plugged memory leak in cfi_staa_writev().
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H A Dcfi_cmdset_0001.c1 // SPDX-License-Identifier: GPL-2.0
10 * - completely revamped method functions so they are aware and
11 * independent of the flash geometry (buswidth, interleave, etc.)
12 * - scalability vs code size is completely set at compile-time
14 * - optimized write buffer method
16 * - reworked lock/unlock/erase support for var size flash
18 * - auto unlock sectors on resume for auto locking flash on power up
124 printk(" Extended Query version %c.%c\n", extp->MajorVersion, extp->MinorVersion); in cfi_tell_features()
125 printk(" Feature/Command Support: %4.4X\n", extp->FeatureSupport); in cfi_tell_features()
126 printk(" - Chip Erase: %s\n", extp->FeatureSupport&1?"supported":"unsupported"); in cfi_tell_features()
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/linux/drivers/ras/amd/atl/
H A Dreg_fields.h1 /* SPDX-License-Identifier: GPL-2.0 */
216 * Hash Interleave Controls
299 * Interleave Address Select
311 * D18F7xE0C [DRAM Address Interleave]
314 * D18F7x20C [DRAM Address Interleave]
322 * Interleave Number of Channels
334 * D18F7xE0C [DRAM Address Interleave]
337 * D18F7x20C [DRAM Address Interleave]
347 * Interleave Number of Dies
361 * D18F7xE0C [DRAM Address Interleave]
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H A Ddenormalize.c1 // SPDX-License-Identifier: GPL-2.0-or-later
22 case DF2: return FIELD_GET(DF2_DST_FABRIC_ID, ctx->map.limit); in get_dst_fabric_id()
23 case DF3: return FIELD_GET(DF3_DST_FABRIC_ID, ctx->map.limit); in get_dst_fabric_id()
24 case DF3p5: return FIELD_GET(DF3p5_DST_FABRIC_ID, ctx->map.limit); in get_dst_fabric_id()
25 case DF4: return FIELD_GET(DF4_DST_FABRIC_ID, ctx->map.ctl); in get_dst_fabric_id()
26 case DF4p5: return FIELD_GET(DF4p5_DST_FABRIC_ID, ctx->map.ctl); in get_dst_fabric_id()
38 * # of interleave bits (n): 3
39 * starting interleave bit (p): 8
41 * expanded address bits: [20+n : n+p][n+p-1 : p][p-1 : 0]
46 return expand_bits(ctx->map.intlv_bit_pos, in make_space_for_coh_st_id_at_intlv_bit()
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/linux/Documentation/driver-api/cxl/
H A Dmemory-devices.rst1 .. SPDX-License-Identifier: GPL-2.0
14 range across multiple devices underneath a host-bridge or interleaved
15 across host-bridges.
28 Platform firmware enumerates a menu of interleave options at the "CXL root port"
32 at which the interleave can be split. For example platform firmware may say at a
34 interleave cycles across multiple Root Ports. An intervening Switch between a
35 port and an endpoint may interleave cycles across multiple Downstream Switch
40 Ports. Each of those Root Ports are connected to 2-way switches with endpoints
43 # cxl list -BEMPu -b cxl_test
185 its descendants. So "root" claims non-PCIe enumerable platform decode ranges and
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/linux/Documentation/ABI/testing/
H A Dsysfs-bus-cxl4 Contact: linux-cxl@vger.kernel.org
14 Contact: linux-cxl@vger.kernel.org
17 Memory Device Output Payload in the CXL-2.0
24 Contact: linux-cxl@vger.kernel.org
34 Contact: linux-cxl@vger.kernel.org
42 Contact: linux-cxl@vger.kernel.org
46 Payload in the CXL-2.0 specification.
52 Contact: linux-cxl@vger.kernel.org
58 class-ids can be compared against a similar "qos_class"
60 that the endpoints map their local memory-class to a
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/linux/drivers/edac/
H A Di5100_edac.c9 * Intel 5100X Chipset Memory Controller Hub (MCH) - Datasheet
13 * can not reflect this configuration so instead the chip-select
44 #define I5100_MIR0 0x80 /* Memory Interleave Range 0 */
45 #define I5100_MIR1 0x84 /* Memory Interleave Range 1 */
46 #define I5100_AMIR_0 0x8c /* Adjusted Memory Interleave Range 0 */
47 #define I5100_AMIR_1 0x90 /* Adjusted Memory Interleave Range 1 */
48 #define I5100_FERR_NF_MEM 0xa0 /* MC First Non Fatal Errors */
70 #define I5100_NERR_NF_MEM 0xa4 /* MC Next Non-Fatal Errors */
82 #define I5100_MTR_0 0x154 /* Memory Technology Registers 0-3 */
83 #define I5100_DMIR 0x15c /* DIMM Interleave Range */
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H A Dsb_edac.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Intel Sandy Bridge -EN/-EP/-EX Memory Controller kernel module
24 #include <asm/intel-family.h>
70 0x60, 0x68, 0x70, 0x78, 0x80, /* 0-4 */
71 0x88, 0x90, 0x98, 0xa0, 0xa8, /* 5-9 */
72 0xb0, 0xb8, 0xc0, 0xc8, 0xd0, /* 10-14 */
73 0xd8, 0xe0, 0xe8, 0xf0, 0xf8, /* 15-19 */
74 0x100, 0x108, 0x110, 0x118, /* 20-23 */
107 0x64, 0x6c, 0x74, 0x7c, 0x84, /* 0-4 */
108 0x8c, 0x94, 0x9c, 0xa4, 0xac, /* 5-9 */
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/linux/tools/perf/scripts/python/
H A Dintel-pt-events.py1 # SPDX-License-Identifier: GPL-2.0
2 # intel-pt-events.py: Print Intel PT Events including Power Events and PTWRITE
3 # Copyright (c) 2017-2021, Intel Corporation.
27 '/scripts/python/Perf-Trace-Util/lib/Perf/Trace')
47 glb_cpu = -1
77 ap.add_argument("--insn-trace", action='store_true')
78 ap.add_argument("--src-trace", action='store_true')
79 ap.add_argument("--all-switch-events", action='store_true')
80 ap.add_argument("--interleave", type=int, nargs='?', const=4, default=0)
105 if glb_args.interleave:
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/linux/drivers/scsi/esas2r/
H A Desas2r_targdb.c5 * Copyright (c) 2001-2013 ATTO Technology, Inc.
21 * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
40 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
50 for (t = a->targetdb; t < a->targetdb_end; t++) { in esas2r_targ_db_initialize()
53 t->target_state = TS_NOT_PRESENT; in esas2r_targ_db_initialize()
54 t->buffered_target_state = TS_NOT_PRESENT; in esas2r_targ_db_initialize()
55 t->new_target_state = TS_INVALID; in esas2r_targ_db_initialize()
64 for (t = a->targetdb; t < a->targetdb_end; t++) { in esas2r_targ_db_remove_all()
65 if (t->target_state != TS_PRESENT) in esas2r_targ_db_remove_all()
68 spin_lock_irqsave(&a->mem_lock, flags); in esas2r_targ_db_remove_all()
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H A Desas2r_disc.c5 * Copyright (c) 2001-2013 ATTO Technology, Inc.
8 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
22 * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
41 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
43 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
85 struct esas2r_sas_nvram *nvr = a->nvram; in esas2r_disc_initialize()
89 clear_bit(AF_DISC_IN_PROG, &a->flags); in esas2r_disc_initialize()
90 clear_bit(AF2_DEV_SCAN, &a->flags2); in esas2r_disc_initialize()
91 clear_bit(AF2_DEV_CNT_OK, &a->flags2); in esas2r_disc_initialize()
93 a->disc_start_time = jiffies_to_msecs(jiffies); in esas2r_disc_initialize()
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/linux/sound/pci/echoaudio/
H A Dechoaudio_dsp.h3 Copyright Echo Digital Audio Corporation (c) 1998 - 2004
21 Foundation, Inc., 59 Temple Place - Suite 330, Boston,
22 MA 02111-1307, USA.
26 Translation from C++ and adaptation for use in ALSA-Driver
41 /**** Echo24: Gina24, Layla24, Mona, Mia, Mia-midi ****/
81 * These are the offsets for the memory-mapped DSP registers; the DSP base
133 #define MIDI_IN_SKIP_DATA (-1)
136 /*----------------------------------------------------------------------------
151 -Set the clock select bits in the control register to 0xe (see the #define
154 -Set double-speed mode if you want to use sample rates above 50 kHz
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H A Dechoaudio_dsp.c3 Copyright Echo Digital Audio Corporation (c) 1998 - 2004
21 Foundation, Inc., 59 Temple Place - Suite 330, Boston,
22 MA 02111-1307, USA.
26 Translation from C++ and adaptation for use in ALSA-Driver
40 command and then write a non-zero value to the Handshake field in the
50 if (chip->comm_page->handshake) { in wait_handshake()
56 dev_err(chip->card->dev, "wait_handshake(): Timeout waiting for DSP\n"); in wait_handshake()
57 return -EBUSY; in wait_handshake()
83 dev_err(chip->card->dev, "timeout on send_vector\n"); in send_vector()
84 return -EBUSY; in send_vector()
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/linux/Documentation/fb/
H A Dapi.rst9 ---------------
12 with frame buffer devices. In-kernel APIs between device drivers and the frame
22 ---------------
36 - FB_CAP_FOURCC
44 --------------------
46 Pixels are stored in memory in hardware-dependent formats. Applications need
58 - FB_TYPE_PACKED_PIXELS
67 - FB_TYPE_PLANES
75 - FB_TYPE_INTERLEAVED_PLANES
81 Planes are interleaved in memory. The interleave factor, defined as the
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/linux/Documentation/devicetree/bindings/sound/
H A Dfsl,qmc-audio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/fsl,qmc-audio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Herve Codina <herve.codina@bootlin.com>
16 if only one QMC channel is used by the DAI or it is working in non-interleaved
20 - $ref: dai-common.yaml#
24 const: fsl,qmc-audio
26 '#address-cells':
28 '#size-cells':
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/linux/include/linux/
H A Dlibnvdimm.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * libnvdimm - Non-volatile-memory Devices Subsystem
5 * Copyright(c) 2013-2015 Intel Corporation. All rights reserved.
53 /* region flag indicating to direct-map persistent memory by default */
107 /* v1.1 definition of the interleave-set-cookie algorithm */
109 /* v1.2 definition of the interleave-set-cookie algorithm */
154 * 'flags == 0' corresponds to an error / not-supported state.
309 return nd_desc->ndctl(nd_desc, nvdimm, cmd, buf, buf_len, cmd_rc); in nvdimm_ctl()
/linux/drivers/acpi/nfit/
H A Dnfit.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * NVDIMM Firmware Interface Table - NFIT
5 * Copyright(c) 2013-2015 Intel Corporation. All rights reserved.
17 #define UUID_NFIT_BUS "2f10e7a4-9e91-11e4-89d3-123b93f75cba"
19 /* https://pmem.io/documents/NVDIMM_DSM_Interface-V1.6.pdf */
20 #define UUID_NFIT_DIMM "4309ac30-0d11-11e4-9191-0800200c9a66"
21 #define UUID_INTEL_BUS "c7d8acd4-2df8-4b82-9f65-a325335af149"
23 /* https://github.com/HewlettPackard/hpe-nvm/blob/master/Documentation/ */
24 #define UUID_NFIT_DIMM_N_HPE1 "9002c334-acf3-4c0e-9642-a235f0d53bc6"
25 #define UUID_NFIT_DIMM_N_HPE2 "5008664b-b758-41a0-a03c-27c2f2d04f7e"
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/linux/Documentation/admin-guide/device-mapper/
H A Ddm-integrity.rst2 dm-integrity
5 The dm-integrity target emulates a block device that has additional
6 per-sector tags that can be used for storing integrity information.
9 writing the sector and the integrity tag must be atomic - i.e. in case of
12 To guarantee write atomicity, the dm-integrity target uses journal, it
16 The dm-integrity target can be used with the dm-crypt target - in this
17 situation the dm-crypt target creates the integrity data and passes them
18 to the dm-integrity target via bio_integrity_payload attached to the bio.
19 In this mode, the dm-crypt and dm-integrity targets provide authenticated
20 disk encryption - if the attacker modifies the encrypted device, an I/O
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/linux/tools/perf/Documentation/
H A Dperf-annotate.txt1 perf-annotate(1)
5 ----
6 perf-annotate - Read perf.data (created by perf record) and display annotated code
9 ---
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/linux/Documentation/i2c/
H A Di2c-topology.rst6 than a straight-forward I2C bus with one adapter and one or more devices.
25 I2C transfers, and all adapters with a parent are part of an "i2c-mux"
40 mux-locked or parent-locked muxes.
43 Mux-locked muxes
44 ----------------
46 Mux-locked muxes does not lock the entire parent adapter during the
47 full select-transfer-deselect transaction, only the muxes on the parent
48 adapter are locked. Mux-locked muxes are mostly interesting if the
51 full transaction, unrelated I2C transfers may interleave the different
55 Mux-locked Example
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/linux/drivers/mtd/maps/
H A Dpcmciamtd.c2 * pcmciamtd.c - MTD driver for PCMCIA flash memory cards
45 /* 2 = do 16-bit transfers, 1 = do 8-bit transfers */
71 MODULE_PARM_DESC(force_size, "Force size of card in MiB (1-64)");
85 struct pcmciamtd_dev *dev = (struct pcmciamtd_dev *)map->map_priv_1; in remap_window()
86 struct resource *win = (struct resource *) map->map_priv_2; in remap_window()
90 if (!pcmcia_dev_present(dev->p_dev)) { in remap_window()
95 offset = to & ~(dev->win_size-1); in remap_window()
96 if (offset != dev->offset) { in remap_window()
98 dev->offset, offset); in remap_window()
99 ret = pcmcia_map_mem_page(dev->p_dev, win, offset); in remap_window()
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/linux/include/uapi/linux/
H A Dfb.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
24 /* 0x4607-0x460B are defined below */
41 #define FB_TYPE_PLANES 1 /* Non interleaved planes */
52 #define FB_AUX_TEXT_SVGA_GROUP 8 /* 8-15: SVGA tileblit compatible modes */
140 #define FB_ACCEL_SAVAGE3D_MV 0x82 /* S3 Savage3D-MV */
142 #define FB_ACCEL_SAVAGE_MX_MV 0x84 /* S3 Savage/MX-MV */
144 #define FB_ACCEL_SAVAGE_IX_MV 0x86 /* S3 Savage/IX-MV */
152 #define FB_ACCEL_PROSAVAGE_DDRK 0x8e /* S3 ProSavage DDR-K */
154 #define FB_ACCEL_PUV3_UNIGFX 0xa0 /* PKUnity-v3 Unigfx */
156 #define FB_CAP_FOURCC 1 /* Device supports FOURCC-based formats */
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