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/linux/Documentation/accel/qaic/
H A Daic100.rst1 .. SPDX-License-Identifier: GPL-2.0-only
10 The Qualcomm Cloud AI 100/AIC100 family of products (including SA9000P - part of
16 (x8). An individual SoC on a card can have up to 16 NSPs for running workloads.
20 performance. AIC100 cards are multi-user capable and able to execute workloads
26 An AIC100 card consists of an AIC100 SoC, on-card DDR, and a set of misc
39 AIC100 implements MSI but does not implement MSI-X. AIC100 prefers 17 MSIs to
44 hardware. AIC100 provides 3, 64-bit BARs.
52 configuration, but defaults to 64K. This BAR currently has no purpose.
54 From the host perspective, AIC100 has several key hardware components -
63 ---
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/linux/Documentation/devicetree/bindings/net/
H A Dsnps,dwmac.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandre Torgue <alexandre.torgue@foss.st.com>
11 - Giuseppe Cavallaro <peppe.cavallaro@st.com>
12 - Jose Abreu <joabreu@synopsys.com>
23 - snps,dwmac
24 - snps,dwmac-3.40a
25 - snps,dwmac-3.50a
26 - snps,dwmac-3.610
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H A Dstarfive,jh7110-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/starfive,jh7110-dwmac.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Emil Renner Berthing <kernel@esmil.dk>
12 - Samin Guo <samin.guo@starfivetech.com>
19 - starfive,jh7100-dwmac
20 - starfive,jh7110-dwmac
22 - compatible
27 - items:
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/linux/lib/
H A Dtest_printf.c1 // SPDX-License-Identifier: GPL-2.0-only
79 written = min(bufsize-1, elen); in do_test()
81 pr_warn("vsnprintf(buf, %d, \"%s\", ...) did not nul-terminate buffer\n", in do_test()
86 if (memchr_inv(test_buffer + written + 1, FILL_CHAR, bufsize - (written + 1))) { in do_test()
87 pr_warn("vsnprintf(buf, %d, \"%s\", ...) wrote beyond the nul-terminator\n", in do_test()
92 if (memchr_inv(test_buffer + bufsize, FILL_CHAR, BUF_SIZE + PAD_SIZE - bufsize)) { in do_test()
152 /* Work around annoying "warning: zero-lengt in test_basic()
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/linux/drivers/net/ethernet/stmicro/stmmac/
H A Dstmmac_platform.c1 // SPDX-License-Identifier: GPL-2.0-only
5 Copyright (C) 2007-2011 STMicroelectronics Ltd
26 * dwmac1000_validate_mcast_bins - validates the number of Multicast filter bins
57 * dwmac1000_validate_ucast_entries - validate the Unicast address entries
88 * stmmac_axi_setup - parse DT parameters for programming the AXI register
91 * if required, from device-tree the AXI internal register can be tuned
99 np = of_parse_phandle(pdev->dev.of_node, "snps,axi-config", 0); in stmmac_axi_setup()
103 axi = devm_kzalloc(&pdev->dev, sizeof(*axi), GFP_KERNEL); in stmmac_axi_setup()
106 return ERR_PTR(-ENOMEM); in stmmac_axi_setup()
109 axi->axi_lpi_en = of_property_read_bool(np, "snps,lpi_en"); in stmmac_axi_setup()
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/linux/drivers/net/ethernet/tehuti/
H A Dtehuti.c1 // SPDX-License-Identifier: GPL-2.0-or-later
12 * 1) RX Free Fifo - RXF - holds descriptors of empty buffers to accept incoming
16 * 2) RX Data Fifo - RXD - holds descriptors of full buffers. This Fifo is
23 * One holds 1.5K packets and another - 26K packets. Depending on incoming
30 * skb db - used to keep track of all skbs owned by SW and their dma addresses.
34 * fifo - keeps info about fifo's size and location, relevant HW registers,
42 * NIC sees that there is no RXF buffers and raises
45 * NAPI - interrupt-driven mixed with polling
46 * interrupt-driven only
48 * Interrupt-driven only flow is following. When buffer is ready, HW raises
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H A Dtn40.c1 // SPDX-License-Identifier: GPL-2.0+
23 tn40_write_reg(priv, TN40_REG_IMR, priv->isr_mask); in tn40_enable_interrupts()
43 f->va = dma_alloc_coherent(&priv->pdev->dev, in tn40_fifo_alloc()
44 memsz + TN40_FIFO_EXTRA_SPACE, &f->da, in tn40_fifo_alloc()
46 if (!f->va) in tn40_fifo_alloc()
47 return -ENOMEM; in tn40_fifo_alloc()
49 f->reg_cfg0 = reg_cfg0; in tn40_fifo_alloc()
50 f->reg_cfg1 = reg_cfg1; in tn40_fifo_alloc()
51 f->reg_rptr = reg_rptr; in tn40_fifo_alloc()
52 f->reg_wptr = reg_wptr; in tn40_fifo_alloc()
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/linux/include/linux/
H A Dstmmac.h1 /* SPDX-License-Identifier: GPL-2.0-only */
58 #define STMMAC_CSR_I_4 0x8 /* clk_csr_i/4 */
93 int pbl; member
188 /* MAC ----- optional PCS ----- SerDes ----- optional PHY ----- Media
192 * mac_interface is the MAC-side interface, which may be the same
193 * as phy_interface if there is no intervening PCS. If there is a
199 /* phy_interface is the PHY-side interface - the interface used by
/linux/drivers/infiniband/hw/ocrdma/
H A Docrdma_sli.h3 * Copyright (C) 2012-2015 Emulex. All rights reserved.
16 * - Redistributions of source code must retain the above copyright notice,
19 * - Redistributions in binary form must reproduce the above copyright
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
36 * linux-drivers@emulex.com
149 #define OCRDMA_DB_CQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */
150 #define OCRDMA_DB_CQ_RING_ID_EXT_MASK 0x0C00 /* bits 10-11 of qid at 12-11 */
151 /* qid #2 msbits at 12-11 */
153 #define OCRDMA_DB_CQ_NUM_POPPED_SHIFT 16 /* bits 16 - 28 */
159 #define OCRDMA_EQ_ID_MASK 0x1FF /* bits 0 - 8 */
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/linux/arch/arm/boot/dts/st/
H A Dstm32h743.dtsi2 * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
4 * This file is dual-licensed: you can use it either under the terms
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
43 #include "../armv7-m.dtsi"
44 #include <dt-bindings/clock/stm32h7-clks.h>
45 #include <dt-bindings/mfd/stm32h7-rcc.h>
46 #include <dt-bindings/interrupt-controller/irq.h>
49 #address-cells = <1>;
50 #size-cells = <1>;
53 clk_hse: clk-hse {
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H A Dstm32mp151.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/stm32mp1-clks.h>
8 #include <dt-bindings/reset/stm32mp1-resets.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
19 compatible = "arm,cortex-a7";
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/linux/arch/riscv/boot/dts/starfive/
H A Djh7110.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive,jh7110-crg.h>
9 #include <dt-bindings/power/starfive,jh7110-pmu.h>
10 #include <dt-bindings/reset/starfive,jh7110-crg.h>
11 #include <dt-bindings/thermal/thermal.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
19 #address-cells = <1>;
20 #size-cells = <0>;
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/linux/drivers/remoteproc/
H A Dqcom_q6v5_mss.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Qualcomm self-authenticating modem subsystem remoteproc driver
7 * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
13 #include <linux/dma-mapping.h>
53 /* PBL/MBA interface registers */
79 #define AXI_IDLE_REG 0x8
87 #define QACCEPT_DENY_REG 0x8
274 if (rc != -EPROBE_DEFER) in q6v5_regulator_init()
298 dev_err(qproc->dev, in q6v5_regulator_enable()
309 dev_err(qproc->dev, in q6v5_regulator_enable()
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/linux/drivers/infiniband/hw/cxgb4/
H A Dt4fw_ri_api.h2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
14 * - Redistributions of source code must retain the above
17 * - Redistributions in binary form must reproduce the above
25 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
45 FW_RI_RDMA_INIT = 0x8, /* CHELSIO RI specific ... */
725 __u64 pbl[2]; member
H A Dt4.h2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
14 * - Redistributions of source code must retain the above
17 * - Redistributions in binary form must reproduce the above
25 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
43 #define T4_PAGESIZE_MASK 0xffff000 /* 4KB-128MB */
49 __be32 rsvd1; /* flit 0 - hw owns */
54 u8 qp_err; /* flit 1 - sw owns */
70 #define T4_MAX_SEND_SGE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - \
72 #define T4_MAX_SEND_INLINE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - \
74 #define T4_MAX_WRITE_INLINE ((T4_SQ_NUM_BYTES - \
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/linux/arch/arm/boot/dts/allwinner/
H A Dsun9i-a80.dtsi2 * Copyright 2014 Chen-Yu Tsai
4 * Chen-Yu Tsai <wens@csie.org>
6 * This file is dual-licensed: you can use it either under the terms
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/clock/sun9i-a80-ccu.h>
48 #include <dt-bindings/clock/sun9i-a80-de.h>
49 #include <dt-bindings/clock/sun9i-a80-usb.h>
50 #include <dt-bindings/reset/sun9i-a80-ccu.h>
51 #include <dt-bindings/reset/sun9i-a80-de.h>
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/linux/drivers/scsi/
H A Dscsi_debug.c1 // SPDX-License-Identifier: GPL-2.0-or-later
10 * Copyright (C) 2001 - 2021 Douglas Gilbert
33 #include <linux/crc-t10dif.h>
39 #include <linux/t10-pi.h>
75 #define LOGICAL_UNIT_COMMUNICATION_FAILURE 0x8
149 #define DEF_SCSI_LEVEL 7 /* INQUIRY, byte2 [6->SPC-4; 7->SPC-5] */
169 #define JDELAY_OVERRIDDEN -9999
207 /* As indicated in SAM-5 and SPC-4 Unit Attentions (UAs) are returned in
229 * per-device DEF_CMD_PER_LUN can be changed via sysfs:
237 /* UA - Unit Attention; SA - Service Action; SSU - Start Stop Unit */
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/linux/drivers/infiniband/hw/mthca/
H A Dmthca_cmd.c16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
78 CMD_CLOSE_HCA = 0x8,
151 * commands. So we can't use strict timeouts described in PRM -- we
194 return readl(dev->hcr + HCR_STATUS_OFFSET) & in go_bit()
206 void __iomem *ptr = dev->cmd.dbell_map; in mthca_cmd_post_dbell()
207 u16 *offs = dev->cmd.dbell_offsets; in mthca_cmd_post_dbell()
249 return -EAGAIN; in mthca_cmd_post_hcr()
257 __raw_writel((__force u32) cpu_to_be32(in_param >> 32), dev->hcr + 0 * 4); in mthca_cmd_post_hcr()
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/linux/arch/arm64/boot/dts/qcom/
H A Dsc8280xp.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
7 #include <dt-bindings/clock/qcom,dispcc-sc8280xp.h>
8 #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
9 #include <dt-bindings/clock/qcom,gpucc-sc8280xp.h>
10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/clock/qcom,sc8280xp-camcc.h>
12 #include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
13 #include <dt-bindings/interconnect/qcom,osm-l3.h>
14 #include <dt-bindings/interconnect/qcom,sc8280xp.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
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/linux/drivers/net/ethernet/chelsio/cxgb4/
H A Dcxgb4_main.c4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
109 /* Include PCI Device IDs for both PF4 and PF0-3 so our PCI probe() routine is
126 #define FW4_CFNAME "cxgb4/t4-config.txt"
127 #define FW5_CFNAME "cxgb4/t5-config.txt"
128 #define FW6_CFNAME "cxgb4/t6-config.txt"
144 * order MSI-X, MSI, legacy INTx interrupts. This parameter determines which
154 MODULE_PARM_DESC(msi, "whether to use INTx (0), MSI (1) or MSI-X (2)");
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/linux/drivers/scsi/lpfc/
H A Dlpfc_init.c4 * Copyright (C) 2017-2024 Broadcom. All Rights Reserved. The term *
6 * Copyright (C) 2004-2016 Emulex. All rights reserved. *
9 * Portions Copyright (C) 2004-2005 Christoph Hellwig *
17 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
26 #include <linux/dma-mapping.h>
108 * lpfc_config_port_prep - Perform lpfc initialization prior to config port
117 * 0 - success.
118 * -ERESTART - requests the SLI layer to reset the HBA and try again.
119 * Any other value - indicates an error.
124 lpfc_vpd_t *vp = &phba->vpd; in lpfc_config_port_prep()
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