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/linux/arch/arm64/boot/dts/amd/
H A Delba-16core.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Copyright 2020-2023 Advanced Micro Devices, Inc.
8 #address-cells = <1>;
9 #size-cells = <0>;
11 cpu-map {
44 compatible = "arm,cortex-a72";
46 next-level-cache = <&l2_0>;
47 enable-method = "psci";
52 compatible = "arm,cortex-a72";
54 next-level-cache = <&l2_0>;
[all …]
/linux/arch/powerpc/boot/dts/fsl/
H A Dp4080si-pre.dtsi4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
35 /dts-v1/;
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
91 #address-cells = <1>;
92 #size-cells = <0>;
98 next-level-cache = <&L2_0>;
99 fsl,portid-mapping = <0x80000000>;
100 L2_0: l2-cache {
[all …]
H A Dt4240si-pre.dtsi4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
35 /dts-v1/;
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
87 #address-cells = <1>;
88 #size-cells = <0>;
94 next-level-cache = <&L2_1>;
95 fsl,portid-mapping = <0x80000000>;
101 next-level-cache = <&L2_1>;
[all …]
H A Dt104xsi-pre.dtsi4 * Copyright 2013-2014 Freescale Semiconductor Inc.
35 /dts-v1/;
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
71 #address-cells = <1>;
72 #size-cells = <0>;
78 next-level-cache = <&L2_1>;
79 #cooling-cells = <2>;
80 L2_1: l2-cache {
[all …]
H A Dp3041si-pre.dtsi4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
35 /dts-v1/;
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
87 #address-cells = <1>;
88 #size-cells = <0>;
94 next-level-cache = <&L2_0>;
95 fsl,portid-mapping = <0x80000000>;
96 L2_0: l2-cache {
[all …]
H A Dp2041si-pre.dtsi4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
35 /dts-v1/;
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
86 #address-cells = <1>;
87 #size-cells = <0>;
93 next-level-cache = <&L2_0>;
94 fsl,portid-mapping = <0x80000000>;
95 L2_0: l2-cache {
[all …]
H A Dp5040si-pre.dtsi4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
35 /dts-v1/;
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
99 #address-cells = <1>;
100 #size-cells = <0>;
106 next-level-cache = <&L2_0>;
107 fsl,portid-mapping = <0x80000000>;
108 L2_0: l2-cache {
[all …]
/linux/arch/riscv/boot/dts/sophgo/
H A Dsg2042-cpus.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #address-cells = <1>;
9 #size-cells = <0>;
10 timebase-frequency = <50000000>;
12 cpu-map {
260 riscv,isa-base = "rv64i";
261 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
265 i-cache-block-size = <64>;
266 i-cache-size = <65536>;
267 i-cache-sets = <512>;
[all …]
/linux/arch/arm64/boot/dts/amazon/
H A Dalpine-v3.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 compatible = "amazon,al-alpine-v3";
14 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
20 #address-cells = <1>;
21 #size-cells = <0>;
25 compatible = "arm,cortex-a72";
[all …]
/linux/arch/arm64/boot/dts/hisilicon/
H A Dhip05.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip05-d02";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
[all …]
H A Dhip07.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip07-d05";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
[all …]
/linux/arch/powerpc/kernel/
H A Dcacheinfo.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Processor cache information made available to userspace via sysfs;
26 /* per-cpu object for tracking:
27 * - a "cache" kobject for the top-level directory
28 * - a list of "index" objects representing the cpu's local cache hierarchy
31 struct kobject *kobj; /* bare (not embedded) kobject for cache
36 /* "index" object: each cpu's cache directory has an index
37 * subdirectory corresponding to a cache object associated with the
42 struct cache_index_dir *next; /* next index in parent directory */ member
43 struct cache *cache; member
[all …]
/linux/arch/arm64/boot/dts/apple/
H A Dt600x-common.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
11 #address-cells = <2>;
12 #size-cells = <2>;
15 #address-cells = <2>;
16 #size-cells = <0>;
18 cpu-map {
63 enable-method = "spin-table";
64 cpu-release-addr = <0 0>; /* To be filled by loader */
65 next-level-cache = <&l2_cache_0>;
66 i-cache-size = <0x20000>;
[all …]
H A Dt6002.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/apple-aic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/apple.h>
15 #include "multi-die-cpp.h"
17 #include "t600x-common.dtsi"
20 compatible = "apple,t6002", "apple,arm-platform";
22 #address-cells = <2>;
23 #size-cells = <2>;
[all …]
/linux/arch/arm64/boot/dts/ti/
H A Dk3-am654.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
8 #include "k3-am65.dtsi"
12 #address-cells = <1>;
13 #size-cells = <0>;
14 cpu-map {
37 compatible = "arm,cortex-a53";
40 enable-method = "psci";
41 i-cache-size = <0x8000>;
42 i-cache-line-size = <64>;
[all …]
H A Dk3-j784s4.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
7 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
11 #include "k3-j784s4-j742s2-common.dtsi"
18 #address-cells = <1>;
19 #size-cells = <0>;
20 cpu-map {
59 compatible = "arm,cortex-a72";
62 enable-method = "psci";
63 i-cache-size = <0xc000>;
64 i-cache-line-size = <64>;
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls2088a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-2088A family SoC.
12 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
13 #include "fsl-ls208xa.dtsi"
17 compatible = "arm,cortex-a72-pmu";
25 compatible = "arm,cortex-a72";
28 cpu-idle-states = <&CPU_PW20>;
29 next-level-cache = <&cluster0_l2>;
30 #cooling-cells = <2>;
35 compatible = "arm,cortex-a72";
[all …]
H A Dfsl-ls2080a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
5 * Copyright 2014-2016 Freescale Semiconductor, Inc.
12 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
13 #include "fsl-ls208xa.dtsi"
17 compatible = "arm,cortex-a57-pmu";
25 compatible = "arm,cortex-a57";
28 cpu-idle-states = <&CPU_PW20>;
29 next-level-cache = <&cluster0_l2>;
30 #cooling-cells = <2>;
[all …]
/linux/Documentation/devicetree/bindings/cache/
H A Dsocionext,uniphier-system-cache.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/cache/socionext,uniphier-system-cache.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: UniPhier outer cache controller
10 UniPhier ARM 32-bit SoCs are integrated with a full-custom outer cache
11 controller system. All of them have a level 2 cache controller, and some
12 have a level 3 cache controller as well.
15 - Masahiro Yamada <yamada.masahiro@socionext.com>
19 const: socionext,uniphier-system-cache
[all …]
/linux/arch/arm64/boot/dts/marvell/
H A Darmada-ap806-quad.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include "armada-ap806.dtsi"
12 compatible = "marvell,armada-ap806-quad", "marvell,armada-ap806";
15 #address-cells = <1>;
16 #size-cells = <0>;
20 compatible = "arm,cortex-a72";
22 enable-method = "psci";
23 #cooling-cells = <2>;
25 i-cache-size = <0xc000>;
26 i-cache-line-size = <64>;
[all …]
H A Darmada-ap807-quad.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include "armada-ap807.dtsi"
12 compatible = "marvell,armada-ap807-quad", "marvell,armada-ap807";
15 #address-cells = <1>;
16 #size-cells = <0>;
20 compatible = "arm,cortex-a72";
22 enable-method = "psci";
23 #cooling-cells = <2>;
25 i-cache-size = <0xc000>;
26 i-cache-line-size = <64>;
[all …]
/linux/arch/arm64/boot/dts/realtek/
H A Drtd16xx.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <1>;
15 #size-cells = <1>;
17 reserved-memory {
18 #address-cells = <1>;
19 #size-cells = <1>;
32 no-map;
[all …]
H A Drtd1296.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
5 * Copyright (c) 2017-2019 Andreas Färber
14 #address-cells = <2>;
15 #size-cells = <0>;
19 compatible = "arm,cortex-a53";
21 next-level-cache = <&l2>;
26 compatible = "arm,cortex-a53";
28 next-level-cache = <&l2>;
33 compatible = "arm,cortex-a53";
35 next-level-cache = <&l2>;
[all …]
/linux/arch/arm64/boot/dts/amlogic/
H A Dmeson-g12b.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "meson-g12.dtsi"
13 #address-cells = <0x2>;
14 #size-cells = <0x0>;
16 cpu-map {
48 compatible = "arm,cortex-a53";
50 enable-method = "psci";
51 capacity-dmips-mhz = <592>;
52 next-level-cache = <&l2>;
53 #cooling-cells = <2>;
[all …]
/linux/arch/arm64/boot/dts/arm/
H A Dfvp-base-revc.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Architecture Envelope Model (AEM) ARMv8-A
11 /dts-v1/;
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include "rtsm_ve-motherboard.dtsi"
18 #include "rtsm_ve-motherboard-rs2.dtsi"
22 compatible = "arm,fvp-base-revc", "arm,vexpress";
23 interrupt-parent = <&gic>;
24 #address-cells = <2>;
25 #size-cells = <2>;
[all …]

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