Lines Matching +full:next +full:- +full:level +full:- +full:cache
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/apple-aic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/apple.h>
14 #include <dt-bindings/spmi/spmi.h>
16 #include "multi-die-cpp.h"
18 #include "t600x-common.dtsi"
21 compatible = "apple,t6002", "apple,arm-platform";
23 #address-cells = <2>;
24 #size-cells = <2>;
27 cpu-map {
72 enable-method = "spin-table";
73 cpu-release-addr = <0 0>; /* To be filled by loader */
74 next-level-cache = <&l2_cache_3>;
75 i-cache-size = <0x20000>;
76 d-cache-size = <0x10000>;
77 operating-points-v2 = <&icestorm_opp>;
78 capacity-dmips-mhz = <714>;
79 performance-domains = <&cpufreq_e_die1>;
86 enable-method = "spin-table";
87 cpu-release-addr = <0 0>; /* To be filled by loader */
88 next-level-cache = <&l2_cache_3>;
89 i-cache-size = <0x20000>;
90 d-cache-size = <0x10000>;
91 operating-points-v2 = <&icestorm_opp>;
92 capacity-dmips-mhz = <714>;
93 performance-domains = <&cpufreq_e_die1>;
100 enable-method = "spin-table";
101 cpu-release-addr = <0 0>; /* To be filled by loader */
102 next-level-cache = <&l2_cache_4>;
103 i-cache-size = <0x30000>;
104 d-cache-size = <0x20000>;
105 operating-points-v2 = <&firestorm_opp>;
106 capacity-dmips-mhz = <1024>;
107 performance-domains = <&cpufreq_p0_die1>;
114 enable-method = "spin-table";
115 cpu-release-addr = <0 0>; /* To be filled by loader */
116 next-level-cache = <&l2_cache_4>;
117 i-cache-size = <0x30000>;
118 d-cache-size = <0x20000>;
119 operating-points-v2 = <&firestorm_opp>;
120 capacity-dmips-mhz = <1024>;
121 performance-domains = <&cpufreq_p0_die1>;
128 enable-method = "spin-table";
129 cpu-release-addr = <0 0>; /* To be filled by loader */
130 next-level-cache = <&l2_cache_4>;
131 i-cache-size = <0x30000>;
132 d-cache-size = <0x20000>;
133 operating-points-v2 = <&firestorm_opp>;
134 capacity-dmips-mhz = <1024>;
135 performance-domains = <&cpufreq_p0_die1>;
142 enable-method = "spin-table";
143 cpu-release-addr = <0 0>; /* To be filled by loader */
144 next-level-cache = <&l2_cache_4>;
145 i-cache-size = <0x30000>;
146 d-cache-size = <0x20000>;
147 operating-points-v2 = <&firestorm_opp>;
148 capacity-dmips-mhz = <1024>;
149 performance-domains = <&cpufreq_p0_die1>;
156 enable-method = "spin-table";
157 cpu-release-addr = <0 0>; /* To be filled by loader */
158 next-level-cache = <&l2_cache_5>;
159 i-cache-size = <0x30000>;
160 d-cache-size = <0x20000>;
161 operating-points-v2 = <&firestorm_opp>;
162 capacity-dmips-mhz = <1024>;
163 performance-domains = <&cpufreq_p1_die1>;
170 enable-method = "spin-table";
171 cpu-release-addr = <0 0>; /* To be filled by loader */
172 next-level-cache = <&l2_cache_5>;
173 i-cache-size = <0x30000>;
174 d-cache-size = <0x20000>;
175 operating-points-v2 = <&firestorm_opp>;
176 capacity-dmips-mhz = <1024>;
177 performance-domains = <&cpufreq_p1_die1>;
184 enable-method = "spin-table";
185 cpu-release-addr = <0 0>; /* To be filled by loader */
186 next-level-cache = <&l2_cache_5>;
187 i-cache-size = <0x30000>;
188 d-cache-size = <0x20000>;
189 operating-points-v2 = <&firestorm_opp>;
190 capacity-dmips-mhz = <1024>;
191 performance-domains = <&cpufreq_p1_die1>;
198 enable-method = "spin-table";
199 cpu-release-addr = <0 0>; /* To be filled by loader */
200 next-level-cache = <&l2_cache_5>;
201 i-cache-size = <0x30000>;
202 d-cache-size = <0x20000>;
203 operating-points-v2 = <&firestorm_opp>;
204 capacity-dmips-mhz = <1024>;
205 performance-domains = <&cpufreq_p1_die1>;
208 l2_cache_3: l2-cache-3 {
209 compatible = "cache";
210 cache-level = <2>;
211 cache-unified;
212 cache-size = <0x400000>;
215 l2_cache_4: l2-cache-4 {
216 compatible = "cache";
217 cache-level = <2>;
218 cache-unified;
219 cache-size = <0xc00000>;
222 l2_cache_5: l2-cache-5 {
223 compatible = "cache";
224 cache-level = <2>;
225 cache-unified;
226 cache-size = <0xc00000>;
231 compatible = "simple-bus";
232 #address-cells = <2>;
233 #size-cells = <2>;
237 nonposted-mmio;
243 compatible = "simple-bus";
244 #address-cells = <2>;
245 #size-cells = <2>;
248 nonposted-mmio;
258 #include "t600x-die0.dtsi"
259 #include "t600x-dieX.dtsi"
262 #include "t600x-pmgr.dtsi"
263 #include "t600x-gpio-pins.dtsi"
272 #include "t600x-dieX.dtsi"
273 #include "t600x-nvme.dtsi"
276 #include "t600x-pmgr.dtsi"
283 e-core-pmu-affinity {
284 apple,fiq-index = <AIC_CPU_PMU_E>;
289 p-core-pmu-affinity {
290 apple,fiq-index = <AIC_CPU_PMU_P>;
301 power-domains = <&ps_afr>, <&ps_afr_die1>;
305 compatible = "apple,agx-g13d", "apple,agx-g13s";