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/linux/drivers/gpu/drm/bridge/
H A Dti-tpd12s015.c1 // SPDX-License-Identifier: GPL-2.0
7 * Based on the omapdrm-specific encoder-opa362 driver
48 return -EINVAL; in tpd12s015_attach()
50 ret = drm_bridge_attach(encoder, tpd->next_bridge, in tpd12s015_attach()
55 gpiod_set_value_cansleep(tpd->ls_oe_gpio, 1); in tpd12s015_attach()
57 /* DC-DC converter needs at max 300us to get to 90% of 5V. */ in tpd12s015_attach()
67 gpiod_set_value_cansleep(tpd->ls_oe_gpio, 0); in tpd12s015_detach()
74 if (gpiod_get_value_cansleep(tpd->hpd_gpio)) in tpd12s015_detect()
90 gpiod_set_value_cansleep(tpd->ct_cp_hpd_gpio, 1); in tpd12s015_hpd_enable()
97 gpiod_set_value_cansleep(tpd->ct_cp_hpd_gpio, 0); in tpd12s015_hpd_disable()
[all …]
H A Dti-sn65dsi86.c1 // SPDX-License-Identifier: GPL-2.0
134 * struct ti_sn65dsi86 - Platform data for ti-sn65dsi86 driver.
135 * @bridge_aux: AUX-bus sub device for MIPI-to-eDP bridge functionality.
136 * @gpio_aux: AUX-bus sub device for GPIO controller functionality.
137 * @aux_aux: AUX-bus sub device for eDP AUX channel functionality.
138 * @pwm_aux: AUX-bus sub device for PWM controller functionality.
153 * @ln_polrs: Value for the 4-bit LN_POLRS field of SN_ENH_FRAME_REG.
159 * serves double-duty of keeping track of the direction and
165 * each other's read-modify-write.
230 ret = regmap_bulk_read(pdata->regmap, reg, buf, ARRAY_SIZE(buf)); in ti_sn65dsi86_read_u16()
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H A Dtda998x_drv.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <sound/hdmi-codec.h>
25 #include <media/cec-notifier.h>
27 #include <dt-bindings/display/tda998x.h>
411 .addr = priv->cec_addr, in cec_write()
417 ret = i2c_transfer(priv->hdmi->adapter, &msg, 1); in cec_write()
419 dev_err(&priv->hdmi->dev, "Error %d writing to cec:0x%x\n", in cec_write()
429 .addr = priv->cec_addr, in cec_read()
433 .addr = priv->cec_addr, in cec_read()
441 ret = i2c_transfer(priv->hdmi->adapter, msg, ARRAY_SIZE(msg)); in cec_read()
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/linux/drivers/gpu/drm/meson/
H A Dmeson_dw_hdmi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
32 #define DRIVER_NAME "meson-dw-hdmi"
33 #define DRIVER_DESC "Amlogic Meson HDMI-TX DRM driver"
40 * - A Synopsys DesignWare HDMI Controller IP
41 * - A TOP control block controlling the Clocks and PHY
42 * - A custom HDMI PHY in order convert video to TMDS signal
47 * | HDMI TOP |<= HPD
55 * The HDMI TOP block only supports HPD sensing.
79 * - HPD Rise & Fall interrupt
80 * - HDMI Controller Interrupt
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/linux/drivers/usb/typec/altmodes/
H A Ddisplayport.c1 // SPDX-License-Identifier: GPL-2.0
3 * USB Typec-C DisplayPort Alternate Mode driver
20 #define DP_HEADER(_dp, ver, cmd) (VDO((_dp)->alt->svid, 1, ver, cmd) \
66 bool hpd; member
70 * hpd is mandatory for irq_hpd assertion, so irq_hpd also needs its own pending flag if
71 * both hpd and irq_hpd are asserted in the first Status Update before the pin assignment
89 if (dp->data.conf) { in dp_altmode_notify()
90 state = get_count_order(DP_CONF_GET_PIN_ASSIGN(dp->data.conf)); in dp_altmode_notify()
96 return typec_altmode_notify(dp->alt, conf, &dp->data); in dp_altmode_notify()
105 conf = (dp->data.conf & DP_CONF_SIGNALLING_MASK) >> DP_CONF_SIGNALLING_SHIFT; in dp_altmode_configure()
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/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc.h2 * Copyright 2012-2023 Advanced Micro Devices, Inc.
61 * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC
65 * MAX_PLANES - representative of the upper bound of planes that are supported by the HW
118 // for example, 1080p -> 8K is 4.0, or 4000 raw value
126 // for example, 8K -> 1080p is 0.25, or 250 raw value
138 * DOC: color-management-caps
143 * abstracted HW. DCE 5-12 had almost no important changes, but starting with
150 * struct rom_curve_caps - predefined transfer function caps for degamma and regamma
166 * struct dpp_color_caps - color pipeline capabilities for display pipe and
171 * just plain 256-entry lookup
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/linux/Documentation/userspace-api/media/cec/
H A Dcec-ioc-adap-g-caps.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
13 CEC_ADAP_G_CAPS - Query device capabilities
42 .. flat-table:: struct cec_caps
43 :header-rows: 0
44 :stub-columns: 0
47 * - char
48 - ``driver[32]``
49 - The name of the cec adapter driver.
50 * - char
51 - ``name[32]``
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/linux/drivers/gpu/drm/amd/amdgpu/
H A Ddce_v8_0.c82 (0x13830 - 0x7030) >> 2,
89 uint32_t hpd; member
95 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
100 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
105 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
110 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
115 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
120 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
129 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); in dce_v8_0_audio_endpt_rreg()
132 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); in dce_v8_0_audio_endpt_rreg()
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H A Ddce_v10_0.c55 static void dce_v10_0_hpd_int_ack(struct amdgpu_device *adev, int hpd);
90 uint32_t hpd; member
96 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
101 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
106 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
111 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
116 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
121 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
150 switch (adev->asic_type) { in dce_v10_0_init_golden_registers()
178 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); in dce_v10_0_audio_endpt_rreg()
[all …]
H A Ddce_v6_0.c94 (0x13830 - 0x7030) >> 2,
101 uint32_t hpd; member
107 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
112 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
117 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
122 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
127 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
132 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
141 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); in dce_v6_0_audio_endpt_rreg()
144 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); in dce_v6_0_audio_endpt_rreg()
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H A Datombios_encoders.c2 * Copyright 2007-11 Advanced Micro Devices, Inc.
74 struct drm_device *dev = amdgpu_encoder->base.dev; in amdgpu_atombios_encoder_get_backlight_level()
77 if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) in amdgpu_atombios_encoder_get_backlight_level()
87 struct drm_encoder *encoder = &amdgpu_encoder->base; in amdgpu_atombios_encoder_set_backlight_level()
88 struct drm_device *dev = amdgpu_encoder->base.dev; in amdgpu_atombios_encoder_set_backlight_level()
92 if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) in amdgpu_atombios_encoder_set_backlight_level()
95 if ((amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) && in amdgpu_atombios_encoder_set_backlight_level()
96 amdgpu_encoder->enc_priv) { in amdgpu_atombios_encoder_set_backlight_level()
97 dig = amdgpu_encoder->enc_priv; in amdgpu_atombios_encoder_set_backlight_level()
98 dig->backlight_level = level; in amdgpu_atombios_encoder_set_backlight_level()
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H A Damdgpu_display.c2 * Copyright 2007-8 Advanced Micro Devices, Inc.
52 * amdgpu_display_hotplug_work_func - work handler for display hotplug event
72 struct drm_mode_config *mode_config = &dev->mode_config; in amdgpu_display_hotplug_work_func()
76 mutex_lock(&mode_config->mutex); in amdgpu_display_hotplug_work_func()
81 mutex_unlock(&mode_config->mutex); in amdgpu_display_hotplug_work_func()
98 schedule_work(&work->flip_work.work); in amdgpu_display_flip_callback()
111 if (!dma_fence_add_callback(fence, &work->cb, in amdgpu_display_flip_handle_fence()
125 struct amdgpu_device *adev = work->adev; in amdgpu_display_flip_work_func()
126 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[work->crtc_id]; in amdgpu_display_flip_work_func()
128 struct drm_crtc *crtc = &amdgpu_crtc->base; in amdgpu_display_flip_work_func()
[all …]
/linux/Documentation/devicetree/bindings/media/cec/
H A Dsamsung,s5p-cec.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/media/cec/samsung,s5p-cec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Marek Szyprowski <m.szyprowski@samsung.com>
14 - $ref: cec-common.yaml#
18 const: samsung,s5p-cec
23 clock-names:
25 - const: hdmicec
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/linux/drivers/media/i2c/
H A Dtda1997x_regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 /* Page 0x00 - General Control */
127 /* HPD Detection */
129 #define DETECT_HPD BIT(6) /* HPD of HDMI level */
157 #define HPD_MAN_CTRL_HPD_PULSE BIT(7) /* HPD Pulse low 110ms */
159 #define HPD_MAN_CTRL_HPD_B BIT(1) /* Assert HPD High for Input A */
160 #define HPD_MAN_CTRL_HPD_A BIT(0) /* Assert HPD High for Input A */
165 #define RT_MAN_CTRL_RT_B BIT(1) /* enable TMDS pull-up on Input B */
166 #define RT_MAN_CTRL_RT_A BIT(0) /* enable TMDS pull-up on Input A */
212 #define PCLK_DELAY_SHIFT 4 /* Pixel delay (-8..+7) */
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/linux/arch/arm/boot/dts/samsung/
H A Dexynos4412-odroidu3.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Hardkernel's Exynos4412 based ODROID-U3 board device tree source
7 * Device tree source file for Hardkernel's ODROID-U3 board which is based
11 /dts-v1/;
12 #include <dt-bindings/leds/common.h>
13 #include "exynos4412-odroid-common.dtsi"
14 #include "exynos4412-prime.dtsi"
17 model = "Hardkernel ODROID-U3 board based on Exynos4412";
18 compatible = "hardkernel,odroid-u3", "samsung,exynos4412", "samsung,exynos4";
29 vbus_otg_reg: regulator-1 {
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H A Dexynos5422-odroidxu3-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Hardkernel Odroid XU3/XU3-Lite/XU4 boards common device tree source
12 #include <dt-bindings/input/input.h>
13 #include "exynos5422-odroid-core.dtsi"
20 gpio-keys {
21 compatible = "gpio-keys";
22 pinctrl-names = "default";
23 pinctrl-0 = <&power_key>;
25 power-key {
36 debounce-interval = <0>;
[all …]
/linux/drivers/gpu/drm/bridge/analogix/
H A Danx7625.c1 // SPDX-License-Identifier: GPL-2.0-only
35 #include <media/v4l2-fwnode.h>
36 #include <sound/hdmi-codec.h>
50 struct device *dev = &client->dev; in i2c_access_workaround()
53 if (client == ctx->last_client) in i2c_access_workaround()
56 ctx->last_client = client; in i2c_access_workaround()
58 if (client == ctx->i2c.tcpc_client) in i2c_access_workaround()
60 else if (client == ctx->i2c.tx_p0_client) in i2c_access_workaround()
62 else if (client == ctx->i2c.tx_p1_client) in i2c_access_workaround()
64 else if (client == ctx->i2c.rx_p0_client) in i2c_access_workaround()
[all …]
/linux/drivers/gpu/drm/radeon/
H A Dr600.c105 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL
125 spin_lock_irqsave(&rdev->rcu_idx_lock, flags); in r600_rcu_rreg()
128 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags); in r600_rcu_rreg()
136 spin_lock_irqsave(&rdev->rcu_idx_lock, flags); in r600_rcu_wreg()
139 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags); in r600_rcu_wreg()
147 spin_lock_irqsave(&rdev->uvd_idx_lock, flags); in r600_uvd_ctx_rreg()
150 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags); in r600_uvd_ctx_rreg()
158 spin_lock_irqsave(&rdev->uvd_idx_lock, flags); in r600_uvd_ctx_wreg()
161 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags); in r600_uvd_ctx_wreg()
165 * r600_get_allowed_info_register - fetch the register for the info ioctl
[all …]
H A Devergreen.c62 spin_lock_irqsave(&rdev->cg_idx_lock, flags); in eg_cg_rreg()
65 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags); in eg_cg_rreg()
73 spin_lock_irqsave(&rdev->cg_idx_lock, flags); in eg_cg_wreg()
76 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags); in eg_cg_wreg()
84 spin_lock_irqsave(&rdev->pif_idx_lock, flags); in eg_pif_phy0_rreg()
87 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags); in eg_pif_phy0_rreg()
95 spin_lock_irqsave(&rdev->pif_idx_lock, flags); in eg_pif_phy0_wreg()
98 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags); in eg_pif_phy0_wreg()
106 spin_lock_irqsave(&rdev->pif_idx_lock, flags); in eg_pif_phy1_rreg()
109 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags); in eg_pif_phy1_rreg()
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/linux/drivers/gpu/drm/msm/hdmi/
H A Dhdmi_hdcp.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2010-2015, The Linux Foundation. All rights reserved.
99 rc = i2c_transfer(hdmi->i2c, msgs, 2); in msm_hdmi_ddc_read()
101 retry--; in msm_hdmi_ddc_read()
107 rc = -EIO; in msm_hdmi_ddc_read()
131 if (data_len > (HDCP_DDC_WRITE_MAX_BYTE_NUM - 1)) { in msm_hdmi_ddc_write()
133 return -ERANGE; in msm_hdmi_ddc_write()
141 rc = i2c_transfer(hdmi->i2c, msgs, 1); in msm_hdmi_ddc_write()
143 retry--; in msm_hdmi_ddc_write()
149 rc = -EIO; in msm_hdmi_ddc_write()
[all …]
/linux/drivers/gpu/drm/rockchip/
H A Dcdn-dp-core.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Chris Zhong <zyw@rock-chips.com>
16 #include <sound/hdmi-codec.h>
27 #include "cdn-dp-core.h"
28 #include "cdn-dp-reg.h"
63 { .compatible = "rockchip,rk3399-cdn-dp",
75 ret = clk_prepare_enable(dp->grf_clk); in cdn_dp_grf_write()
77 DRM_DEV_ERROR(dp->dev, "Failed to prepare_enable grf clock\n"); in cdn_dp_grf_write()
81 ret = regmap_write(dp->grf, reg, val); in cdn_dp_grf_write()
83 DRM_DEV_ERROR(dp->dev, "Could not write to GRF: %d\n", ret); in cdn_dp_grf_write()
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/linux/drivers/gpu/drm/bridge/cadence/
H A Dcdns-mhdp8546-core.h1 /* SPDX-License-Identifier: GPL-2.0 */
7 * Author: Quentin Schulz <quentin.schulz@free-electrons.com>
98 #define CDNS_DP_NUM_LANES(x) ((x) - 1)
120 #define CDNS_DP_LANE_EN_LANES(x) GENMASK((x) - 1, 0)
243 /* HPD */
260 #define CDNS_SUPPORT_TPS(x) BIT((x) - 1)
317 * MHDP_HW_READY <-> MHDP_HW_STOPPED
398 * setting needs to be protected when enabling the FW.
/linux/drivers/platform/x86/
H A Dapple-gmux.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (C) 2010-2012 Andreas Heider <andreas@meetr.de>
19 #include <linux/apple-gmux.h>
32 * A `Lattice XP2`_ on pre-retinas, a `Renesas R4F2113`_ on pre-T2 retinas.
41 * dual GPUs but no built-in display.)
45 * to access a pre-retina gmux are infixed ``_pio_``, those for a pre-T2
54 * https://www.nxp.com/docs/en/data-sheet/PCAL6524.pdf
112 return inb(gmux_data->iostart + port); in gmux_pio_read8()
118 outb(val, gmux_data->iostart + port); in gmux_pio_write8()
123 return inl(gmux_data->iostart + port); in gmux_pio_read32()
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/linux/drivers/gpu/drm/vc4/
H A Dvc4_hdmi.c1 // SPDX-License-Identifier: GPL-2.0-only
21 * and transfers them over an internal MAI (multi-channel audio
53 #include <sound/hdmi-codec.h>
118 struct drm_display_info *display = &vc4_hdmi->connector.display_info; in vc4_hdmi_supports_scrambling()
120 lockdep_assert_held(&vc4_hdmi->mutex); in vc4_hdmi_supports_scrambling()
122 if (!display->is_hdmi) in vc4_hdmi_supports_scrambling()
125 if (!display->hdmi.scdc.supported || in vc4_hdmi_supports_scrambling()
126 !display->hdmi.scdc.scrambling.supported) in vc4_hdmi_supports_scrambling()
143 struct drm_debugfs_entry *entry = m->private; in vc4_hdmi_debugfs_regs()
144 struct vc4_hdmi *vc4_hdmi = entry->file.data; in vc4_hdmi_debugfs_regs()
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/linux/drivers/gpu/drm/mediatek/
H A Dmtk_dp.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2019-2022 MediaTek Inc.
18 #include <linux/arm-smccc.h>
23 #include <linux/media-bus-format.h>
24 #include <linux/nvmem-consumer.h>
33 #include <sound/hdmi-codec.h>
402 .name = "mtk-dp-registers",
415 ret = regmap_read(mtk_dp->regs, offset, &read_val); in mtk_dp_read()
417 dev_err(mtk_dp->dev, "Failed to read register 0x%x: %d\n", in mtk_dp_read()
427 int ret = regmap_write(mtk_dp->regs, offset, val); in mtk_dp_write()
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