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/linux/drivers/mtd/nand/
H A Dcore.c10 #define pr_fmt(fmt) "nand: " fmt
13 #include <linux/mtd/nand.h>
17 * @nand: NAND device
22 bool nanddev_isbad(struct nand_device *nand, const struct nand_pos *pos) in nanddev_isbad() argument
27 if (nanddev_bbt_is_initialized(nand)) { in nanddev_isbad()
31 entry = nanddev_bbt_pos_to_entry(nand, pos); in nanddev_isbad()
32 status = nanddev_bbt_get_block_status(nand, entry); in nanddev_isbad()
35 if (nand->ops->isbad(nand, pos)) in nanddev_isbad()
40 nanddev_bbt_set_block_status(nand, entry, status); in nanddev_isbad()
50 return nand->ops->isbad(nand, pos); in nanddev_isbad()
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H A Decc.c10 * This file describes the abstraction of any NAND ECC engine. It has been
15 * - external: The ECC engine is outside the NAND pipeline, typically this
17 * outside the NAND controller pipeline.
18 * - pipelined: The ECC engine is inside the NAND pipeline, ie. on the
19 * controller's side. This is the case of most of the raw NAND
23 * - ondie: The ECC engine is inside the NAND pipeline, on the chip's side.
24 * Some NAND chips can correct themselves the data.
44 * - read: Load data from the NAND chip
45 * - write: Store data in the NAND chip
97 #include <linux/mtd/nand.h>
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H A Decc-sw-bch.c14 #include <linux/mtd/nand.h>
15 #include <linux/mtd/nand-ecc-sw-bch.h>
19 * @nand: NAND device
23 int nand_ecc_sw_bch_calculate(struct nand_device *nand, in nand_ecc_sw_bch_calculate() argument
26 struct nand_ecc_sw_bch_conf *engine_conf = nand->ecc.ctx.priv; in nand_ecc_sw_bch_calculate()
30 bch_encode(engine_conf->bch, buf, nand->ecc.ctx.conf.step_size, code); in nand_ecc_sw_bch_calculate()
42 * @nand: NAND device
49 int nand_ecc_sw_bch_correct(struct nand_device *nand, unsigned char *buf, in nand_ecc_sw_bch_correct() argument
52 struct nand_ecc_sw_bch_conf *engine_conf = nand->ecc.ctx.priv; in nand_ecc_sw_bch_correct()
53 unsigned int step_size = nand->ecc.ctx.conf.step_size; in nand_ecc_sw_bch_correct()
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H A Dbbt.c10 #define pr_fmt(fmt) "nand-bbt: " fmt
12 #include <linux/mtd/nand.h>
17 * @nand: NAND device
23 int nanddev_bbt_init(struct nand_device *nand) in nanddev_bbt_init() argument
26 unsigned int nblocks = nanddev_neraseblocks(nand); in nanddev_bbt_init()
28 nand->bbt.cache = bitmap_zalloc(nblocks * bits_per_block, GFP_KERNEL); in nanddev_bbt_init()
29 if (!nand->bbt.cache) in nanddev_bbt_init()
38 * @nand: NAND device
42 void nanddev_bbt_cleanup(struct nand_device *nand) in nanddev_bbt_cleanup() argument
44 bitmap_free(nand->bbt.cache); in nanddev_bbt_cleanup()
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/linux/Documentation/devicetree/bindings/mtd/
H A Dbrcm,brcmnand.yaml7 title: Broadcom STB NAND Controller
15 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
27 -- Additional SoC-specific NAND controller properties --
29 The NAND controller is integrated differently on the variety of SoCs on which
31 bits with which to control the 8 exposed NAND interrupts, as well as hardware
35 interesting ways, sometimes with registers that lump multiple NAND-related
39 register resources within the NAND controller node above.
58 - description: BCMBCA SoC-specific NAND controller
60 - const: brcm,nand-bcm63138
65 - description: iProc SoC-specific NAND controller
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H A Dmarvell,nand-controller.yaml4 $id: http://devicetree.org/schemas/mtd/marvell,nand-controller.yaml#
7 title: Marvell NAND Flash Controller (NFC)
16 - const: marvell,armada-8k-nand-controller
17 - const: marvell,armada370-nand-controller
19 - marvell,ac5-nand-controller
20 - marvell,armada370-nand-controller
21 - marvell,pxa3xx-nand-controller
25 - marvell,armada-8k-nand
26 - marvell,armada370-nand
27 - marvell,pxa3xx-nand
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H A Dnvidia-tegra20-nand.txt1 NVIDIA Tegra NAND Flash controller
5 - "nvidia,tegra20-nand"
11 - nand
15 - nand
18 Individual NAND chips are children of the NAND controller node. Currently
19 only one NAND chip supported.
25 - nand-ecc-mode: String, operation mode of the NAND ecc mode. Currently only
27 - nand-ecc-algo: string, algorithm of NAND ECC.
29 - nand-bus-width : See nand-controller.yaml
30 - nand-on-flash-bbt: See nand-controller.yaml
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H A Ddenali,nand.yaml4 $id: http://devicetree.org/schemas/mtd/denali,nand.yaml#
7 title: Denali NAND controller
15 - altr,socfpga-denali-nand
16 - socionext,uniphier-denali-nand-v5a
17 - socionext,uniphier-denali-nand-v5b
38 nand: controller core clock
42 - const: nand
53 nand: controller core reset
57 - const: nand
59 - const: nand
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H A Datmel-nand.txt1 Atmel NAND flash controller bindings
3 The NAND flash controller node should be defined under the EBI bus (see
5 One or several NAND devices can be defined under this NAND controller.
6 The NAND controller might be connected to an ECC engine.
8 * NAND controller bindings:
12 "atmel,at91rm9200-nand-controller"
13 "atmel,at91sam9260-nand-controller"
14 "atmel,at91sam9261-nand-controller"
15 "atmel,at91sam9g45-nand-controller"
16 "atmel,sama5d3-nand-controller"
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H A Dsamsung-s3c2410.txt1 * Samsung S3C2410 and compatible NAND flash controller
5 "samsung,s3c2410-nand"
6 "samsung,s3c2412-nand"
7 "samsung,s3c2440-nand"
9 - #address-cells, #size-cells : see nand-controller.yaml
10 - clocks : phandle to the nand controller clock
11 - clock-names : must contain "nand"
14 Child nodes representing the available nand chips.
17 - nand-ecc-mode : see nand-controller.yaml
18 - nand-on-flash-bbt : see nand-controller.yaml
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H A Dhisi504-nand.txt1 Hisilicon Hip04 Soc NAND controller DT binding
7 NAND controller's registers. The second contains base
8 physical address and size of NAND controller's buffer.
10 - nand-bus-width: See nand-controller.yaml.
11 - nand-ecc-mode: Support none and hw ecc mode.
17 - nand-ecc-strength: Number of bits to correct per ECC step.
18 - nand-ecc-step-size: Number of data bytes covered by a single ECC step.
22 - nand-ecc-strength = <16>, nand-ecc-step-size = <1024>
29 nand: nand@4020000 {
33 nand-bus-width = <8>;
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H A Dfsmc-nand.txt2 NAND Interface
5 - compatible : "st,spear600-fsmc-nand", "stericsson,fsmc-nand"
12 - nand-skip-bbtscan: Indicates the BBT scanning should be skipped
13 - timings: array of 6 bytes for NAND timings. The meanings of these bytes
27 NAND flash in response to SMWAITn. Zero means 1 cycle,
32 - bank: default NAND bank to use (0-3 are valid, 0 is the default).
33 - nand-ecc-mode : see nand-controller.yaml
34 - nand-ecc-strength : see nand-controller.yaml
35 - nand-ecc-step-size : see nand-controller.yaml
43 compatible = "st,spear600-fsmc-nand";
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H A Dmediatek,mtk-nfc.yaml7 title: MediaTek(MTK) SoCs raw NAND FLASH controller (NFC)
42 "^nand@[a-f0-9]$":
43 $ref: raw-nand-chip.yaml#
48 nand-ecc-mode:
52 - $ref: nand-controller.yaml#
61 "^nand@[a-f0-9]$":
63 nand-ecc-step-size:
65 nand-ecc-strength:
76 "^nand@[a-f0-9]$":
78 nand-ecc-step-size:
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H A Dingenic,nand.yaml4 $id: http://devicetree.org/schemas/mtd/ingenic,nand.yaml#
7 title: Ingenic SoCs NAND controller
13 - $ref: nand-controller.yaml#
19 - ingenic,jz4740-nand
20 - ingenic,jz4725b-nand
21 - ingenic,jz4780-nand
25 - description: Bank number, offset and size of first attached NAND chip
26 - description: Bank number, offset and size of second attached NAND chip
27 - description: Bank number, offset and size of third attached NAND chip
28 - description: Bank number, offset and size of fourth attached NAND chip
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H A Dti,gpmc-nand.yaml4 $id: http://devicetree.org/schemas/mtd/ti,gpmc-nand.yaml#
7 title: Texas Instruments GPMC NAND Flash controller.
14 GPMC NAND controller/Flash is represented as a child of the
21 - ti,am64-nand
22 - ti,omap2-nand
36 ti,nand-ecc-opt:
41 ti,nand-xfer-type:
52 nand-bus-width:
54 Bus width to the NAND chip
61 GPIO connection to R/B signal from NAND chip
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H A Damlogic,meson-nand.yaml4 $id: http://devicetree.org/schemas/mtd/amlogic,meson-nand.yaml#
7 title: Amlogic NAND Flash Controller (NFC) for GXBB/GXL/AXG family SoCs
10 - $ref: nand-controller.yaml
41 "^nand@[0-7]$":
43 $ref: raw-nand-chip.yaml
49 nand-ecc-mode:
52 nand-ecc-step-size:
55 nand-ecc-strength:
62 nand-rb:
86 nand-ecc-strength: [nand-ecc-step-size]
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H A Drockchip,nand-controller.yaml4 $id: http://devicetree.org/schemas/mtd/rockchip,nand-controller.yaml#
7 title: Rockchip SoCs NAND FLASH Controller (NFC)
10 - $ref: nand-controller.yaml#
58 "^nand@[0-7]$":
60 $ref: raw-nand-chip.yaml
66 nand-ecc-mode:
69 nand-ecc-step-size:
72 nand-ecc-strength:
88 nand-bus-width:
98 Only used in combination with 'nand-is-boot-medium'.
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H A Dnand-controller.yaml4 $id: http://devicetree.org/schemas/mtd/nand-controller.yaml#
7 title: NAND Controller Common Properties
14 The NAND controller should be represented with its own DT node, and
15 all NAND chips attached to this controller should be defined as
16 children nodes of the NAND controller. This representation should be
21 pattern: "^nand-controller(@.*)?"
35 NAND controller (even if they are not used). As many additional
37 lines. 'reg' entries of the NAND chip subnodes become indexes of
43 "^nand@[a-f0-9]$":
45 $ref: raw-nand-chip.yaml#
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/linux/drivers/mtd/nand/raw/
H A Dmeson_nand.c3 * Amlogic Meson Nand Flash Controller Driver
101 /* nand flash controller delay 3 ns */
124 struct nand_chip nand; member
258 static struct meson_nfc_nand_chip *to_meson_nand(struct nand_chip *nand) in to_meson_nand() argument
260 return container_of(nand, struct meson_nfc_nand_chip, nand); in to_meson_nand()
263 static void meson_nfc_select_chip(struct nand_chip *nand, int chip) in meson_nfc_select_chip() argument
265 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand); in meson_nfc_select_chip()
266 struct meson_nfc *nfc = nand_get_controller_data(nand); in meson_nfc_select_chip()
306 static int meson_nfc_is_boot_page(struct nand_chip *nand, int page) in meson_nfc_is_boot_page() argument
308 const struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand); in meson_nfc_is_boot_page()
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H A Dnand_ids.c25 * Some incompatible NAND chips share device ID's and so must be
68 LEGACY_ID_NAND("NAND 4MiB 5V 8-bit", 0x6B, 4, SZ_8K, SP_OPTIONS),
69 LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE3, 4, SZ_8K, SP_OPTIONS),
70 LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE5, 4, SZ_8K, SP_OPTIONS),
71 LEGACY_ID_NAND("NAND 8MiB 3,3V 8-bit", 0xD6, 8, SZ_8K, SP_OPTIONS),
72 LEGACY_ID_NAND("NAND 8MiB 3,3V 8-bit", 0xE6, 8, SZ_8K, SP_OPTIONS),
74 LEGACY_ID_NAND("NAND 16MiB 1,8V 8-bit", 0x33, 16, SZ_16K, SP_OPTIONS),
75 LEGACY_ID_NAND("NAND 16MiB 3,3V 8-bit", 0x73, 16, SZ_16K, SP_OPTIONS),
76 LEGACY_ID_NAND("NAND 16MiB 1,8V 16-bit", 0x43, 16, SZ_16K, SP_OPTIONS16),
77 LEGACY_ID_NAND("NAND 16MiB 3,3V 16-bit", 0x53, 16, SZ_16K, SP_OPTIONS16),
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/linux/drivers/mtd/nand/spi/
H A Dcore.c10 #define pr_fmt(fmt) "spi-nand: " fmt
53 struct nand_device *nand = spinand_to_nand(spinand); in spinand_get_cfg() local
56 spinand->cur_target >= nand->memorg.ntargets)) in spinand_get_cfg()
65 struct nand_device *nand = spinand_to_nand(spinand); in spinand_set_cfg() local
69 spinand->cur_target >= nand->memorg.ntargets)) in spinand_set_cfg()
109 * spinand_select_target() - Select a specific NAND target/die
119 struct nand_device *nand = spinand_to_nand(spinand); in spinand_select_target() local
122 if (WARN_ON(target >= nand->memorg.ntargets)) in spinand_select_target()
128 if (nand->memorg.ntargets == 1) { in spinand_select_target()
143 struct nand_device *nand = spinand_to_nand(spinand); in spinand_read_cfg() local
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/linux/drivers/mtd/nand/raw/atmel/
H A Dnand-controller.c13 * Derived from drivers/mtd/nand/autcpu12.c (removed in v3.8)
24 * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
30 * Add Nand Flash Controller support for SAMA5 SoC
201 struct atmel_nand *nand);
203 int (*setup_interface)(struct atmel_nand *nand, int csline,
205 int (*exec_op)(struct atmel_nand *nand,
337 dev_err(nc->base.dev, "Waiting NAND R/B Timeout\n"); in atmel_nfc_wait()
462 "Failed to send NAND command (err = %d)!", in atmel_nfc_exec_op()
471 static void atmel_nand_data_in(struct atmel_nand *nand, void *buf, in atmel_nand_data_in() argument
476 nc = to_nand_controller(nand->base.controller); in atmel_nand_data_in()
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/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmarvell,kirkwood-pinctrl.txt24 mpp0 0 gpio, nand(io2), spi(cs)
25 mpp1 1 gpo, nand(io3), spi(mosi)
26 mpp2 2 gpo, nand(io4), spi(sck)
27 mpp3 3 gpo, nand(io5), spi(miso)
28 mpp4 4 gpio, nand(io6), uart0(rxd), ptp(clk)
29 mpp5 5 gpo, nand(io7), uart0(txd), ptp(trig)
45 mpp18 18 gpo, nand(io0)
46 mpp19 19 gpo, nand(io1)
62 mpp0 0 gpio, nand(io2), spi(cs)
63 mpp1 1 gpo, nand(io3), spi(mosi)
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H A Dlantiq,pinctrl-xway.txt56 ebu wait, nand ale, nand cs1, nand cle, spi_di, spi_do, spi_clk, spi_cs1,
67 ebu cs1, ebu wait, nand ale, nand cs1, nand cle, nand rdy, nand rd,
79 ebu cs1, ebu wait, nand ale, nand cs1, nand cle, nand rdy, nand rd,
93 exin0, exin1, exin2, exin4, nand ale, nand cs0, nand cs1, nand cle,
94 nand rdy, nand rd, nand_d0, nand_d1, nand_d2, nand_d3, nand_d4, nand_d5,
95 nand_d6, nand_d7, nand_d1, nand wr, nand wp, nand se, spi_di, spi_do,
/linux/include/linux/mtd/
H A Dspinand.h15 #include <linux/mtd/nand.h>
20 * Standard SPI NAND flash operations
227 * Standard SPI NAND flash commands
280 * struct spinand_id - SPI NAND id structure
297 * struct spinand_devid - SPI NAND device id structure
316 * struct manufacurer_ops - SPI NAND manufacturer specific operations
317 * @init: initialize a SPI NAND device
318 * @cleanup: cleanup a SPI NAND device
320 * Each SPI NAND manufacturer driver should implement this interface so that
321 * NAND chips coming from this vendor can be initialized properly.
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