| /linux/drivers/mtd/nand/raw/ |
| H A D | nuvoton-ma35d1-nand-controller.c | 148 struct ma35_nand_info *nand = nand_get_controller_data(chip); in ma35_clear_spare() local
152 writel(0xff, nand->regs + MA35_NFI_REG_NANDRA0); in ma35_clear_spare()
155 static inline void read_remaining_bytes(struct ma35_nand_info *nand, u32 *buf, in read_remaining_bytes() argument
158 u32 value = readl(nand->regs + MA35_NFI_REG_NANDRA0 + offset); in read_remaining_bytes()
170 struct ma35_nand_info *nand = nand_get_controller_data(chip); in ma35_read_spare() local
176 read_remaining_bytes(nand, buf, off, 4 - len, 1); in ma35_read_spare()
182 *buf++ = readl(nand->regs + MA35_NFI_REG_NANDRA0 + off + (i * 4)); in ma35_read_spare()
184 read_remaining_bytes(nand, buf, off + (size & ~3), size % 4, 0); in ma35_read_spare()
189 struct ma35_nand_info *nand = nand_get_controller_data(chip); in ma35_write_spare() local
195 writel(*buf++, nand->regs + MA35_NFI_REG_NANDRA0 + j); in ma35_write_spare()
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| H A D | meson_nand.c | 3 * Amlogic Meson Nand Flash Controller Driver
101 /* nand flash controller delay 3 ns */
124 struct nand_chip nand; member
258 static struct meson_nfc_nand_chip *to_meson_nand(struct nand_chip *nand) in to_meson_nand() argument
260 return container_of(nand, struct meson_nfc_nand_chip, nand); in to_meson_nand()
263 static void meson_nfc_select_chip(struct nand_chip *nand, int chip) in meson_nfc_select_chip() argument
265 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand); in meson_nfc_select_chip()
266 struct meson_nfc *nfc = nand_get_controller_data(nand); in meson_nfc_select_chip()
306 static int meson_nfc_is_boot_page(struct nand_chip *nand, int page) in meson_nfc_is_boot_page() argument
308 const struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand); in meson_nfc_is_boot_page()
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| H A D | nand_ids.c | 25 * Some incompatible NAND chips share device ID's and so must be
68 LEGACY_ID_NAND("NAND 4MiB 5V 8-bit", 0x6B, 4, SZ_8K, SP_OPTIONS),
69 LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE3, 4, SZ_8K, SP_OPTIONS),
70 LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE5, 4, SZ_8K, SP_OPTIONS),
71 LEGACY_ID_NAND("NAND 8MiB 3,3V 8-bit", 0xD6, 8, SZ_8K, SP_OPTIONS),
72 LEGACY_ID_NAND("NAND 8MiB 3,3V 8-bit", 0xE6, 8, SZ_8K, SP_OPTIONS),
74 LEGACY_ID_NAND("NAND 16MiB 1,8V 8-bit", 0x33, 16, SZ_16K, SP_OPTIONS),
75 LEGACY_ID_NAND("NAND 16MiB 3,3V 8-bit", 0x73, 16, SZ_16K, SP_OPTIONS),
76 LEGACY_ID_NAND("NAND 16MiB 1,8V 16-bit", 0x43, 16, SZ_16K, SP_OPTIONS16),
77 LEGACY_ID_NAND("NAND 16MiB 3,3V 16-bit", 0x53, 16, SZ_16K, SP_OPTIONS16),
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| H A D | mtk_nand.c | 3 * MTK NAND Flash controller driver.
19 #include <linux/mtd/nand-ecc-mtk.h>
21 /* NAND controller register definition */
89 #define MTK_NAME "mtk-nand"
126 struct nand_chip nand; member
178 static inline struct mtk_nfc_nand_chip *to_mtk_nand(struct nand_chip *nand) in to_mtk_nand() argument
180 return container_of(nand, struct mtk_nfc_nand_chip, nand); in to_mtk_nand()
499 static void mtk_nfc_select_target(struct nand_chip *nand, unsigned int cs) in mtk_nfc_select_target() argument
501 struct mtk_nfc *nfc = nand_get_controller_data(nand); in mtk_nfc_select_target()
502 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(nand); in mtk_nfc_select_target()
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| /linux/Documentation/devicetree/bindings/mtd/ |
| H A D | denali,nand.yaml | 4 $id: http://devicetree.org/schemas/mtd/denali,nand.yaml#
7 title: Denali NAND controller
15 - altr,socfpga-denali-nand
16 - socionext,uniphier-denali-nand-v5a
17 - socionext,uniphier-denali-nand-v5b
38 nand: controller core clock
42 - const: nand
53 nand: controller core reset
57 - const: nand
59 - const: nand
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| H A D | atmel-nand.txt | 1 Atmel NAND flash controller bindings
3 The NAND flash controller node should be defined under the EBI bus (see
5 One or several NAND devices can be defined under this NAND controller.
6 The NAND controller might be connected to an ECC engine.
8 * NAND controller bindings:
12 "atmel,at91rm9200-nand-controller"
13 "atmel,at91sam9260-nand-controller"
14 "atmel,at91sam9261-nand-controller"
15 "atmel,at91sam9g45-nand-controller"
16 "atmel,sama5d3-nand-controller"
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| H A D | hisi504-nand.txt | 1 Hisilicon Hip04 Soc NAND controller DT binding
7 NAND controller's registers. The second contains base
8 physical address and size of NAND controller's buffer.
10 - nand-bus-width: See nand-controller.yaml.
11 - nand-ecc-mode: Support none and hw ecc mode.
17 - nand-ecc-strength: Number of bits to correct per ECC step.
18 - nand-ecc-step-size: Number of data bytes covered by a single ECC step.
22 - nand-ecc-strength = <16>, nand-ecc-step-size = <1024>
29 nand: nand@4020000 {
33 nand-bus-width = <8>;
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| H A D | fsmc-nand.txt | 2 NAND Interface
5 - compatible : "st,spear600-fsmc-nand", "stericsson,fsmc-nand"
12 - nand-skip-bbtscan: Indicates the BBT scanning should be skipped
13 - timings: array of 6 bytes for NAND timings. The meanings of these bytes
27 NAND flash in response to SMWAITn. Zero means 1 cycle,
32 - bank: default NAND bank to use (0-3 are valid, 0 is the default).
33 - nand-ecc-mode : see nand-controller.yaml
34 - nand-ecc-strength : see nand-controller.yaml
35 - nand-ecc-step-size : see nand-controller.yaml
43 compatible = "st,spear600-fsmc-nand";
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| H A D | mediatek,mtk-nfc.yaml | 7 title: MediaTek(MTK) SoCs raw NAND FLASH controller (NFC)
42 "^nand@[a-f0-9]$":
43 $ref: raw-nand-chip.yaml#
48 nand-ecc-mode:
52 - $ref: nand-controller.yaml#
61 "^nand@[a-f0-9]$":
63 nand-ecc-step-size:
65 nand-ecc-strength:
76 "^nand@[a-f0-9]$":
78 nand-ecc-step-size:
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| H A D | ingenic,nand.yaml | 4 $id: http://devicetree.org/schemas/mtd/ingenic,nand.yaml#
7 title: Ingenic SoCs NAND controller
13 - $ref: nand-controller.yaml#
19 - ingenic,jz4740-nand
20 - ingenic,jz4725b-nand
21 - ingenic,jz4780-nand
25 - description: Bank number, offset and size of first attached NAND chip
26 - description: Bank number, offset and size of second attached NAND chip
27 - description: Bank number, offset and size of third attached NAND chip
28 - description: Bank number, offset and size of fourth attached NAND chip
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| H A D | ti,gpmc-nand.yaml | 4 $id: http://devicetree.org/schemas/mtd/ti,gpmc-nand.yaml#
7 title: Texas Instruments GPMC NAND Flash controller.
14 GPMC NAND controller/Flash is represented as a child of the
21 - ti,am64-nand
22 - ti,omap2-nand
36 ti,nand-ecc-opt:
41 ti,nand-xfer-type:
52 nand-bus-width:
54 Bus width to the NAND chip
61 GPIO connection to R/B signal from NAND chip
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| H A D | rockchip,nand-controller.yaml | 4 $id: http://devicetree.org/schemas/mtd/rockchip,nand-controller.yaml#
7 title: Rockchip SoCs NAND FLASH Controller (NFC)
10 - $ref: nand-controller.yaml#
58 "^nand@[0-7]$":
60 $ref: raw-nand-chip.yaml
66 nand-ecc-mode:
69 nand-ecc-step-size:
72 nand-ecc-strength:
88 nand-bus-width:
98 Only used in combination with 'nand-is-boot-medium'.
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| H A D | technologic,nand.yaml | 4 $id: http://devicetree.org/schemas/mtd/technologic,nand.yaml#
7 title: Technologic Systems NAND controller
13 - $ref: nand-controller.yaml
18 - const: technologic,ts7200-nand
21 - technologic,ts7300-nand
22 - technologic,ts7260-nand
23 - technologic,ts7250-nand
24 - const: technologic,ts7200-nand
37 nand-controller@60000000 {
38 compatible = "technologic,ts7200-nand";
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| H A D | gpio-control-nand.txt | 1 GPIO assisted NAND flash
3 The GPIO assisted NAND flash uses a memory mapped interface to
4 read/write the NAND commands and data and GPIO pins for the control
8 - compatible : "gpio-control-nand"
10 resource describes the data bus connected to the NAND flash and all accesses
14 - gpios : Specifies the GPIO pins to control the NAND device. The order of
22 - gpio-control-nand,io-sync-reg : A 64-bit physical address for a read
24 the GPIO's and the NAND flash data bus. If present, then after changing
33 gpio-nand@1,0 {
34 compatible = "gpio-control-nand";
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| H A D | mxicy,nand-ecc-engine.yaml | 4 $id: http://devicetree.org/schemas/mtd/mxicy,nand-ecc-engine.yaml#
7 title: Macronix NAND ECC engine
14 const: mxicy,nand-ecc-engine-rev3
44 compatible = "spi-nand";
46 nand-ecc-engine = <&ecc_engine0>;
51 compatible = "mxicy,nand-ecc-engine-rev3";
65 nand-ecc-engine = <&ecc_engine1>;
68 compatible = "spi-nand";
70 nand-ecc-engine = <&spi_controller1>;
75 compatible = "mxicy,nand-ecc-engine-rev3";
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| /linux/drivers/mtd/nand/ |
| H A D | ecc-sw-bch.c | 14 #include <linux/mtd/nand.h>
15 #include <linux/mtd/nand-ecc-sw-bch.h>
19 * @nand: NAND device
23 int nand_ecc_sw_bch_calculate(struct nand_device *nand, in nand_ecc_sw_bch_calculate() argument
26 struct nand_ecc_sw_bch_conf *engine_conf = nand->ecc.ctx.priv; in nand_ecc_sw_bch_calculate()
30 bch_encode(engine_conf->bch, buf, nand->ecc.ctx.conf.step_size, code); in nand_ecc_sw_bch_calculate()
42 * @nand: NAND device
49 int nand_ecc_sw_bch_correct(struct nand_device *nand, unsigned char *buf, in nand_ecc_sw_bch_correct() argument
52 struct nand_ecc_sw_bch_conf *engine_conf = nand->ecc.ctx.priv; in nand_ecc_sw_bch_correct()
53 unsigned int step_size = nand->ecc.ctx.conf.step_size; in nand_ecc_sw_bch_correct()
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| H A D | bbt.c | 10 #define pr_fmt(fmt) "nand-bbt: " fmt
12 #include <linux/mtd/nand.h>
17 * @nand: NAND device
23 int nanddev_bbt_init(struct nand_device *nand) in nanddev_bbt_init() argument
26 unsigned int nblocks = nanddev_neraseblocks(nand); in nanddev_bbt_init()
28 nand->bbt.cache = bitmap_zalloc(nblocks * bits_per_block, GFP_KERNEL); in nanddev_bbt_init()
29 if (!nand->bbt.cache) in nanddev_bbt_init()
38 * @nand: NAND device
42 void nanddev_bbt_cleanup(struct nand_device *nand) in nanddev_bbt_cleanup() argument
44 bitmap_free(nand->bbt.cache); in nanddev_bbt_cleanup()
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| /linux/drivers/mtd/nand/spi/ |
| H A D | core.c | 10 #define pr_fmt(fmt) "spi-nand: " fmt
154 struct nand_device *nand = spinand_to_nand(spinand); in spinand_get_cfg() local
157 spinand->cur_target >= nand->memorg.ntargets)) in spinand_get_cfg()
166 struct nand_device *nand = spinand_to_nand(spinand); in spinand_set_cfg() local
170 spinand->cur_target >= nand->memorg.ntargets)) in spinand_set_cfg()
210 * spinand_select_target() - Select a specific NAND target/die
220 struct nand_device *nand = spinand_to_nand(spinand); in spinand_select_target() local
223 if (WARN_ON(target >= nand->memorg.ntargets)) in spinand_select_target()
229 if (nand->memorg.ntargets == 1) { in spinand_select_target()
244 struct nand_device *nand = spinand_to_nand(spinand); in spinand_read_cfg() local
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| /linux/Documentation/devicetree/bindings/pinctrl/ |
| H A D | marvell,kirkwood-pinctrl.txt | 24 mpp0 0 gpio, nand(io2), spi(cs)
25 mpp1 1 gpo, nand(io3), spi(mosi)
26 mpp2 2 gpo, nand(io4), spi(sck)
27 mpp3 3 gpo, nand(io5), spi(miso)
28 mpp4 4 gpio, nand(io6), uart0(rxd), ptp(clk)
29 mpp5 5 gpo, nand(io7), uart0(txd), ptp(trig)
45 mpp18 18 gpo, nand(io0)
46 mpp19 19 gpo, nand(io1)
62 mpp0 0 gpio, nand(io2), spi(cs)
63 mpp1 1 gpo, nand(io3), spi(mosi)
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| H A D | lantiq,pinctrl-xway.txt | 56 ebu wait, nand ale, nand cs1, nand cle, spi_di, spi_do, spi_clk, spi_cs1,
67 ebu cs1, ebu wait, nand ale, nand cs1, nand cle, nand rdy, nand rd,
79 ebu cs1, ebu wait, nand ale, nand cs1, nand cle, nand rdy, nand rd,
93 exin0, exin1, exin2, exin4, nand ale, nand cs0, nand cs1, nand cle,
94 nand rdy, nand rd, nand_d0, nand_d1, nand_d2, nand_d3, nand_d4, nand_d5,
95 nand_d6, nand_d7, nand_d1, nand wr, nand wp, nand se, spi_di, spi_do,
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| /linux/drivers/mtd/nand/raw/brcmnand/ |
| H A D | Kconfig | 2 tristate "Broadcom STB NAND controller"
6 Enables the Broadcom NAND controller driver. The controller was
13 tristate "Broadcom BCM63xx NAND controller glue"
16 Enables the BRCMNAND glue driver to register the NAND controller
20 tristate "Broadcom BCMA NAND controller"
29 tristate "Broadcom BCMBCA NAND controller glue"
32 Enables the BRCMNAND glue driver to register the NAND controller
36 tristate "Broadcom STB Nand controller glue"
39 Enables the BRCMNAND glue driver to register the NAND controller
43 tristate "Broadcom iProc NAND controller glue"
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| /linux/include/linux/mtd/ |
| H A D | spinand.h | 15 #include <linux/mtd/nand.h>
20 * Standard SPI NAND flash operations
242 * Octal DDR SPI NAND flash operations
366 * struct spinand_id - SPI NAND id structure
383 * struct spinand_devid - SPI NAND device id structure
402 * struct manufacurer_ops - SPI NAND manufacturer specific operations
403 * @init: initialize a SPI NAND device
404 * @cleanup: cleanup a SPI NAND device
406 * Each SPI NAND manufacturer driver should implement this interface so that
407 * NAND chips coming from this vendor can be initialized properly.
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| H A D | nand-ecc-sw-bch.h | 5 * This file is the header for the NAND BCH ECC implementation.
11 #include <linux/mtd/nand.h>
37 int nand_ecc_sw_bch_calculate(struct nand_device *nand,
39 int nand_ecc_sw_bch_correct(struct nand_device *nand, unsigned char *buf,
41 int nand_ecc_sw_bch_init_ctx(struct nand_device *nand);
42 void nand_ecc_sw_bch_cleanup_ctx(struct nand_device *nand);
47 static inline int nand_ecc_sw_bch_calculate(struct nand_device *nand, in nand_ecc_sw_bch_calculate() argument
54 static inline int nand_ecc_sw_bch_correct(struct nand_device *nand, in nand_ecc_sw_bch_correct() argument
62 static inline int nand_ecc_sw_bch_init_ctx(struct nand_device *nand) in nand_ecc_sw_bch_init_ctx() argument
67 static inline void nand_ecc_sw_bch_cleanup_ctx(struct nand_device *nand) {} in nand_ecc_sw_bch_cleanup_ctx() argument
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| H A D | rawnand.h | 8 * Contains standard defines and IDs for NAND flash devices
17 #include <linux/mtd/nand.h>
29 /* The maximum number of NAND chips in an array */
50 * Standard NAND flash commands
97 * Enable generic NAND 'page erased' check. This check is only done when
133 /* Device is one of 'new' xD cards that expose fake nand command set */
136 /* Device behaves just like nand, but is readonly */
160 * Autodetect nand buswidth with readid/onfi.
184 * Whether the NAND chip is a boot medium. Drivers might use this information
225 * struct nand_parameters - NAND generic parameters from the parameter page
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| H A D | nand-ecc-sw-hamming.h | 7 * This file is the header for the NAND Hamming ECC implementation.
13 #include <linux/mtd/nand.h>
34 int nand_ecc_sw_hamming_init_ctx(struct nand_device *nand);
35 void nand_ecc_sw_hamming_cleanup_ctx(struct nand_device *nand);
38 int nand_ecc_sw_hamming_calculate(struct nand_device *nand,
44 int nand_ecc_sw_hamming_correct(struct nand_device *nand, unsigned char *buf,
50 static inline int nand_ecc_sw_hamming_init_ctx(struct nand_device *nand) in nand_ecc_sw_hamming_init_ctx() argument
55 static inline void nand_ecc_sw_hamming_cleanup_ctx(struct nand_device *nand) {} in nand_ecc_sw_hamming_cleanup_ctx() argument
64 static inline int nand_ecc_sw_hamming_calculate(struct nand_device *nand, in nand_ecc_sw_hamming_calculate() argument
79 static inline int nand_ecc_sw_hamming_correct(struct nand_device *nand, in nand_ecc_sw_hamming_correct() argument
|