/freebsd/sys/contrib/device-tree/Bindings/mtd/ |
H A D | gpmi-nand.txt | 1 * Freescale General-Purpose Media Interface (GPMI) 3 The GPMI nand controller provides an interface to control the 4 NAND flash chips. 7 - compatible : should be "fsl,<chip>-gpmi-nand", chip can be: 13 - reg : should contain registers location and length for gpmi and bch. 14 - reg-names: Should contain the reg names "gpmi-nand" and "bch" 15 - interrupts : BCH interrupt number. 16 - interrupt-names : Should be "bch". 17 - dmas: DMA specifier, consisting of a phandle to DMA controller node 19 Refer to dma.txt and fsl-mxs-dma.txt for details. [all …]
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H A D | brcm,brcmnand.txt | 1 * Broadcom STB NAND Controller 3 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND 4 flash chips. It has a memory-mapped register interface for both control 5 registers and for its data input/output buffer. On some SoCs, this controller is 6 paired with a custom DMA engine (inventively named "Flash DMA") which supports 10 available on a variety of Broadcom SoCs, including some BCM3xxx, BCM63xx, and 15 - compatible : May contain an SoC-specific compatibility string (see below) 16 to account for any SoC-specific hardware bits that may be 17 added on top of the base core controller. 19 the core NAND controller, of the following form: [all …]
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H A D | davinci-nand.txt | 1 Device tree bindings for Texas instruments Davinci/Keystone NAND controller 4 NAND interface contains. 7 Davinci DM646x - https://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf 8 Kestone - https://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf 12 - compatible: "ti,davinci-nand" 13 "ti,keystone-nand" 15 - reg: Contains 2 offset/length values: 16 - offset and length for the access window. 17 - offset and length for accessing the AEMIF 20 - ti,davinci-chipselect: number of chipselect. Indicates on the [all …]
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H A D | samsung-s3c2410.txt | 1 * Samsung S3C2410 and compatible NAND flash controller 4 - compatible : The possible values are: 5 "samsung,s3c2410-nand" 6 "samsung,s3c2412-nand" 7 "samsung,s3c2440-nand" 8 - reg : register's location and length. 9 - #address-cells, #size-cells : see nand-controller.yaml 10 - clocks : phandle to the nand controller clock 11 - clock-names : must contain "nand" 14 Child nodes representing the available nand chips. [all …]
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H A D | atmel-nand.txt | 1 Atmel NAND flash controller bindings 3 The NAND flash controller node should be defined under the EBI bus (see 4 Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt). 5 One or several NAND devices can be defined under this NAND controller. 6 The NAND controller might be connected to an ECC engine. 8 * NAND controller bindings: 11 - compatible: should be one of the following 12 "atmel,at91rm9200-nand-controller" 13 "atmel,at91sam9260-nand-controller" 14 "atmel,at91sam9261-nand-controller" [all …]
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H A D | vf610-nfc.txt | 1 Freescale's NAND flash controller (NFC) 3 This variant of the Freescale NAND flash controller (NFC) can be found on 7 - compatible: Should be set to "fsl,vf610-nfc". 8 - reg: address range of the NFC. 9 - interrupts: interrupt of the NFC. 10 - #address-cells: shall be set to 1. Encode the nand CS. 11 - #size-cells : shall be set to 0. 12 - assigned-clocks: main clock from the SoC, for Vybrid <&clks VF610_CLK_NFC>; 13 - assigned-clock-rates: The NAND bus timing is derived from this clock 14 rate and should not exceed maximum timing for any NAND memory chip [all …]
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H A D | mtk-nand.txt | 1 MTK SoCs NAND FLASH controller (NFC) DT binding 3 This file documents the device tree bindings for MTK SoCs NAND controllers. 5 the nand controller interface driver and the ECC engine driver. 10 1) NFC NAND Controller Interface (NFI): 13 The first part of NFC is NAND Controller Interface (NFI) HW. 15 - compatible: Should be one of 16 "mediatek,mt2701-nfc", 17 "mediatek,mt2712-nfc", 18 "mediatek,mt7622-nfc". 19 - reg: Base physical address and size of NFI. [all …]
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H A D | nvidia-tegra20-nand.txt | 1 NVIDIA Tegra NAND Flash controller 4 - compatible: Must be one of: 5 - "nvidia,tegra20-nand" 6 - reg: MMIO address range 7 - interrupts: interrupt output of the NFC controller 8 - clocks: Must contain an entry for each entry in clock-names. 9 See ../clocks/clock-bindings.txt for details. 10 - clock-names: Must include the following entries: 11 - nand 12 - resets: Must contain an entry for each entry in reset-names. [all …]
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H A D | lpc32xx-slc.txt | 1 NXP LPC32xx SoC NAND SLC controller 4 - compatible: "nxp,lpc3220-slc" 5 - reg: Address and size of the controller 6 - nand-on-flash-bbt: Use bad block table on flash 7 - gpios: GPIO specification for NAND write protect 11 - nxp,wdr-clks: Delay before Ready signal is tested on write (W_RDY) 12 - nxp,rdr-clks: Delay before Ready signal is tested on read (R_RDY) 15 - nxp,wwidth: Write pulse width (W_WIDTH) 16 - nxp,whold: Write hold time (W_HOLD) 17 - nxp,wsetup: Write setup time (W_SETUP) [all …]
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H A D | gpmi-nand.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/mtd/gpmi-nand.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Freescale General-Purpose Media Interface (GPMI) 10 - Han Xu <han.xu@nxp.com> 13 The GPMI nand controller provides an interface to control the NAND 14 flash chips. The device tree may optionally contain sub-nodes 21 - enum: 22 - fsl,imx23-gpmi-nand [all …]
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H A D | marvell-nand.txt | 1 Marvell NAND Flash Controller (NFC) 4 - compatible: can be one of the following: 5 * "marvell,armada-8k-nand-controller" 6 * "marvell,armada370-nand-controller" 7 * "marvell,pxa3xx-nand-controller" 8 * "marvell,armada-8k-nand" (deprecated) 9 * "marvell,armada370-nand" (deprecated) 10 * "marvell,pxa3xx-nand" (deprecated) 13 - reg: NAND flash controller memory area. 14 - #address-cells: shall be set to 1. Encode the NAND CS. [all …]
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H A D | raw-nand-chip.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/mtd/raw-nand-chip.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Raw NAND Chip Common Properties 10 - Miquel Raynal <miquel.raynal@bootlin.com> 13 - $ref: nand-chip.yaml# 19 {size} bytes for a particular raw NAND chip. 21 The interpretation of these parameters is implementation-defined, so 28 pattern: "^nand@[a-f0-9]$" [all …]
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H A D | brcm,brcmnand.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Broadcom STB NAND Controller 10 - Brian Norris <computersforpeace@gmail.com> 11 - Kamal Dasu <kdasu.kdev@gmail.com> 12 - William Zhang <william.zhang@broadcom.com> 15 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND 16 flash chips. It has a memory-mapped register interface for both control 17 registers and for its data input/output buffer. On some SoCs, this controller [all …]
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H A D | amlogic,meson-nand.txt | 1 Amlogic NAND Flash Controller (NFC) for GXBB/GXL/AXG family SoCs 4 the MTD NAND bindings. 7 - compatible : contains one of: 8 - "amlogic,meson-gxl-nfc" 9 - "amlogic,meson-axg-nfc" 10 - clocks : 11 A list of phandle + clock-specifier pairs for the clocks listed 12 in clock-names. 14 - clock-names: Should contain the following: 15 "core" - NFC module gate clock [all …]
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H A D | mxc-nand.txt | 4 - compatible: "fsl,imxXX-nand" 5 - reg: address range of the nfc block 6 - interrupts: irq to be used 7 - nand-bus-width: see nand-controller.yaml 8 - nand-ecc-mode: see nand-controller.yaml 9 - nand-on-flash-bbt: see nand-controller.yaml 13 nand@d8000000 { 14 compatible = "fsl,imx27-nand"; 17 nand-bus-width = <8>; 18 nand-ecc-mode = "hw";
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/freebsd/sys/contrib/device-tree/src/mips/brcm/ |
H A D | bcm97xxx-nand-cs1-bch24.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 2 &nand { 6 nand-on-flash-bbt; 8 nand-ecc-strength = <24>; 9 nand-ecc-step-size = <1024>; 10 brcm,nand-oob-sector-size = <27>; 13 compatible = "fixed-partitions"; 14 #address-cells = <1>; 15 #size-cells = <1>;
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H A D | bcm97xxx-nand-cs1-bch4.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 2 &nand { 6 nand-on-flash-bbt; 8 nand-ecc-strength = <4>; 9 nand-ecc-step-size = <512>; 10 brcm,nand-oob-sector-size = <16>; 13 compatible = "fixed-partitions"; 14 #address-cells = <1>; 15 #size-cells = <1>;
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/freebsd/sys/contrib/device-tree/src/arm/marvell/ |
H A D | armada-385-atl-x530.dts | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 4 (x530/AT-GS980MX) 9 /dts-v1/; 10 #include "armada-385.dtsi" 12 #include <dt-bindings/gpio/gpio.h> 15 model = "x530/AT-GS980MX"; 19 stdout-path = "serial1:115200n8"; 32 internal-regs { 34 pinctrl-names = "default"; 35 pinctrl-0 = <&i2c0_pins>; [all …]
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H A D | armada-xp-db-xc3-24g4xg.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 * Device Tree file for DB-XC3-24G4XG board 7 * Based on armada-xp-db.dts 12 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier 19 /dts-v1/; 20 #include "armada-xp-98dx3336.dtsi" 23 model = "DB-XC3-24G4XG"; 24 compatible = "marvell,db-xc3-24g4xg", "marvell,armadaxp-98dx3336", "marvell,armada-370-xp"; 37 arm,parity-enable; 38 marvell,ecc-enable; [all …]
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H A D | armada-xp-db-dxbc2.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 * Device Tree file for DB-DXBC2 board 7 * Based on armada-xp-db.dts 12 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier 19 /dts-v1/; 20 #include "armada-xp-98dx4251.dtsi" 24 compatible = "marvell,db-dxbc2", "marvell,armadaxp-98dx4251", "marvell,armada-370-xp"; 43 devbus,bus-width = <16>; 44 devbus,turn-off-ps = <60000>; 45 devbus,badr-skew-ps = <0>; [all …]
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H A D | armada-398-db.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 10 /dts-v1/; 11 #include "armada-398.dtsi" 15 compatible = "marvell,a398-db", "marvell,armada398", "marvell,armada390"; 18 stdout-path = "serial0:115200n8"; 30 internal-regs { 32 pinctrl-0 = <&i2c0_pins>; 33 pinctrl-names = "default"; 35 clock-frequency = <100000>; [all …]
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H A D | armada-390-db.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 4 * (DB-88F6920) 11 /dts-v1/; 12 #include "armada-390.dtsi" 16 compatible = "marvell,a390-db", "marvell,armada390"; 19 stdout-path = "serial0:115200n8"; 31 internal-regs { 34 clock-frequency = <100000>; 81 pinctrl-0 = <&spi1_pins>; 82 pinctrl-names = "default"; [all …]
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/freebsd/sys/contrib/device-tree/src/arm/microchip/ |
H A D | sama5d3xcm.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later 3 * sama5d3xcm.dtsi - Device Tree Include file for SAMA5D3x CPU Module 14 stdout-path = "serial0:115200n8"; 23 clock-frequency = <32768>; 27 clock-frequency = <12000000>; 34 cs-gpios = <&pioD 13 0>, <0>, <0>, <0>; 39 compatible = "atmel,tcb-timer"; 44 compatible = "atmel,tcb-timer"; 51 pinctrl-0 = <&pinctrl_ebi_addr &pinctrl_ebi_cs0>; 52 pinctr-name = "default"; [all …]
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/freebsd/sys/contrib/device-tree/src/arm/broadcom/ |
H A D | bcm963138dvt.dts | 1 // SPDX-License-Identifier: GPL-2.0 6 /dts-v1/; 16 stdout-path = &serial0; 35 brcm,wp-not-connected; 40 nand-ecc-strength = <4>; 41 nand-ecc-step-size = <512>; 42 brcm,nand-oob-sector-size = <16>; 43 nand-on-flash-bbt;
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H A D | bcm7445-bcm97445svmb.dts | 1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 20 nand@1 { 23 nand-ecc-step-size = <512>; 24 nand-ecc-strength = <8>; 25 nand-on-flash-bbt; 27 #size-cells = <2>; 28 #address-cells = <2>;
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