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/linux/drivers/mtd/nand/
H A Decc.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Generic Error-Correcting Code (ECC) engine
10 * This file describes the abstraction of any NAND ECC engine. It has been
11 * designed to fit most cases, including parallel NANDs and SPI-NANDs.
13 * There are three main situations where instantiating this ECC engine makes
15 * - external: The ECC engine is outside the NAND pipeline, typically this
16 * is a software ECC engine, or an hardware engine that is
17 * outside the NAND controller pipeline.
18 * - pipelined: The ECC engine is inside the NAND pipeline, ie. on the
19 * controller's side. This is the case of most of the raw NAND
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H A Decc-sw-bch.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * This file provides ECC correction for more than 1 bit per block of data,
14 #include <linux/mtd/nand.h>
15 #include <linux/mtd/nand-ecc-sw-bch.h>
18 * nand_ecc_sw_bch_calculate - Calculate the ECC corresponding to a data block
19 * @nand: NAND device
21 * @code: Output buffer with ECC
23 int nand_ecc_sw_bch_calculate(struct nand_device *nand, in nand_ecc_sw_bch_calculate() argument
26 struct nand_ecc_sw_bch_conf *engine_conf = nand->ecc.ctx.priv; in nand_ecc_sw_bch_calculate()
29 memset(code, 0, engine_conf->code_size); in nand_ecc_sw_bch_calculate()
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/linux/Documentation/devicetree/bindings/mtd/
H A Dnvidia-tegra20-nand.txt1 NVIDIA Tegra NAND Flash controller
4 - compatible: Must be one of:
5 - "nvidia,tegra20-nand"
6 - reg: MMIO address range
7 - interrupts: interrupt output of the NFC controller
8 - clocks: Must contain an entry for each entry in clock-names.
9 See ../clocks/clock-bindings.txt for details.
10 - clock-names: Must include the following entries:
11 - nand
12 - resets: Must contain an entry for each entry in reset-names.
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H A Dnand-chip.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/nand-chip.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NAND Chip Common Properties
10 - Miquel Raynal <miquel.raynal@bootlin.com>
13 - $ref: mtd.yaml#
16 This file covers the generic description of a NAND chip. It implies that the
17 bus interface should not be taken into account: both raw NAND devices and
18 SPI-NAND devices are concerned by this description.
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H A Dmxic-nand.txt1 Macronix Raw NAND Controller Device Tree Bindings
2 -------------------------------------------------
5 - compatible: should be "mxic,multi-itfc-v009-nand-controller"
6 - reg: should contain 1 entry for the registers
7 - #address-cells: should be set to 1
8 - #size-cells: should be set to 0
9 - interrupts: interrupt line connected to this raw NAND controller
10 - clock-names: should contain "ps", "send" and "send_dly"
11 - clocks: should contain 3 phandles for the "ps", "send" and
15 - children nodes represent the available NAND chips.
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H A Dallwinner,sun4i-a10-nand.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mtd/allwinner,sun4i-a10-nand.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 NAND Controller
10 - $ref: nand-controller.yaml
13 - Chen-Yu Tsai <wens@csie.org>
14 - Maxime Ripard <mripard@kernel.org>
19 - allwinner,sun4i-a10-nand
20 - allwinner,sun8i-a23-nand-controller
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H A Dintel,lgm-ebunand.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/intel,lgm-ebunand.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Intel LGM SoC NAND Controller
10 - $ref: nand-controller.yaml
13 - Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
17 const: intel,lgm-ebunand
22 reg-names:
24 - const: ebunand
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H A Dbrcm,brcmnand.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom STB NAND Controller
10 - Brian Norris <computersforpeace@gmail.com>
11 - Kamal Dasu <kdasu.kdev@gmail.com>
12 - William Zhang <william.zhang@broadcom.com>
15 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
16 flash chips. It has a memory-mapped register interface for both control
27 -- Additional SoC-specific NAND controller properties --
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/linux/drivers/mtd/nand/raw/
H A Dtegra_nand.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2014-2015 Lucas Stach <dev@lynxeye.de>
10 #include <linux/dma-mapping.h>
34 #define COMMAND_TRANS_SIZE(size) ((((size) - 1) & 0xf) << 20)
40 #define COMMAND_CLE_SIZE(size) ((((size) - 1) & 0x3) << 4)
41 #define COMMAND_ALE_SIZE(size) ((((size) - 1) & 0xf) << 0)
156 #define OFFSET(val, off) ((val) < (off) ? 0 : (val) - (off))
185 struct mtd_oob_region ecc; member
207 int bytes_per_step = DIV_ROUND_UP(BITS_PER_STEP_RS * chip->ecc.strength, in tegra_nand_ooblayout_rs_ecc()
211 return -ERANGE; in tegra_nand_ooblayout_rs_ecc()
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H A Dtechnologic-nand-controller.c1 // SPDX-License-Identifier: GPL-2.0
3 * Technologic Systems TS72xx NAND controller driver
47 switch (chip->ecc.engine_type) { in ts72xx_nand_attach_chip()
49 return -EINVAL; in ts72xx_nand_attach_chip()
51 if (chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN) in ts72xx_nand_attach_chip()
52 chip->ecc.algo = NAND_ECC_ALGO_HAMMING; in ts72xx_nand_attach_chip()
53 chip->ecc.algo = NAND_ECC_ALGO_HAMMING; in ts72xx_nand_attach_chip()
63 unsigned char bits = ioread8(data->ctrl) & ~GENMASK(2, 0); in ts72xx_nand_ctrl()
65 iowrite8(bits | value, data->ctrl); in ts72xx_nand_ctrl()
76 switch (instr->type) { in ts72xx_nand_exec_instr()
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H A Dplat_nand.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Generic NAND driver
24 if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_SOFT && in plat_nand_attach_chip()
25 chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN) in plat_nand_attach_chip()
26 chip->ecc.algo = NAND_ECC_ALGO_HAMMING; in plat_nand_attach_chip()
36 * Probe for the NAND device.
40 struct platform_nand_data *pdata = dev_get_platdata(&pdev->dev); in plat_nand_probe()
47 dev_err(&pdev->dev, "platform_nand_data is missing\n"); in plat_nand_probe()
48 return -EINVAL; in plat_nand_probe()
51 if (pdata->chip.nr_chips < 1) { in plat_nand_probe()
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H A Dsocrates_nand.c1 // SPDX-License-Identifier: GPL-2.0-only
33 * socrates_nand_write_buf - write buffer to chip
34 * @this: NAND chip object
45 out_be32(host->io_base, FPGA_NAND_ENABLE | in socrates_nand_write_buf()
52 * socrates_nand_read_buf - read chip data into buffer
53 * @this: NAND chip object
66 out_be32(host->io_base, val); in socrates_nand_read_buf()
68 buf[i] = (in_be32(host->io_base) >> in socrates_nand_read_buf()
74 * socrates_nand_read_byte - read one byte from the chip
85 * Hardware specific access to control-lines
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H A Dxway_nand.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright © 2016 Hauke Mehrtens <hauke@hauke-m.de>
14 /* nand registers */
18 #define NAND_WAIT_RD BIT(0) /* NAND flash status output */
19 #define NAND_WAIT_WR_C BIT(3) /* NAND Write/Read complete */
24 * nand commands
25 * The pins of the NAND chip are selected based on the address bits of the
41 /* we need to tel the ebu which addr we mapped the nand to */
45 /* we need to tell the EBU that we have nand attached and set it up properly */
76 return readb(data->nandaddr + op); in xway_readb()
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H A Dpasemi_nand.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2006-2007 PA Semi, Inc
8 * Driver for the PWRficient onchip NAND flash interface
35 static const char driver_name[] = "pasemi-nand";
40 memcpy_fromio(buf, chip->legacy.IO_ADDR_R, 0x800); in pasemi_read_buf()
42 len -= 0x800; in pasemi_read_buf()
44 memcpy_fromio(buf, chip->legacy.IO_ADDR_R, len); in pasemi_read_buf()
51 memcpy_toio(chip->legacy.IO_ADDR_R, buf, 0x800); in pasemi_write_buf()
53 len -= 0x800; in pasemi_write_buf()
55 memcpy_toio(chip->legacy.IO_ADDR_R, buf, len); in pasemi_write_buf()
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H A Ddavinci_nand.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * davinci_nand.c - NAND Flash Driver for DaVinci family chips
8 * Sander Huijsen <Shuijsen@optelecom-nkf.com>
28 /* 4-bit ECC syndrome registers */
40 * for ALE/CLE unless they support booting from NAND.
51 * 0-indexed chip-select number of the asynchronous
52 * interface to which the NAND device has been connected.
54 * So, if you have NAND connected to CS3 of DA850, you
71 * All DaVinci-family chips support 1-bit hardware ECC.
72 * Newer ones also support 4-bit ECC, but are awkward
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H A Dorion_nand.c2 * NAND support for Marvell Orion SoC platforms
22 #include <linux/platform_data/mtd-orion_nand.h>
40 offs = (1 << board->cle); in orion_nand_cmd_ctrl()
42 offs = (1 << board->ale); in orion_nand_cmd_ctrl()
46 if (nc->options & NAND_BUSWIDTH_16) in orion_nand_cmd_ctrl()
49 writeb(cmd, nc->legacy.IO_ADDR_W + offs); in orion_nand_cmd_ctrl()
54 void __iomem *io_base = chip->legacy.IO_ADDR_R; in orion_nand_read_buf()
62 len--; in orion_nand_read_buf()
88 if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_SOFT && in orion_nand_attach_chip()
89 chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN) in orion_nand_attach_chip()
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H A Dau1550nd.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <asm/mach-au1x00/au1000.h>
16 #include <asm/mach-au1x00/au1550nd.h>
33 * au_write_buf - write buffer to chip
34 * @this: NAND chip object
48 writeb(p[i], ctx->base + MEM_STNAND_DATA); in au_write_buf()
54 * au_read_buf - read chip data into buffer
55 * @this: NAND chip object
69 p[i] = readb(ctx->base + MEM_STNAND_DATA); in au_read_buf()
75 * au_write_buf16 - write buffer to chip
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H A Dgpio.c1 // SPDX-License-Identifier: GPL-2.0-only
10 * Device driver for NAND flash that uses a memory mapped interface to
11 * read/write the NAND commands and data, and GPIO pins for control signals
12 * (the DT binding refers to this as "GPIO assisted NAND flash")
25 #include <linux/mtd/nand-gpio.h>
52 * Make sure the GPIO state changes occur in-order with writes to NAND
54 * Needed on PXA due to bus-reordering within the SoC itself (see section on
61 if (gpiomtd->io_sync) { in gpio_nand_dosync()
64 * What's required is what's here - a read from a separate in gpio_nand_dosync()
67 tmp = readl(gpiomtd->io_sync); in gpio_nand_dosync()
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H A Dnand_base.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * This is the generic MTD driver for NAND flash devices. It should be
5 * capable of working with almost all NAND chips currently available.
8 * http://www.linux-mtd.infradead.org/doc/nand.html
11 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
21 * Check, if mtd->ecctype should be set to MTD_ECC_HW
22 * if we have HW ECC support.
37 #include <linux/mtd/nand.h>
38 #include <linux/mtd/nand-ecc-sw-hamming.h>
39 #include <linux/mtd/nand-ecc-sw-bch.h>
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H A Dams-delta.c1 // SPDX-License-Identifier: GPL-2.0
5 * Derived from drivers/mtd/nand/toto.c (removed in v2.6.28)
13 * This is a device driver for the NAND flash device found on the
22 #include <linux/mtd/nand-gpio.h>
52 gpiod_set_value(priv->gpiod_nwe, 1); in gpio_nand_write_commit()
53 ndelay(priv->tWP); in gpio_nand_write_commit()
54 gpiod_set_value(priv->gpiod_nwe, 0); in gpio_nand_write_commit()
59 struct gpio_descs *data_gpiods = priv->data_gpiods; in gpio_nand_io_write()
62 gpiod_set_raw_array_value(data_gpiods->ndescs, data_gpiods->desc, in gpio_nand_io_write()
63 data_gpiods->info, values); in gpio_nand_io_write()
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/linux/arch/arm/boot/dts/broadcom/
H A Dbcm5301x-nand-cs0-bch8.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 * Broadcom BCM470X / BCM5301X Nand chip defaults.
5 * This should be included if the NAND controller is on chip select 0
6 * and uses 8 bit ECC.
8 * Copyright (C) 2015 Hauke Mehrtens <hauke@hauke-m.de>
11 #include "bcm5301x-nand-cs0.dtsi"
14 nand-ecc-algo = "bch";
15 nand-ecc-strength = <8>;
16 nand-ecc-step-size = <512>;
H A Dbcm5301x-nand-cs0-bch1.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 * Broadcom Northstar NAND.
8 #include "bcm5301x-nand-cs0.dtsi"
11 nand-ecc-algo = "bch";
12 nand-ecc-strength = <1>;
13 nand-ecc-step-size = <512>;
H A Dbcm5301x-nand-cs0-bch4.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
6 #include "bcm5301x-nand-cs0.dtsi"
9 nand-ecc-algo = "bch";
10 nand-ecc-strength = <4>;
11 nand-ecc-step-size = <512>;
/linux/arch/arm64/boot/dts/xilinx/
H A Dzynqmp-zc1751-xm016-dc2.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm016-dc2
5 * (C) Copyright 2015 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
19 model = "ZynqMP zc1751-xm016-dc2 RevA";
20 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
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/linux/include/linux/mtd/
H A Dnand.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright 2017 - Free Electrons
6 * Boris Brezillon <boris.brezillon@free-electrons.com>
18 * struct nand_memory_organization - Memory organization structure
19 * @bits_per_cell: number of bits per NAND cell
27 * @ntargets: total number of targets exposed by the NAND device
55 * struct nand_row_converter - Information needed to convert an absolute offset
67 * struct nand_pos - NAND position object
68 * @target: the NAND target/die
74 * These information are usually used by specific sub-layers to select the
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