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/linux/drivers/gpu/drm/msm/registers/adreno/
H A Da2xx.xml10 <enum name="a2xx_rb_dither_type">
11 <value name="DITHER_PIXEL" value="0"/>
12 <value name="DITHER_SUBPIXEL" value="1"/>
15 <enum name="a2xx_colorformatx">
16 <value name="COLORX_4_4_4_4" value="0"/>
17 <value name="COLORX_1_5_5_5" value="1"/>
18 <value name="COLORX_5_6_5" value="2"/>
19 <value name="COLORX_8" value="3"/>
20 <value name="COLORX_8_8" value="4"/>
21 <value name="COLORX_8_8_8_8" value="5"/>
[all …]
H A Da5xx.xml9 <enum name="a5xx_color_fmt">
10 <value value="0x02" name="RB5_A8_UNORM"/>
11 <value value="0x03" name="RB5_R8_UNORM"/>
12 <value value="0x04" name="RB5_R8_SNORM"/>
13 <value value="0x05" name="RB5_R8_UINT"/>
14 <value value="0x06" name="RB5_R8_SINT"/>
15 <value value="0x08" name="RB5_R4G4B4A4_UNORM"/>
16 <value value="0x0a" name="RB5_R5G5B5A1_UNORM"/>
17 <value value="0x0e" name="RB5_R5G6B5_UNORM"/>
18 <value value="0x0f" name="RB5_R8G8_UNORM"/>
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H A Da4xx.xml9 <enum name="a4xx_color_fmt">
10 <value name="RB4_A8_UNORM" value="0x01"/>
11 <value name="RB4_R8_UNORM" value="0x02"/>
12 <value name="RB4_R8_SNORM" value="0x03"/>
13 <value name="RB4_R8_UINT" value="0x04"/>
14 <value name="RB4_R8_SINT" value="0x05"/>
16 <value name="RB4_R4G4B4A4_UNORM" value="0x08"/>
17 <value name="RB4_R5G5B5A1_UNORM" value="0x0a"/>
18 <value name="RB4_R5G6B5_UNORM" value="0x0e"/>
19 <value name="RB4_R8G8_UNORM" value="0x0f"/>
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H A Da8xx_enums.xml9 <enum name="a8xx_statetype_id">
10 <value value="0" name="A8XX_TP0_NCTX_REG"/>
11 <value value="1" name="A8XX_TP0_CTX0_3D_CVS_REG"/>
12 <value value="2" name="A8XX_TP0_CTX0_3D_CPS_REG"/>
13 <value value="3" name="A8XX_TP0_CTX1_3D_CVS_REG"/>
14 <value value="4" name="A8XX_TP0_CTX1_3D_CPS_REG"/>
15 <value value="5" name="A8XX_TP0_CTX2_3D_CPS_REG"/>
16 <value value="6" name="A8XX_TP0_CTX3_3D_CPS_REG"/>
17 <value value="9" name="A8XX_TP0_TMO_DATA"/>
18 <value value="10" name="A8XX_TP0_SMO_DATA"/>
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H A Da3xx.xml9 <enum name="a3xx_tile_mode">
10 <value name="LINEAR" value="0"/>
11 <value name="TILE_4X4" value="1"/> <!-- "normal" case for textures -->
12 <value name="TILE_32X32" value="2"/> <!-- only used in GMEM -->
13 <value name="TILE_4X2" value="3"/> <!-- only used for CrCb -->
16 <enum name="a3xx_state_block_id">
17 <value name="HLSQ_BLOCK_ID_TP_TEX" value="2"/>
18 <value name="HLSQ_BLOCK_ID_TP_MIPMAP" value="3"/>
19 <value name="HLSQ_BLOCK_ID_SP_VS" value="4"/>
20 <value name="HLSQ_BLOCK_ID_SP_FS" value="6"/>
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H A Dadreno_common.xml7 <enum name="chip" bare="yes">
8 <value name="A2XX" value="2"/>
9 <value name="A3XX" value="3"/>
10 <value name="A4XX" value="4"/>
11 <value name="A5XX" value="5"/>
12 <value name="A6XX" value="6"/>
13 <value name="A7XX" value="7"/>
14 <value name="A8XX" value="8"/>
17 <enum name="adreno_pa_su_sc_draw">
18 <value name="PC_DRAW_POINTS" value="0"/>
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H A Da6xx_enums.xml9 <enum name="a6xx_tile_mode">
10 <value name="TILE6_LINEAR" value="0"/>
11 <value name="TILE6_2" value="2"/>
12 <value name="TILE6_3" value="3"/>
15 <enum name="a6xx_format">
16 <value value="0x02" name="FMT6_A8_UNORM"/>
17 <value value="0x03" name="FMT6_8_UNORM"/>
18 <value value="0x04" name="FMT6_8_SNORM"/>
19 <value value="0x05" name="FMT6_8_UINT"/>
20 <value value="0x06" name="FMT6_8_SINT"/>
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H A Da7xx_enums.xml9 <enum name="a7xx_statetype_id">
10 <value value="0" name="A7XX_TP0_NCTX_REG"/>
11 <value value="1" name="A7XX_TP0_CTX0_3D_CVS_REG"/>
12 <value value="2" name="A7XX_TP0_CTX0_3D_CPS_REG"/>
13 <value value="3" name="A7XX_TP0_CTX1_3D_CVS_REG"/>
14 <value value="4" name="A7XX_TP0_CTX1_3D_CPS_REG"/>
15 <value value="5" name="A7XX_TP0_CTX2_3D_CPS_REG"/>
16 <value value="6" name="A7XX_TP0_CTX3_3D_CPS_REG"/>
17 <value value="9" name="A7XX_TP0_TMO_DATA"/>
18 <value value="10" name="A7XX_TP0_SMO_DATA"/>
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H A Da6xx_gmu.xml8 <domain name="A6XX" width="32" prefix="variant" varset="chip">
10 <bitset name="A6XX_GMU_GPU_IDLE_STATUS">
11 <bitfield name="BUSY_IGN_AHB" pos="23"/>
12 <bitfield name="CX_GX_CPU_BUSY_IGN_AHB" pos="30"/>
15 <bitset name="A6XX_GMU_OOB">
16 <bitfield name="BOOT_SLUMBER_SET_MASK" pos="22"/>
17 <bitfield name="BOOT_SLUMBER_CHECK_MASK" pos="30"/>
18 <bitfield name="BOOT_SLUMBER_CLEAR_MASK" pos="30"/>
19 <bitfield name="DCVS_SET_MASK" pos="23"/>
20 <bitfield name="DCVS_CHECK_MASK" pos="31"/>
[all …]
H A Da6xx.xml30 <domain name="A6XX" width="32" prefix="variant" varset="chip">
31 <bitset name="A6XX_RBBM_INT_0_MASK" inline="no" varset="chip">
32 <bitfield name="RBBM_GPU_IDLE" pos="0" type="boolean"/>
33 <bitfield name="CP_AHB_ERROR" pos="1" type="boolean"/>
34 <bitfield name="CP_IPC_INTR_0" pos="4" type="boolean" variants="A7XX-"/>
35 <bitfield name="CP_IPC_INTR_1" pos="5" type="boolean" variants="A7XX-"/>
36 <bitfield name="RBBM_ATB_ASYNCFIFO_OVERFLOW" pos="6" type="boolean"/>
37 <bitfield name="RBBM_GPC_ERROR" pos="7" type="boolean"/>
38 <bitfield name="CP_SW" pos="8" type="boolean"/>
39 <bitfield name="CP_HW_ERROR" pos="9" type="boolean"/>
[all …]
H A Dadreno_pm4.xml8 <enum name="vgt_event_type" varset="chip">
9 <value name="VS_DEALLOC" value="0x00" variants="A2XX-A5XX"/>
10 <value name="PS_DEALLOC" value="0x01" variants="A2XX-A5XX"/>
11 <value name="VS_DONE_TS" value="0x02" variants="A2XX-A5XX"/>
12 <value name="PS_DONE_TS" value="0x03" variants="A2XX-A5XX"/>
17 <value name="CACHE_FLUSH_TS" value="0x04"/>
18 <value name="CONTEXT_DONE" value="0x05"/>
19 <value name="CACHE_FLUSH" value="0x06" variants="A2XX-A4XX"/>
20 <value name="VIZQUERY_START" value="0x07" variants="A2XX"/>
21 <value name="HLSQ_FLUSH" value="0x07" variants="A3XX-A4XX"/>
[all …]
/linux/drivers/gpu/drm/msm/registers/display/
H A Ddsi.xml7 <domain name="DSI" width="32">
8 <enum name="dsi_traffic_mode">
9 <value name="NON_BURST_SYNCH_PULSE" value="0"/>
10 <value name="NON_BURST_SYNCH_EVENT" value="1"/>
11 <value name="BURST_MODE" value="2"/>
13 <enum name="dsi_vid_dst_format">
14 <value name="VID_DST_FORMAT_RGB565" value="0"/>
15 <value name="VID_DST_FORMAT_RGB666" value="1"/>
16 <value name="VID_DST_FORMAT_RGB666_LOOSE" value="2"/>
17 <value name="VID_DST_FORMAT_RGB888" value="3"/>
[all …]
H A Dmdp4.xml8 <domain name="MDP4" width="32">
9 <enum name="mdp4_pipe">
11 <value name="VG1" value="0"/>
12 <value name="VG2" value="1"/>
13 <value name="RGB1" value="2"/>
14 <value name="RGB2" value="3"/>
15 <value name="RGB3" value="4"/>
16 <value name="VG3" value="5"/>
17 <value name="VG4" value="6"/>
20 <enum name="mdp4_mixer">
[all …]
H A Dedp.xml7 <domain name="EDP" width="32">
8 <enum name="edp_color_depth">
9 <value name="EDP_6BIT" value="0"/>
10 <value name="EDP_8BIT" value="1"/>
11 <value name="EDP_10BIT" value="2"/>
12 <value name="EDP_12BIT" value="3"/>
13 <value name="EDP_16BIT" value="4"/>
16 <enum name="edp_component_format">
17 <value name="EDP_RGB" value="0"/>
18 <value name="EDP_YUV422" value="1"/>
[all …]
H A Ddsi_phy_28nm.xml7 <domain name="DSI_28nm_PHY" width="32">
8 <array offset="0x00000" name="LN" length="4" stride="0x40">
9 <reg32 offset="0x00" name="CFG_0"/>
10 <reg32 offset="0x04" name="CFG_1"/>
11 <reg32 offset="0x08" name="CFG_2"/>
12 <reg32 offset="0x0c" name="CFG_3"/>
13 <reg32 offset="0x10" name="CFG_4"/>
14 <reg32 offset="0x14" name="TEST_DATAPATH"/>
15 <reg32 offset="0x18" name="DEBUG_SEL"/>
16 <reg32 offset="0x1c" name="TEST_STR_0"/>
[all …]
H A Ddsi_phy_14nm.xml7 <domain name="DSI_14nm_PHY_CMN" width="32">
8 <reg32 offset="0x00000" name="REVISION_ID0"/>
9 <reg32 offset="0x00004" name="REVISION_ID1"/>
10 <reg32 offset="0x00008" name="REVISION_ID2"/>
11 <reg32 offset="0x0000c" name="REVISION_ID3"/>
12 <reg32 offset="0x00010" name="CLK_CFG0">
13 <bitfield name="DIV_CTRL_3_0" low="4" high="7" type="uint"/>
14 <bitfield name="DIV_CTRL_7_4" low="4" high="7" type="uint"/>
16 <reg32 offset="0x00014" name="CLK_CFG1">
17 <bitfield name="DSICLK_SEL" pos="0" type="boolean"/>
[all …]
H A Ddsi_phy_28nm_8960.xml7 <domain name="DSI_28nm_8960_PHY" width="32">
9 <array offset="0x00000" name="LN" length="4" stride="0x40">
10 <reg32 offset="0x00" name="CFG_0"/>
11 <reg32 offset="0x04" name="CFG_1"/>
12 <reg32 offset="0x08" name="CFG_2"/>
13 <reg32 offset="0x0c" name="TEST_DATAPATH"/>
14 <reg32 offset="0x14" name="TEST_STR_0"/>
15 <reg32 offset="0x18" name="TEST_STR_1"/>
18 <reg32 offset="0x00100" name="LNCK_CFG_0"/>
19 <reg32 offset="0x00104" name="LNCK_CFG_1"/>
[all …]
H A Ddsi_phy_10nm.xml7 <domain name="DSI_10nm_PHY_CMN" width="32">
8 <reg32 offset="0x00000" name="REVISION_ID0"/>
9 <reg32 offset="0x00004" name="REVISION_ID1"/>
10 <reg32 offset="0x00008" name="REVISION_ID2"/>
11 <reg32 offset="0x0000c" name="REVISION_ID3"/>
12 <reg32 offset="0x00010" name="CLK_CFG0"/>
13 <reg32 offset="0x00014" name="CLK_CFG1"/>
14 <reg32 offset="0x00018" name="GLBL_CTRL"/>
15 <reg32 offset="0x0001c" name="RBUF_CTRL"/>
16 <reg32 offset="0x00020" name="VREG_CTRL"/>
[all …]
/linux/scripts/kconfig/
H A Dgconf.ui6 <property name="visible">True</property>
7 <property name="title" translatable="yes">Gtk Kernel Configurator</property>
8 <property name="type">GTK_WINDOW_TOPLEVEL</property>
9 <property name="window_position">GTK_WIN_POS_NONE</property>
10 <property name="modal">False</property>
11 <property name="default_width">640</property>
12 <property name="default_height">480</property>
13 <property name="resizable">True</property>
14 <property name="destroy_with_parent">False</property>
15 <property name="decorated">True</property>
[all …]
/linux/sound/soc/codecs/
H A Dcs48l32.h93 #define CS48L32_MIXER_CONTROLS(name, base) \ argument
94 SOC_SINGLE_RANGE_TLV(name " Input 1 Volume", base, \
97 SOC_SINGLE_RANGE_TLV(name " Input 2 Volume", base + 4, \
100 SOC_SINGLE_RANGE_TLV(name " Input 3 Volume", base + 8, \
103 SOC_SINGLE_RANGE_TLV(name " Input 4 Volume", base + 12, \
107 #define CS48L32_MUX_ENUM_DECL(name, reg) \ argument
109 name, reg, 0, CS48L32_MIXER_SRC_MASK, \
112 #define CS48L32_MUX_CTL_DECL(name) \ argument
113 const struct snd_kcontrol_new name##_mux = SOC_DAPM_ENUM("Route", name##_enum)
115 #define CS48L32_MUX_ENUMS(name, base_reg) \ argument
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/linux/drivers/scsi/lpfc/
H A Dlpfc_attr.h24 #define LPFC_ATTR(name, defval, minval, maxval, desc) \ argument
25 static uint lpfc_##name = defval;\
26 module_param(lpfc_##name, uint, S_IRUGO);\
27 MODULE_PARM_DESC(lpfc_##name, desc);\
28 lpfc_param_init(name, defval, minval, maxval)
30 #define LPFC_ATTR_R(name, defval, minval, maxval, desc) \ argument
31 static uint lpfc_##name = defval;\
32 module_param(lpfc_##name, uint, S_IRUGO);\
33 MODULE_PARM_DESC(lpfc_##name, desc);\
34 lpfc_param_show(name)\
[all …]
/linux/drivers/accel/habanalabs/include/gaudi/
H A Dgaudi_async_ids_map_extended.h20 char name[64]; member
24 { .fc_id = 0, .cpu_id = 0, .valid = 0, .name = "" },
25 { .fc_id = 1, .cpu_id = 1, .valid = 0, .name = "" },
26 { .fc_id = 2, .cpu_id = 2, .valid = 0, .name = "" },
27 { .fc_id = 3, .cpu_id = 3, .valid = 0, .name = "" },
28 { .fc_id = 4, .cpu_id = 4, .valid = 0, .name = "" },
29 { .fc_id = 5, .cpu_id = 5, .valid = 0, .name = "" },
30 { .fc_id = 6, .cpu_id = 6, .valid = 0, .name = "" },
31 { .fc_id = 7, .cpu_id = 7, .valid = 0, .name = "" },
32 { .fc_id = 8, .cpu_id = 8, .valid = 0, .name = "" },
[all …]
/linux/drivers/clk/bcm/
H A Dclk-bcm63xx-gate.c17 const char * const name; member
31 .name = "mac",
34 .name = "tc",
37 .name = "us_top",
40 .name = "ds_top",
43 .name = "acm",
46 .name = "spi",
49 .name = "usbs",
52 .name = "bmu",
55 .name = "pcm",
[all …]
/linux/fs/nilfs2/
H A Dsysfs.h53 #define NILFS_KOBJ_ATTR_STRUCT(name) \ argument
54 struct nilfs_##name##_attr { \
64 #define NILFS_DEV_ATTR_STRUCT(name) \ argument
65 struct nilfs_##name##_attr { \
67 ssize_t (*show)(struct nilfs_##name##_attr *, struct the_nilfs *, \
69 ssize_t (*store)(struct nilfs_##name##_attr *, struct the_nilfs *, \
80 #define NILFS_CP_ATTR_STRUCT(name) \ argument
81 struct nilfs_##name##_attr { \
83 ssize_t (*show)(struct nilfs_##name##_attr *, struct nilfs_root *, \
85 ssize_t (*store)(struct nilfs_##name##_attr *, struct nilfs_root *, \
[all …]
/linux/drivers/clk/imx/
H A Dclk.h95 struct clk_hw *imx_clk_fracn_gppll(const char *name, const char *parent_name, void __iomem *base,
97 struct clk_hw *imx_clk_fracn_gppll_integer(const char *name, const char *parent_name,
104 #define imx_clk_cpu(name, parent_name, div, mux, pll, step) \ argument
105 to_clk(imx_clk_hw_cpu(name, parent_name, div, mux, pll, step))
107 #define clk_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \ argument
109 to_clk(clk_hw_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \
112 #define imx_clk_pllv3(type, name, parent_name, base, div_mask) \ argument
113 to_clk(imx_clk_hw_pllv3(type, name, parent_name, base, div_mask))
115 #define imx_clk_pfd(name, parent_name, reg, idx) \ argument
116 to_clk(imx_clk_hw_pfd(name, parent_name, reg, idx))
[all …]

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