93 #define CS48L32_MIXER_CONTROLS(name, base) \  argument
94 	SOC_SINGLE_RANGE_TLV(name " Input 1 Volume", base,		\
97 	SOC_SINGLE_RANGE_TLV(name " Input 2 Volume", base + 4,		\
100 	SOC_SINGLE_RANGE_TLV(name " Input 3 Volume", base + 8,		\
103 	SOC_SINGLE_RANGE_TLV(name " Input 4 Volume", base + 12,		\
107 #define CS48L32_MUX_ENUM_DECL(name, reg) \  argument
109 		name, reg, 0, CS48L32_MIXER_SRC_MASK, \
112 #define CS48L32_MUX_CTL_DECL(name) \  argument
113 	const struct snd_kcontrol_new name##_mux = SOC_DAPM_ENUM("Route", name##_enum)
115 #define CS48L32_MUX_ENUMS(name, base_reg) \  argument
116 	static CS48L32_MUX_ENUM_DECL(name##_enum, base_reg);	\
117 	static CS48L32_MUX_CTL_DECL(name)
119 #define CS48L32_MIXER_ENUMS(name, base_reg) \  argument
120 	CS48L32_MUX_ENUMS(name##_in1, base_reg);     \
121 	CS48L32_MUX_ENUMS(name##_in2, base_reg + 4); \
122 	CS48L32_MUX_ENUMS(name##_in3, base_reg + 8); \
123 	CS48L32_MUX_ENUMS(name##_in4, base_reg + 12)
125 #define CS48L32_MUX(name, ctrl) SND_SOC_DAPM_MUX(name, SND_SOC_NOPM, 0, 0, ctrl)  argument
127 #define CS48L32_MUX_WIDGETS(name, name_str) CS48L32_MUX(name_str " Input 1", &name##_mux)  argument
129 #define CS48L32_MIXER_WIDGETS(name, name_str)	\  argument
130 	CS48L32_MUX(name_str " Input 1", &name##_in1_mux), \
131 	CS48L32_MUX(name_str " Input 2", &name##_in2_mux), \
132 	CS48L32_MUX(name_str " Input 3", &name##_in3_mux), \
133 	CS48L32_MUX(name_str " Input 4", &name##_in4_mux), \
136 #define CS48L32_MUX_ROUTES(widget, name) \  argument
137 	{ widget, NULL, name " Input 1" }, \
138 	CS48L32_MIXER_INPUT_ROUTES(name " Input 1")
140 #define CS48L32_MIXER_ROUTES(widget, name)		\  argument
141 	{ widget, NULL, name " Mixer" },		\
142 	{ name " Mixer", NULL, name " Input 1" },	\
143 	{ name " Mixer", NULL, name " Input 2" },	\
144 	{ name " Mixer", NULL, name " Input 3" },	\
145 	{ name " Mixer", NULL, name " Input 4" },	\
146 	CS48L32_MIXER_INPUT_ROUTES(name " Input 1"),	\
147 	CS48L32_MIXER_INPUT_ROUTES(name " Input 2"),	\
148 	CS48L32_MIXER_INPUT_ROUTES(name " Input 3"),	\
149 	CS48L32_MIXER_INPUT_ROUTES(name " Input 4")
151 #define CS48L32_DSP_ROUTES_1_8_SYSCLK(name)		\  argument
152 	{ name, NULL, name " Preloader" },		\
153 	{ name, NULL, "SYSCLK" },		\
154 	{ name " Preload", NULL, name " Preloader" },	\
155 	CS48L32_MIXER_ROUTES(name, name "RX1"),		\
156 	CS48L32_MIXER_ROUTES(name, name "RX2"),		\
157 	CS48L32_MIXER_ROUTES(name, name "RX3"),		\
158 	CS48L32_MIXER_ROUTES(name, name "RX4"),		\
159 	CS48L32_MIXER_ROUTES(name, name "RX5"),		\
160 	CS48L32_MIXER_ROUTES(name, name "RX6"),		\
161 	CS48L32_MIXER_ROUTES(name, name "RX7"),		\
162 	CS48L32_MIXER_ROUTES(name, name "RX8")		\
164 #define CS48L32_DSP_ROUTES_1_8(name)			\  argument
165 	{ name, NULL, "DSPCLK" },		\
166 	CS48L32_DSP_ROUTES_1_8_SYSCLK(name)		\
168 #define CS48L32_RATE_CONTROL(name, domain) SOC_ENUM(name, cs48l32_sample_rate[(domain) - 1])  argument
170 #define CS48L32_RATE_ENUM(name, enum) \  argument
171 	SOC_ENUM_EXT(name, enum, snd_soc_get_enum_double, cs48l32_rate_put)
173 #define CS48L32_DSP_RATE_CONTROL(name, num)			\  argument
174 	SOC_ENUM_EXT(name " Rate", cs48l32_dsp_rate_enum[num],	\
178 {	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname,	\
187 #define CS48L32_EQ_BAND_COEFF_CONTROLS(name, band)		\  argument
188 	CS48L32_EQ_COEFF_CONTROL(#name " " #band " A",		\
189 		CS48L32_EQ_REG_NAME_PASTER(name, band, COEFF1),	\
190 		CS48L32_EQ_REG_NAME_PASTER(name, BAND1, COEFF1),	\
192 	CS48L32_EQ_COEFF_CONTROL(#name " " #band " B",		\
193 		CS48L32_EQ_REG_NAME_PASTER(name, band, COEFF1),	\
194 		CS48L32_EQ_REG_NAME_PASTER(name, BAND1, COEFF1),	\
196 	CS48L32_EQ_COEFF_CONTROL(#name " " #band " C",		\
197 		CS48L32_EQ_REG_NAME_PASTER(name, band, COEFF2),	\
198 		CS48L32_EQ_REG_NAME_PASTER(name, BAND1, COEFF1),	\
200 	CS48L32_EQ_COEFF_CONTROL(#name " " #band " PG",		\
201 		CS48L32_EQ_REG_NAME_PASTER(name, band, PG),	\
202 		CS48L32_EQ_REG_NAME_PASTER(name, BAND1, COEFF1),	\
205 #define CS48L32_EQ_COEFF_CONTROLS(name)				\  argument
206 	CS48L32_EQ_BAND_COEFF_CONTROLS(name, BAND1),		\
207 	CS48L32_EQ_BAND_COEFF_CONTROLS(name, BAND2),		\
208 	CS48L32_EQ_BAND_COEFF_CONTROLS(name, BAND3),		\
209 	CS48L32_EQ_BAND_COEFF_CONTROLS(name, BAND4),		\
210 	CS48L32_EQ_COEFF_CONTROL(#name " BAND5 A",		\
211 		CS48L32_EQ_REG_NAME_PASTER(name, BAND5, COEFF1),	\
212 		CS48L32_EQ_REG_NAME_PASTER(name, BAND1, COEFF1),	\
214 	CS48L32_EQ_COEFF_CONTROL(#name " BAND5 B",		\
215 		CS48L32_EQ_REG_NAME_PASTER(name, BAND5, COEFF1),	\
216 		CS48L32_EQ_REG_NAME_PASTER(name, BAND1, COEFF1),	\
218 	CS48L32_EQ_COEFF_CONTROL(#name " BAND5 PG",		\
219 		CS48L32_EQ_REG_NAME_PASTER(name, BAND5, PG),	\
220 		CS48L32_EQ_REG_NAME_PASTER(name, BAND1, COEFF1),	\
224 {	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname,	\
231 #define CS48L32_DSP_FREQ_WIDGET_EV(name, num, event)			\  argument
232 	SND_SOC_DAPM_SUPPLY_S(name "FREQ", 100, SND_SOC_NOPM, num, 0,	\
240 #define CS48L32_MIXER_INPUT_ROUTES(name) \  argument
241 	{ name, "Tone Generator 1", "Tone Generator 1" }, \
242 	{ name, "Tone Generator 2", "Tone Generator 2" }, \
243 	{ name, "Noise Generator", "Noise Generator" }, \
244 	{ name, "IN1L", "IN1L PGA" }, \
245 	{ name, "IN1R", "IN1R PGA" }, \
246 	{ name, "IN2L", "IN2L PGA" }, \
247 	{ name, "IN2R", "IN2R PGA" }, \
248 	{ name, "ASP1RX1", "ASP1RX1" }, \
249 	{ name, "ASP1RX2", "ASP1RX2" }, \
250 	{ name, "ASP1RX3", "ASP1RX3" }, \
251 	{ name, "ASP1RX4", "ASP1RX4" }, \
252 	{ name, "ASP1RX5", "ASP1RX5" }, \
253 	{ name, "ASP1RX6", "ASP1RX6" }, \
254 	{ name, "ASP1RX7", "ASP1RX7" }, \
255 	{ name, "ASP1RX8", "ASP1RX8" }, \
256 	{ name, "ASP2RX1", "ASP2RX1" }, \
257 	{ name, "ASP2RX2", "ASP2RX2" }, \
258 	{ name, "ASP2RX3", "ASP2RX3" }, \
259 	{ name, "ASP2RX4", "ASP2RX4" }, \
260 	{ name, "ISRC1DEC1", "ISRC1DEC1" }, \
261 	{ name, "ISRC1DEC2", "ISRC1DEC2" }, \
262 	{ name, "ISRC1DEC3", "ISRC1DEC3" }, \
263 	{ name, "ISRC1DEC4", "ISRC1DEC4" }, \
264 	{ name, "ISRC1INT1", "ISRC1INT1" }, \
265 	{ name, "ISRC1INT2", "ISRC1INT2" }, \
266 	{ name, "ISRC1INT3", "ISRC1INT3" }, \
267 	{ name, "ISRC1INT4", "ISRC1INT4" }, \
268 	{ name, "ISRC2DEC1", "ISRC2DEC1" }, \
269 	{ name, "ISRC2DEC2", "ISRC2DEC2" }, \
270 	{ name, "ISRC2INT1", "ISRC2INT1" }, \
271 	{ name, "ISRC2INT2", "ISRC2INT2" }, \
272 	{ name, "ISRC3DEC1", "ISRC3DEC1" }, \
273 	{ name, "ISRC3DEC2", "ISRC3DEC2" }, \
274 	{ name, "ISRC3INT1", "ISRC3INT1" }, \
275 	{ name, "ISRC3INT2", "ISRC3INT2" }, \
276 	{ name, "EQ1", "EQ1" }, \
277 	{ name, "EQ2", "EQ2" }, \
278 	{ name, "EQ3", "EQ3" }, \
279 	{ name, "EQ4", "EQ4" }, \
280 	{ name, "DRC1L", "DRC1L" }, \
281 	{ name, "DRC1R", "DRC1R" }, \
282 	{ name, "DRC2L", "DRC2L" }, \
283 	{ name, "DRC2R", "DRC2R" }, \
284 	{ name, "LHPF1", "LHPF1" }, \
285 	{ name, "LHPF2", "LHPF2" }, \
286 	{ name, "LHPF3", "LHPF3" }, \
287 	{ name, "LHPF4", "LHPF4" }, \
288 	{ name, "Ultrasonic 1", "Ultrasonic 1" }, \
289 	{ name, "Ultrasonic 2", "Ultrasonic 2" }, \
290 	{ name, "DSP1.1", "DSP1" }, \
291 	{ name, "DSP1.2", "DSP1" }, \
292 	{ name, "DSP1.3", "DSP1" }, \
293 	{ name, "DSP1.4", "DSP1" }, \
294 	{ name, "DSP1.5", "DSP1" }, \
295 	{ name, "DSP1.6", "DSP1" }, \
296 	{ name, "DSP1.7", "DSP1" }, \
297 	{ name, "DSP1.8", "DSP1" }