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Searched full:mux_reg (Results 1 – 25 of 61) sorted by relevance

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/linux/arch/arm/mach-omap1/
H A Dmux.h27 #define MUX_REG(reg, mode_offset, mode) .mux_reg_name = "FUNC_MUX_CTRL_"#reg, \ macro
28 .mux_reg = FUNC_MUX_CTRL_##reg, \
42 .mux_reg = OMAP7XX_IO_CONF_##reg, \
53 #define MUX_REG(reg, mode_offset, mode) .mux_reg = FUNC_MUX_CTRL_##reg, \ macro
65 .mux_reg = OMAP7XX_IO_CONF_##reg, \
75 #define MUX_CFG(desc, mux_reg, mode_offset, mode, \ argument
81 MUX_REG(mux_reg, mode_offset, mode) \
94 #define MUX_CFG_7XX(desc, mux_reg, mode_offset, mode, \ argument
99 MUX_REG_7XX(mux_reg, mode_offset, mode) \
100 PULL_REG_7XX(mux_reg, pull_bit, pull_status) \
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H A Dmux.c295 if (cfg->mux_reg) { in omap1_cfg_reg()
299 reg_orig = omap_readl(cfg->mux_reg); in omap1_cfg_reg()
312 omap_writel(reg, cfg->mux_reg); in omap1_cfg_reg()
371 cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg); in omap1_cfg_reg()
/linux/drivers/clk/samsung/
H A Dclk-cpu.c143 static void wait_until_mux_stable(void __iomem *mux_reg, u32 mux_pos, in wait_until_mux_stable() argument
149 if (((readl(mux_reg) >> mux_pos) & mask) == mux_value) in wait_until_mux_stable()
153 if (((readl(mux_reg) >> mux_pos) & mask) == mux_value) in wait_until_mux_stable()
203 unsigned long div0, div1 = 0, mux_reg; in exynos_cpuclk_pre_rate_change() local
256 mux_reg = readl(base + regs->mux_sel); in exynos_cpuclk_pre_rate_change()
257 writel(mux_reg | (1 << 16), base + regs->mux_sel); in exynos_cpuclk_pre_rate_change()
282 unsigned long mux_reg; in exynos_cpuclk_post_rate_change() local
297 mux_reg = readl(base + regs->mux_sel); in exynos_cpuclk_post_rate_change()
298 writel(mux_reg & ~(1 << 16), base + regs->mux_sel); in exynos_cpuclk_post_rate_change()
330 unsigned long div0, div1 = 0, mux_reg; in exynos5433_cpuclk_pre_rate_change() local
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/linux/drivers/clk/qcom/
H A Dlpass-gfm-sm8250.c29 unsigned int mux_reg; member
70 .mux_reg = 0x20000,
90 .mux_reg = 0x20000,
110 .mux_reg = 0x220d8,
130 .mux_reg = 0x220d8,
150 .mux_reg = 0x240d8,
170 .mux_reg = 0x240d8,
275 gfm->gfm_mux = gfm->gfm_mux + data->gfm_clks[i]->mux_reg; in lpass_gfm_clk_driver_probe()
/linux/sound/soc/tegra/
H A Dtegra210_ahub.h71 #define MUX_REG(id) (TEGRA210_XBAR_RX_STRIDE * (id)) macro
92 SOC_VALUE_ENUM_WIDE_DECL(ename##_enum, MUX_REG(id), 0, \
101 SOC_VALUE_ENUM_WIDE_DECL(ename##_enum, MUX_REG(id), 0, \
112 SOC_VALUE_ENUM_WIDE_DECL(ename##_enum, MUX_REG(id), 0, \
/linux/arch/arm/mach-davinci/
H A Dmux.h17 const unsigned char mux_reg; member
264 .mux_reg = PINMUX(muxreg), \
275 .mux_reg = INTMUX, \
286 .mux_reg = EVTMUX, \
H A Dmux.c68 reg_orig = __raw_readl(pinmux_base + cfg->mux_reg); in davinci_cfg_reg()
80 __raw_writel(reg, pinmux_base + cfg->mux_reg); in davinci_cfg_reg()
94 cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg); in davinci_cfg_reg()
/linux/drivers/clk/mediatek/
H A Dclk-mtk.h98 uint32_t mux_reg; member
118 .mux_reg = _reg, \
154 .mux_reg = _reg, \
186 .mux_reg = _mux_reg, \
/linux/Documentation/devicetree/bindings/firmware/
H A Dnxp,imx95-scmi-pinctrl.yaml29 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
38 "mux_reg" indicates the offset of mux register.
/linux/drivers/pinctrl/freescale/
H A Dpinctrl-imx7ulp.c270 if (pin_reg->mux_reg == -1) in imx7ulp_pmx_gpio_set_direction()
273 reg = readl(ipctl->base + pin_reg->mux_reg); in imx7ulp_pmx_gpio_set_direction()
278 writel(reg, ipctl->base + pin_reg->mux_reg); in imx7ulp_pmx_gpio_set_direction()
H A Dpinctrl-imx.h61 * @mux_reg: mux register offset
65 s16 mux_reg; member
H A Dpinctrl-vf610.c302 if (pin_reg->mux_reg == -1) in vf610_pmx_gpio_set_direction()
306 reg = readl(ipctl->base + pin_reg->mux_reg); in vf610_pmx_gpio_set_direction()
311 writel(reg, ipctl->base + pin_reg->mux_reg); in vf610_pmx_gpio_set_direction()
H A Dpinctrl-imx-scmi.c66 int mux_reg, conf_reg, input_reg, mux_val, conf_val, input_val; in pinctrl_scmi_imx_dt_node_to_map() local
110 mux_reg = be32_to_cpu(*list++); in pinctrl_scmi_imx_dt_node_to_map()
119 pin_id = mux_reg / 4; in pinctrl_scmi_imx_dt_node_to_map()
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dfsl,imxrt1050.yaml36 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
45 "mux_reg" indicates the offset of mux register.
H A Dfsl,imxrt1170.yaml36 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
45 "mux_reg" indicates the offset of mux register.
H A Dfsl,imx8m-pinctrl.yaml39 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
49 "mux_reg" indicates the offset of mux register.
H A Dfsl,imx9-pinctrl.yaml40 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
49 "mux_reg" indicates the offset of mux register.
H A Dfsl,imx7d-pinctrl.yaml44 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
53 "mux_reg" indicates the offset of mux register.
H A Dfsl,imx35-pinctrl.yaml52 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
61 "mux_reg" indicates the offset of mux register.
H A Dfsl,imx-pinctrl.txt26 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
/linux/drivers/clk/microchip/
H A Dclk-core.c763 void __iomem *mux_reg; member
827 v = (readl(sclk->mux_reg) >> OSC_CUR_SHIFT) & OSC_CUR_MASK; in sclk_get_parent()
851 v = readl(sclk->mux_reg); in sclk_set_parent()
857 writel(v, sclk->mux_reg); in sclk_set_parent()
860 writel(OSC_SWEN, PIC32_SET(sclk->mux_reg)); in sclk_set_parent()
878 cosc = (readl(sclk->mux_reg) >> OSC_CUR_SHIFT) & OSC_CUR_MASK; in sclk_set_parent()
942 sclk->mux_reg = data->mux_reg + core->iobase; in pic32_sys_clk_register()
H A Dclk-core.h29 const u32 mux_reg; member
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6ull-pinfunc-snvs.h11 * <mux_reg conf_reg input_reg mux_mode input_val>
/linux/drivers/pinctrl/
H A Dpinctrl-pistachio.c89 int mux_reg; member
644 .mux_reg = -1, \
658 .mux_reg = -1, \
672 .mux_reg = _reg, \
954 if (pg->mux_reg > 0) { in pistachio_pinmux_enable()
965 val = pctl_readl(pctl, pg->mux_reg); in pistachio_pinmux_enable()
968 pctl_writel(pctl, val, pg->mux_reg); in pistachio_pinmux_enable()
/linux/drivers/clk/
H A Dclk-k210.c38 u8 mux_reg; member
60 .mux_reg = (_reg), \
721 reg = readl(ksc->regs + cfg->mux_reg); in k210_clk_set_parent()
726 writel(reg, ksc->regs + cfg->mux_reg); in k210_clk_set_parent()
741 reg = readl(ksc->regs + cfg->mux_reg); in k210_clk_get_parent()

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