Home
last modified time | relevance | path

Searched +full:multicast +full:- +full:filter +full:- +full:bins (Results 1 – 25 of 31) sorted by relevance

12

/freebsd/sys/contrib/device-tree/Bindings/net/
H A Drenesas,rzn1-gmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/renesas,rzn1-gmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Romain Gantois <romain.gantois@bootlin.com>
17 - renesas,r9a06g032-gmac
18 - renesas,rzn1-gmac
20 - compatible
23 - $ref: snps,dwmac.yaml#
28 - enum:
[all …]
H A Dsnps,dwmac.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandre Torgue <alexandre.torgue@foss.st.com>
11 - Giuseppe Cavallaro <peppe.cavallaro@st.com>
12 - Jose Abreu <joabreu@synopsys.com>
23 - snps,dwmac
24 - snps,dwmac-3.40a
25 - snps,dwmac-3.50a
26 - snps,dwmac-3.610
[all …]
H A Dsophgo,cv1800b-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/sophgo,cv1800b-dwmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Inochi Amaoto <inochiama@gmail.com>
17 - sophgo,cv1800b-dwmac
19 - compatible
24 - const: sophgo,cv1800b-dwmac
25 - const: snps,dwmac-3.70a
32 - description: GMAC main clock
[all …]
H A Dsophgo,sg2044-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/sophgo,sg2044-dwmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Inochi Amaoto <inochiama@gmail.com>
17 - sophgo,sg2044-dwmac
18 - sophgo,sg2042-dwmac
20 - compatible
25 - items:
26 - const: sophgo,sg2042-dwmac
[all …]
H A Dstarfive,jh7110-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/starfive,jh7110-dwmac.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Emil Renner Berthing <kernel@esmil.dk>
12 - Samin Guo <samin.guo@starfivetech.com>
19 - starfive,jh7100-dwmac
20 - starfive,jh7110-dwmac
22 - compatible
27 - items:
[all …]
H A Drenesas,rzv2h-gbeth.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/renesas,rzv2h-gbeth.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
17 - renesas,r9a09g047-gbeth
18 - renesas,r9a09g056-gbeth
19 - renesas,r9a09g057-gbeth
20 - renesas,rzv2h-gbeth
22 - compatible
[all …]
H A Drenesas,r9a09g057-gbeth.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/renesas,r9a09g057-gbeth.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
17 - renesas,r9a09g056-gbeth
18 - renesas,r9a09g057-gbeth
19 - renesas,rzv2h-gbeth
21 - compatible
26 - enum:
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/intel/
H A Dsocfpga_agilex.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/agilex-clock.h>
13 compatible = "intel,socfpga-agilex";
14 #address-cells = <2>;
15 #size-cells = <2>;
17 reserved-memory {
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/altera/
H A Dsocfpga_stratix10.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/stratix10-clock.h>
12 compatible = "altr,socfpga-stratix10";
13 #address-cells = <2>;
14 #size-cells = <2>;
16 reserved-memory {
17 #address-cells = <2>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/intel/socfpga/
H A Dsocfpga_arria10.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
16 enable-method = "altr,socfpga-a10-smp";
19 compatible = "arm,cortex-a9";
22 next-level-cache = <&L2>;
[all …]
H A Dsocfpga.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/reset/altr,rst-mgr.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
22 #address-cells = <1>;
23 #size-cells = <0>;
24 enable-metho
[all...]
/freebsd/sys/dev/sfxge/common/
H A Def10_tlv_layout.h1 /*-
2 * Copyright (c) 2012-2016 Solarflare Communications Inc.
48 * systems which are little-endian and do not do strange things with structure
49 * padding. (Big-endian host systems will require some byte-swapping.)
51 * -----
53 * Please refer to SF-108797-SW for a general overview of the TLV partition
56 * -----
62 * - L is a location, indicating where this tag is expected to be found:
69 * - TTT is a type, which is just a unique value. The same type value
73 * - NNNN is an index of some form. Some item types are per-port, some
[all …]
/freebsd/sys/dev/qlnx/qlnxe/
H A Decore_l2_api.h2 * Copyright (c) 2017-2018 Cavium, Inc.
165 /* MOVE is not supported for multicast */
204 /* Add / remove / move / remove-all unicast MAC-VLAN filters.
206 * 1. Adding a filter to a full table.
207 * 2. Adding a filter which already exists on that vport.
208 * 3. Removing a filter which doesn't exist.
217 /* Add / remove / move multicast MAC filters. */
236 * @brief ecore_eth_rx_queue_start - RX Queue Start Ramrod
263 * @brief ecore_eth_rx_queue_stop - This ramrod closes an Rx queue
283 * @brief - TX Queue Start Ramrod
[all …]
H A Decore_l2.c2 * Copyright (c) 2017-2018 Cavium, Inc.
79 p_l2_info = OSAL_VZALLOC(p_hwfn->p_dev, sizeof(*p_l2_info)); in ecore_l2_alloc()
82 p_hwfn->p_l2_info = p_l2_info; in ecore_l2_alloc()
84 if (IS_PF(p_hwfn->p_dev)) { in ecore_l2_alloc()
85 p_l2_info->queues = RESC_NUM(p_hwfn, ECORE_L2_QUEUE); in ecore_l2_alloc()
92 p_l2_info->queues = (u32)OSAL_MAX_T(u8, rx, tx); in ecore_l2_alloc()
95 pp_qids = OSAL_VZALLOC(p_hwfn->p_dev, in ecore_l2_alloc()
97 p_l2_info->queues); in ecore_l2_alloc()
100 p_l2_info->pp_qid_usage = pp_qids; in ecore_l2_alloc()
102 for (i = 0; i < p_l2_info->queues; i++) { in ecore_l2_alloc()
[all …]
/freebsd/sys/contrib/device-tree/src/arm/renesas/
H A Dr9a06g032.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/r9a06g032-sysctrl.h>
14 #address-cells = <1>;
15 #size-cells = <1>;
18 #address-cells = <1>;
19 #size-cells = <0>;
23 compatible = "arm,cortex-a7";
30 compatible = "arm,cortex-a7";
33 enable-method = "renesas,r9a06g032-smp";
[all …]
/freebsd/sys/contrib/device-tree/src/riscv/thead/
H A Dth1520.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/clock/thead,th1520-clk-ap.h>
9 #include <dt-bindings/power/thead,th1520-power.h>
10 #include <dt-bindings/reset/thead,th1520-reset.h>
14 #address-cells = <2>;
15 #size-cells = <2>;
18 #address-cells = <1>;
19 #size-cells = <0>;
20 timebase-frequency = <3000000>;
[all …]
/freebsd/sys/contrib/device-tree/src/arc/
H A Daxs10x_mb.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
14 compatible = "simple-bus";
15 #address-cells = <1>;
16 #size-cells = <1>;
18 interrupt-parent = <&mb_intc>;
20 creg_rst: reset-controller@11220 {
21 compatible = "snps,axs10x-reset";
22 #reset-cells = <1>;
27 compatible = "snps,axs10x-i2s-pll-clock";
[all …]
H A Dhsdk.dts1 // SPDX-License-Identifier: GPL-2.0-only
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/reset/snps,hsdk-reset.h>
18 #address-cells = <2>;
19 #size-cells = <2>;
22 … "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
30 #address-cells = <1>;
31 #size-cells = <0>;
62 input_clk: input-clk {
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/renesas/
H A Dr9a09g056.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/clock/renesas,r9a09g056-cpg.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
12 /* RZV2N_Px = Offset address of PFC_P_mn - 0x20 */
31 #address-cells = <2>;
32 #size-cells = <2>;
34 audio_extal_clk: audio-clk {
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
[all …]
H A Dr9a09g047.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/clock/renesas,r9a09g047-cpg.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
16 audio_extal_clk: audio-clk {
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
20 clock-frequency = <0>;
30 cluster0_opp: opp-table-0 {
[all …]
/freebsd/sys/contrib/device-tree/src/riscv/starfive/
H A Djh7100.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive-jh7100.h>
9 #include <dt-bindings/reset/starfive-jh7100.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
17 #address-cells = <1>;
18 #size-cells = <0>;
21 compatible = "sifive,u74-mc", "riscv";
23 d-cache-block-size = <64>;
[all …]
H A Djh7110.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive,jh7110-crg.h>
9 #include <dt-bindings/power/starfive,jh7110-pmu.h>
10 #include <dt-bindings/reset/starfive,jh7110-crg.h>
11 #include <dt-bindings/thermal/thermal.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
19 #address-cells = <1>;
20 #size-cells = <0>;
[all …]
/freebsd/sys/contrib/dev/athk/ath10k/
H A Dwmi.h1 /* SPDX-License-Identifier: ISC */
3 * Copyright (c) 2005-2011 Atheros Communications Inc.
4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
5 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
28 * 1. Add new WMI commands ONLY within the specified range - 0x9000 - 0x9fff
44 * variable is already 4-byte aligned by virtue of being a u32
526 * for wmi_services is 64 as target is using only 4-bits of each 32-bit
532 __le32_to_cpu((wmi_svc_bmap)[((svc_id) - (len)) / 28]) & \
533 BIT(((((svc_id) - (len)) % 28) & 0x1f) + 4))
1159 /** DFS-specific commands */
[all …]
/freebsd/sys/contrib/device-tree/src/riscv/sophgo/
H A Dcv180x.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <dt-bindings/clock/sophgo,cv1800.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include "cv18xx-reset.h"
13 #address-cells = <1>;
14 #size-cells = <1>;
17 compatible = "fixed-clock";
18 clock-output-names = "osc_25m";
19 #clock-cells = <0>;
[all …]
/freebsd/sys/dev/bxe/
H A Decore_sp.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2007-2017 QLogic Corporation. All rights reserved.
39 * ecore_exe_queue_init - init the Exe Queue object
61 ECORE_LIST_INIT(&o->exe_queue); in ecore_exe_queue_init()
62 ECORE_LIST_INIT(&o->pending_comp); in ecore_exe_queue_init()
64 ECORE_SPIN_LOCK_INIT(&o->lock, sc); in ecore_exe_queue_init()
66 o->exe_chunk_len = exe_len; in ecore_exe_queue_init()
67 o->owner = owner; in ecore_exe_queue_init()
70 o->validate = validate; in ecore_exe_queue_init()
[all …]

12