Searched +full:mt8192 +full:- +full:pcie (Results 1 – 8 of 8) sorted by relevance
| /freebsd/sys/contrib/device-tree/Bindings/pci/ |
| H A D | mediatek-pcie-gen3.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pci/mediatek-pcie-gen3.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Gen3 PCIe controller on MediaTek SoCs 10 - Jianjun Wang <jianjun.wang@mediatek.com> 13 PCIe Gen3 MAC controller for MediaTek SoCs, it supports Gen3 speed 16 This PCIe controller supports up to 256 MSI vectors, the MSI hardware 19 +-----+ 21 +-----+ [all …]
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| /freebsd/sys/contrib/device-tree/src/arm64/mediatek/ |
| H A D | mt7988a.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only OR MIT 3 #include <dt-bindings/clock/mediatek,mt7988-clk.h> 4 #include <dt-bindings/interrupt-controller/arm-gic.h> 5 #include <dt-bindings/phy/phy.h> 6 #include <dt-bindings/pinctrl/mt65xx.h> 7 #include <dt-bindings/reset/mediatek,mt7988-resets.h> 11 interrupt-parent = <&gic>; 12 #address-cells = <2>; 13 #size-cells = <2>; 16 compatible = "mediatek,mt7988-cci", "mediatek,mt8183-cci"; [all …]
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| H A D | mt8192.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 7 /dts-v1/; 8 #include <dt-bindings/clock/mt8192-clk.h> 9 #include <dt-bindings/gce/mt8192-gce.h> 10 #include <dt-bindings/interrupt-controller/arm-gic.h> 11 #include <dt-bindings/interrupt-controller/irq.h> 12 #include <dt-bindings/memory/mt8192-larb-port.h> 13 #include <dt-bindings/pinctrl/mt8192-pinfunc.h> 14 #include <dt-bindings/phy/phy.h> 15 #include <dt-bindings/power/mt8192-power.h> [all …]
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| H A D | mt8195.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 7 /dts-v1/; 8 #include <dt-bindings/clock/mt8195-clk.h> 9 #include <dt-bindings/gce/mt8195-gce.h> 10 #include <dt-bindings/interrupt-controller/arm-gic.h> 11 #include <dt-bindings/interrupt-controller/irq.h> 12 #include <dt-bindings/memory/mt8195-memory-port.h> 13 #include <dt-bindings/phy/phy.h> 14 #include <dt-bindings/pinctrl/mt8195-pinfunc.h> 15 #include <dt-bindings/power/mt8195-power.h> [all …]
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| H A D | mt8192-asurada.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 6 /dts-v1/; 7 #include "mt8192.dtsi" 9 #include <dt-bindings/gpio/gpio.h> 10 #include <dt-bindings/spmi/spmi.h> 25 stdout-path = "serial0:115200n8"; 33 backlight_lcd0: backlight-lcd0 { 34 compatible = "pwm-backlight"; 36 power-supply = <&ppvar_sys>; 37 enable-gpios = <&pio 152 0>; [all …]
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| H A D | mt7986a.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 7 #include <dt-bindings/interrupt-controller/irq.h> 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 9 #include <dt-bindings/clock/mt7986-clk.h> 10 #include <dt-bindings/reset/mt7986-resets.h> 11 #include <dt-bindings/phy/phy.h> 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 20 #address-cells = <1>; [all …]
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| H A D | mt8188.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ 7 /dts-v1/; 8 #include <dt-bindings/clock/mediatek,mt8188-clk.h> 9 #include <dt-bindings/interrupt-controller/arm-gic.h> 10 #include <dt-bindings/interrupt-controller/irq.h> 11 #include <dt-bindings/mailbox/mediatek,mt8188-gce.h> 12 #include <dt-bindings/memory/mediatek,mt8188-memory-port.h> 13 #include <dt-bindings/phy/phy.h> 14 #include <dt-bindings/pinctrl/mediatek,mt8188-pinfunc.h> 15 #include <dt-bindings/power/mediatek,mt8188-power.h> [all …]
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| /freebsd/sys/contrib/device-tree/Bindings/phy/ |
| H A D | mediatek,tphy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 4 --- 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 title: MediaTek T-PHY Controller 11 - Chunfeng Yun <chunfeng.yun@mediatek.com> 14 The T-PHY controller supports physical layer functionality for a number of 15 controllers on MediaTek SoCs, includes USB2.0, USB3.0, PCIe and SATA. 17 Layout differences of banks between T-PHY V1 (mt8173/mt2701) and 18 T-PHY V2 (mt2712) / V3 (mt8195) when works on USB mode: 19 ----------------------------------- [all …]
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