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Searched +full:mt7986 +full:- +full:eth (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/clk/mediatek/
H A Dclk-mt7986-eth.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
12 #include "clk-mtk.h"
13 #include "clk-gate.h"
15 #include <dt-bindings/clock/mt7986-clk.h>
82 { .compatible = "mediatek,mt7986-ethsys", .data = &eth_desc },
83 { .compatible = "mediatek,mt7986-sgmiisys_0", .data = &sgmii0_desc },
84 { .compatible = "mediatek,mt7986-sgmiisys_1", .data = &sgmii1_desc },
91 .name = "clk-mt7986-eth",
99 MODULE_DESCRIPTION("MediaTek MT7986 Ethernet clocks driver");
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o rese…
3 obj-$(CONFIG_COMMON_CLK_MEDIATEK_FHCTL) += clk-fhctl.o clk-pllfh.o
5 obj-$(CONFIG_COMMON_CLK_MT6735) += clk-mt6735-apmixedsys.o clk-mt6735-infracfg.o clk-mt6735-pericfg…
6 obj-$(CONFIG_COMMON_CLK_MT6735_IMGSYS) += clk-mt6735-imgsys.o
7 obj-$(CONFIG_COMMON_CLK_MT6735_MFGCFG) += clk-mt6735-mfgcfg.o
8 obj-$(CONFIG_COMMON_CLK_MT6735_VDECSYS) += clk-mt6735-vdecsys.o
9 obj-$(CONFIG_COMMON_CLK_MT6735_VENCSYS) += clk-mt6735-vencsys.o
10 obj-$(CONFIG_COMMON_CLK_MT6765) += clk-mt6765.o
11 obj-$(CONFIG_COMMON_CLK_MT6765_AUDIOSYS) += clk-mt6765-audio.o
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/linux/Documentation/devicetree/bindings/net/
H A Dmediatek,net.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Bianconi <lorenzo@kernel.org>
11 - Felix Fietkau <nbd@nbd.name>
20 - mediatek,mt2701-eth
21 - mediatek,mt7623-eth
22 - mediatek,mt7621-eth
23 - mediatek,mt7622-eth
24 - mediatek,mt7629-eth
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/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmediatek,mt7986-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt7986-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek MT7986 Pin Controller
10 - Sean Wang <sean.wang@kernel.org>
13 The MediaTek's MT7986 Pin controller is used to control SoC pins.
18 - mediatek,mt7986a-pinctrl
19 - mediatek,mt7986b-pinctrl
25 reg-names:
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/linux/drivers/net/ethernet/mediatek/
H A Dmtk_wed.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/dma-mapping.h>
102 regmap_update_bits(dev->hw->regs, reg, mask | val, val); in wed_m32()
138 return readl(dev->wlan.base + reg); in wifi_r32()
144 writel(val, dev->wlan.base + reg); in wifi_w32()
164 if (!mtk_wed_is_v3_or_greater(dev->hw)) in mtk_wdma_v3_rx_reset()
173 dev_err(dev->hw->dev, "rx reset failed\n"); in mtk_wdma_v3_rx_reset()
178 dev_err(dev->hw->dev, "rx reset failed\n"); in mtk_wdma_v3_rx_reset()
186 dev_err(dev->hw->dev, "rx reset failed\n"); in mtk_wdma_v3_rx_reset()
191 dev_err(dev->hw->dev, "rx reset failed\n"); in mtk_wdma_v3_rx_reset()
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H A Dmtk_eth_soc.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
24 #include <linux/pcs/pcs-mtk-lynxi.h>
35 static int mtk_msg_level = -1;
37 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
289 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg) in mtk_w32() argument
291 __raw_writel(val, eth->base + reg); in mtk_w32()
294 u32 mtk_r32(struct mtk_eth *eth, unsigned reg) in mtk_r32() argument
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