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Searched +full:mt7621 +full:- +full:memc (Results 1 – 6 of 6) sorted by relevance

/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dmediatek,mt7621-memc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/mediatek,mt7621-memc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MT7621 SDRAM controller
10 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
15 - const: mediatek,mt7621-memc
16 - const: syscon
22 - compatible
23 - reg
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/linux/drivers/clk/ralink/
H A Dclk-mt7621.c1 // SPDX-License-Identifier: GPL-2.0
3 * Mediatek MT7621 Clock Driver
9 #include <linux/clk-provider.h>
14 #include <linux/reset-controller.h>
16 #include <dt-bindings/clock/mt7621-clk.h>
17 #include <dt-bindings/reset/mt7621-reset.h>
37 struct regmap *memc; member
101 struct regmap *sysc = clk_gate->priv->sysc; in mt7621_gate_enable()
104 clk_gate->bit_idx, clk_gate->bit_idx); in mt7621_gate_enable()
110 struct regmap *sysc = clk_gate->priv->sysc; in mt7621_gate_disable()
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/linux/arch/mips/ralink/
H A Dof.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
24 #include <asm/mach-ralink/ralink_regs.h>
33 { .compatible = "mediatek,mt7621-memc" },
34 { .compatible = "ralink,mt7620a-memc" },
35 { .compatible = "ralink,rt2880-memc" },
36 { .compatible = "ralink,rt3050-memc" },
37 { .compatible = "ralink,rt3883-memc" },
42 { .compatible = "mediatek,mt7621-sysc" },
43 { .compatible = "ralink,mt7620-sysc" },
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/linux/Documentation/devicetree/bindings/clock/
H A Dmediatek,mt7621-sysc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/mediatek,mt7621-sysc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MT7621 Clock
10 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
13 The MT7621 has a PLL controller from where the cpu clock is provided
21 [1]: <include/dt-bindings/clock/mt7621-clk.h>.
28 [2]: <include/dt-bindings/reset/mt7621-reset.h>.
33 - const: mediatek,mt7621-sysc
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/linux/arch/mips/boot/dts/ralink/
H A Dmt7628a.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #address-cells = <1>;
5 #size-cells = <1>;
6 compatible = "ralink,mt7628a-soc";
9 #address-cells = <1>;
10 #size-cells = <0>;
19 resetc: reset-controller {
20 compatible = "ralink,rt2880-reset";
21 #reset-cells = <1>;
24 cpuintc: interrupt-controller {
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/linux/
H A DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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