| /freebsd/sys/x86/x86/ |
| H A D | msi.c | 34 * Support for PCI Message Signalled Interrupts (MSI). MSI interrupts on
63 /* Fields in address for Intel MSI messages. */
72 /* Fields in data for Intel MSI messages. */
89 * Build Intel MSI message and data values from a source. AMD64 systems
92 #define INTEL_ADDR(msi) \ argument
93 (MSI_INTEL_ADDR_BASE | (msi)->msi_cpu << 12 | \
95 #define INTEL_DATA(msi) \ argument
96 (MSI_INTEL_DATA_TRGREDG | MSI_INTEL_DATA_DELFIXED | (msi)->msi_vector)
98 static MALLOC_DEFINE(M_MSI, "msi", "PCI MSI");
101 * MSI sources are bunched into groups. This is because MSI forces
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/pci/ |
| H A D | pci-msi.txt | 2 relationship between PCI devices and MSI controllers.
18 Requester ID. A mechanism is required to associate a device with both the MSI
22 For generic MSI bindings, see
23 Documentation/devicetree/bindings/interrupt-controller/msi.txt.
32 - msi-map: Maps a Requester ID to an MSI controller and associated
33 msi-specifier data. The property is an arbitrary number of tuples of
34 (rid-base,msi-controller,msi-base,length), where:
38 * msi-controller is a single phandle to an MSI controller
40 * msi-base is an msi-specifier describing the msi-specifier produced for the
47 the listed msi-controller, with the msi-specifier (r - rid-base + msi-base).
[all …]
|
| H A D | brcm,iproc-pcie.txt | 44 MSI support (optional):
46 For older platforms without MSI integrated in the GIC, iProc PCIe core provides
47 an event queue based MSI support. The iProc MSI uses host memories to store
48 MSI posted writes in the event queues
50 On newer iProc platforms, gicv2m or gicv3-its based MSI support should be used
52 - msi-map: Maps a Requester ID to an MSI controller and associated MSI
55 - msi-parent: Link to the device node of the MSI controller, used when no MSI
56 sideband data is passed between the iProc PCIe controller and the MSI
60 the use of 'msi-map' and 'msi-parent':
61 Documentation/devicetree/bindings/pci/pci-msi.txt
[all …]
|
| H A D | xgene-pci-msi.txt | 1 * AppliedMicro X-Gene v1 PCIe MSI controller
5 - compatible: should be "apm,xgene1-msi" to identify
6 X-Gene v1 PCIe MSI controller block.
7 - msi-controller: indicates that this is an X-Gene v1 PCIe MSI controller node
9 registers. These registers include the MSI termination address and data
10 registers as well as the MSI interrupt status registers.
16 Each PCIe node needs to have property msi-parent that points to an MSI
23 + MSI node:
24 msi@79000000 {
25 compatible = "apm,xgene1-msi";
[all …]
|
| H A D | brcm,iproc-pcie.yaml | 63 msi:
65 $ref: /schemas/interrupt-controller/msi-controller.yaml#
71 - const: brcm,iproc-msi
76 brcm,pcie-msi-inten:
80 interrupt enable registers to be set explicitly to enable MSI
82 msi-parent: true
86 brcm,pcie-msi-inten: [msi-controller]
139 msi-parent = <&msi0>;
141 /* iProc event queue based MSI */
142 msi0: msi {
[all …]
|
| H A D | altr,msi-controller.yaml | 5 $id: http://devicetree.org/schemas/altr,msi-controller.yaml#
8 title: Altera PCIe MSI controller
16 - altr,msi-1.0
31 msi-controller: true
44 - msi-controller
48 - $ref: /schemas/interrupt-controller/msi-controller.yaml#
56 msi@ff200000 {
57 compatible = "altr,msi-1.0";
63 msi-controller;
|
| H A D | altera-pcie-msi.txt | 1 * Altera PCIe MSI controller
4 - compatible: should contain "altr,msi-1.0"
14 - msi-controller: indicates that this is MSI controller node
18 msi0: msi@0xFF200000 {
19 compatible = "altr,msi-1.0";
25 msi-controller;
|
| /freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/ |
| H A D | msi.txt | 1 This document describes the generic device tree binding for MSI controllers and
9 those busses to the MSI controllers which they are capable of using,
17 they can address. An MSI controller may feature a number of doorbells.
22 MSI controllers may have restrictions on permitted payloads.
28 MSI controller and device rather than a property of either in isolation).
31 MSI controllers:
34 An MSI controller signals interrupts to a CPU when a write is made to an MMIO
35 address by some master. An MSI controller may feature a number of doorbells.
40 - msi-controller: Identifies the node as an MSI controller.
45 - #msi-cells: The number of cells in an msi-specifier, required if not zero.
[all …]
|
| H A D | fsl,ls-msi.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,ls-msi.yaml#
7 title: Freescale Layerscape SCFG PCIe MSI controller
15 Each PCIe node needs to have property msi-parent that points to
16 MSI controller node
24 - fsl,ls1012a-msi
25 - fsl,ls1021a-msi
26 - fsl,ls1043a-msi
27 - fsl,ls1043a-v1.1-msi
28 - fsl,ls1046a-msi
33 '#msi-cells':
[all …]
|
| H A D | loongson,pch-msi.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/loongson,pch-msi.yaml#
7 title: Loongson PCH MSI Controller
14 transforming interrupts from PCIe MSI into HyperTransport vectorized
19 const: loongson,pch-msi-1.0
24 loongson,msi-base-vec:
27 to PCH MSI.
32 loongson,msi-num-vecs:
35 to PCH MSI.
40 msi-controller: true
45 - msi-controller
[all …]
|
| H A D | fsl,ls-scfg-msi.txt | 1 * Freescale Layerscape SCFG PCIe MSI controller
5 - compatible: should be "fsl,<soc-name>-msi" to identify
6 Layerscape PCIe MSI controller block such as:
7 "fsl,ls1021a-msi"
8 "fsl,ls1043a-msi"
9 "fsl,ls1046a-msi"
10 "fsl,ls1043a-v1.1-msi"
11 "fsl,ls1012a-msi"
12 - msi-controller: indicates that this is a PCIe MSI controller node
20 Each PCIe node needs to have property msi-parent that points to
[all …]
|
| H A D | fsl,mu-msi.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,mu-msi.yaml#
7 title: Freescale/NXP i.MX Messaging Unit (MU) work as msi controller
25 MU can work as msi interrupt controller to do doorbell
28 - $ref: /schemas/interrupt-controller/msi-controller.yaml#
33 - fsl,imx6sx-mu-msi
34 - fsl,imx7ulp-mu-msi
35 - fsl,imx8ulp-mu-msi
36 - fsl,imx8ulp-mu-msi-s4
67 msi-controller: true
69 "#msi-cells":
[all …]
|
| H A D | msi-controller.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/msi-controller.yaml#
7 title: MSI controller
13 An MSI controller signals interrupts to a CPU when a write is made
14 to an MMIO address by some master. An MSI controller may feature a
18 "#msi-cells":
20 The number of cells in an msi-specifier, required if not zero.
26 The meaning of the msi-specifier is defined by the device tree
27 binding of the specific MSI controller.
30 msi-controller:
32 Identifies the node as an MSI controller.
[all …]
|
| H A D | arm,gic-v3.yaml | 115 msi-controller:
182 mbi-ranges: [ msi-controller ]
183 msi-controller: [ mbi-ranges ]
192 # msi-controller is preferred, but allow other names
193 "^(msi-controller|gic-its|interrupt-controller)@[0-9a-f]+$":
197 used to route Message Signalled Interrupts (MSI) to the CPUs.
208 msi-controller: true
210 "#msi-cells":
212 The single msi-cell is the DeviceID of the device which will generate
213 the MSI.
[all …]
|
| H A D | al,alpine-msix.txt | 3 See arm,gic-v3.txt for SPI and MSI definitions.
10 - msi-controller: identifies the node as an PCI Message Signaled Interrupt
12 - al,msi-base-spi: SPI base of the MSI frame
13 - al,msi-num-spis: number of SPIs assigned to the MSI frame, relative to SPI0
22 msi-controller;
23 al,msi-base-spi = <160>;
24 al,msi-num-spis = <160>;
|
| H A D | riscv,imsics.yaml | 7 title: RISC-V Incoming MSI Controller (IMSIC)
14 MSI controller (IMSIC) for handling MSIs in a RISC-V platform. The RISC-V
32 RISC-V platform. The MSI target address of a IMSIC interrupt file at given
44 - $ref: /schemas/interrupt-controller/msi-controller.yaml#
64 msi-controller: true
66 "#msi-cells":
99 Number of guest index bits in the MSI target address.
105 Number of HART index bits in the MSI target address. When not
113 Number of group index bits in the MSI target address.
122 MSI target address.
[all …]
|
| H A D | arm,gic.yaml | 153 * GICv2m extension for MSI/MSI-x support (Optional)
155 Certain revisions of GIC-400 supports MSI/MSI-x via V2M register frame(s).
162 msi-controller: true
166 description: GICv2m MSI interface register base and size
168 arm,msi-base-spi:
170 this property should contain the SPI base of the MSI frame, overriding
174 arm,msi-num-spis:
182 - msi-controller
215 // GICv2m extension for MSI/MSI-x support
231 msi-controller;
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/powerpc/fsl/ |
| H A D | msi-pic.txt | 1 * Freescale MSI interrupt controller
5 The first is "fsl,CHIP-msi", where CHIP is the processor(mpc8610, mpc8572,
6 etc.) and the second is "fsl,mpic-msi" or "fsl,ipic-msi" or
7 "fsl,mpic-msi-v4.3" depending on the parent type and version. If mpic
8 version is 4.3, the number of MSI registers is increased to 16, MSIIR1 is
9 provided to access these 16 registers, and compatible "fsl,mpic-msi-v4.3"
17 region must be added because different MSI group has different MSIIR1 offset.
21 be set as edge sensitive. If msi-available-ranges is present, only
25 - msi-available-ranges: use <start count> style section to define which
26 msi interrupt can be used in the 256 msi interrupts. This property is
[all …]
|
| /freebsd/crypto/krb5/src/windows/installer/wix/ |
| H A D | msi-deployment-guide.txt | 4 MSI Deployment Guide
36 Beginning with "Kerberos for Windows" version 2.6.5, a MSI installer
42 customize the MSI package for a particular organization. Although
51 The information in this document applies to MSI packages
53 onwards or MSI packages built from corresponding source
58 software for editing the MSI database tables and generating the
59 transform from the modified MSI package. ORCA.EXE and MSITRAN.EXE
63 For reference, the schema for the MSI package is based on
64 SCHEMA.MSI distributed with the Platform SDK.
68 http://msdn.microsoft.com/library/en-us/msi/setup/windows_installer_start_page.asp
[all …]
|
| /freebsd/share/man/man9/ |
| H A D | pci.9 | 468 Read the MSI routing ID.
469 This is needed by some interrupt controllers to route MSI and MSI-X interrupts.
846 .Pq MSI
849 .Pq MSI-X
855 MSI and MSI-X interrupts are available to PCI devices as one or more
858 A driver must ask the PCI bus to allocate MSI or MSI-X interrupts
863 before it can use MSI or MSI-X
868 resource if MSI or MSI-X interrupts have been allocated,
869 and attempts to allocate MSI or MSI-X interrupts will fail if the
873 A driver is only allowed to use either MSI or MSI-X,
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/misc/ |
| H A D | fsl,qoriq-mc.txt | 31 The MSI writes are accompanied by sideband data which is derived from the ICID.
32 The msi-map property is used to associate the devices with both the ITS
35 For generic MSI bindings, see
36 Documentation/devicetree/bindings/interrupt-controller/msi.txt.
127 - msi-map: Maps an ICID to a GIC ITS and associated msi-specifier
131 (icid-base,gic-its,msi-base,length).
134 associated with the listed GIC ITS, with the msi-specifier
135 (i - icid-base + msi-base).
139 - msi-parent
141 Definition: Describes the MSI controller node handling message
[all …]
|
| H A D | fsl,qoriq-mc.yaml | 41 The MSI writes are accompanied by sideband data which is derived from the ICID.
42 The msi-map property is used to associate the devices with both the ITS
45 For generic MSI bindings, see
46 Documentation/devicetree/bindings/interrupt-controller/msi.txt.
102 msi-map:
104 Maps an ICID to a GIC ITS and associated msi-specifier
108 (icid-base,gic-its,msi-base,length).
111 associated with the listed GIC ITS, with the msi-specifier
112 (i - icid-base + msi-base).
114 msi-parent:
[all …]
|
| /freebsd/sys/amd64/vmm/io/ |
| H A D | ppt.c | 59 * If the MSI-X table is located in the middle of a BAR then that MMIO
60 * region gets split into two segments - one segment above the MSI-X table
61 * and the other segment below the MSI-X table - with a hole in place of
62 * the MSI-X table so accesses to it can be trapped and emulated.
68 MALLOC_DEFINE(M_PPTMSIX, "pptmsix", "Passthru MSI-X resources");
94 } msi; member
258 if (ppt->msi.num_msgs == 0) in ppt_teardown_msi()
261 for (i = 0; i < ppt->msi.num_msgs; i++) { in ppt_teardown_msi()
262 rid = ppt->msi.startrid + i; in ppt_teardown_msi()
263 res = ppt->msi.res[i]; in ppt_teardown_msi()
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/bus/ |
| H A D | fsl,imx8qxp-pixel-link-msi-bus.yaml | 4 $id: http://devicetree.org/schemas/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml#
7 title: Freescale i.MX8qxp Pixel Link Medium Speed Interconnect (MSI) Bus
13 i.MX8qxp pixel link MSI bus is used to control settings of PHYs, I/Os
14 sitting together with the PHYs. It is not the same as the MSI bus coming
18 i.MX8qxp pixel link MSI bus is a simple memory-mapped bus. Two input clocks,
19 that is, MSI clock and AHB clock, need to be enabled so that peripherals
29 pixel link MSI bus controller and does not allow SCFW user to control it.
43 - fsl,imx8qxp-display-pixel-link-msi-bus
44 - fsl,imx8qm-display-pixel-link-msi-bus
52 - fsl,imx8qxp-display-pixel-link-msi
[all...] |
| /freebsd/sys/contrib/device-tree/Bindings/mailbox/ |
| H A D | brcm,iproc-flexrm-mbox.txt | 14 - msi-parent: Phandles (and potential Device IDs) to MSI controllers
16 interrupts) to CPU. There is one MSI for each FlexRM ring.
17 Refer devicetree/bindings/interrupt-controller/msi.txt
23 The 2nd cell contains MSI completion threshold. This is the
25 one MSI interrupt to CPU.
27 The 3rd cell contains MSI timer value representing time for
31 specified by this cell then it will inject one MSI interrupt
46 msi-parent = <&gic_its 0x7f00>;
|