| /freebsd/sys/contrib/device-tree/Bindings/pci/ |
| H A D | pci-msi.txt | 2 relationship between PCI devices and MSI controllers.
18 Requester ID. A mechanism is required to associate a device with both the MSI
22 For generic MSI bindings, see
23 Documentation/devicetree/bindings/interrupt-controller/msi.txt.
30 -------------------
32 - msi-map: Maps a Requester ID to an MSI controller and associated
33 msi-specifier data. The property is an arbitrary number of tuples of
34 (rid-base,msi-controller,msi-base,length), where:
36 * rid-base is a single cell describing the first RID matched by the entry.
38 * msi-controller is a single phandle to an MSI controller
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| H A D | hisilicon-histb-pcie.txt | 6 Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
11 - compatible: Should be one of the following strings:
12 "hisilicon,hi3798cv200-pcie"
13 - reg: Should contain sysctl, rc_dbi, config registers location and length.
14 - reg-names: Must include the following entries:
16 "rc-dbi": configuration space of PCIe controller;
18 - bus-range: PCI bus numbers covered.
19 - interrupts: MSI interrupt.
20 - interrupt-names: Must include "msi" entries.
21 - clocks: List of phandle and clock specifier pairs as listed in clock-names
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| H A D | altera-pcie-msi.txt | 1 * Altera PCIe MSI controller
4 - compatible: should contain "altr,msi-1.0"
5 - reg: specifies the physical base address of the controller and
7 - reg-names: must include the following entries:
10 - interrupts: specifies the interrupt source of the parent interrupt
11 controller. The format of the interrupt specifier depends on the
13 - num-vectors: number of vectors, range 1 to 32.
14 - msi-controller: indicates that this is MSI controller node
18 msi0: msi@0xFF200000 {
19 compatible = "altr,msi-1.0";
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| H A D | ti,j721e-pci-host.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/pci/ti,j721e-pci-host.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Kishon Vijay Abraham I <kishon@ti.com>
16 - const: ti,j721e-pcie-host
17 - const: ti,j784s4-pcie-host
18 - description: PCIe controller in AM64
20 - const: ti,am64-pcie-host
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| H A D | qcom,pcie.txt | 3 - compatible:
7 - "qcom,pcie-ipq8064" for ipq8064
8 - "qcom,pcie-ipq8064-v2" for ipq8064 rev 2 or ipq8065
9 - "qcom,pcie-apq8064" for apq8064
10 - "qcom,pcie-apq8084" for apq8084
11 - "qcom,pcie-msm8996" for msm8996 or apq8096
12 - "qcom,pcie-ipq4019" for ipq4019
13 - "qcom,pcie-ipq8074" for ipq8074
14 - "qcom,pcie-qcs404" for qcs404
15 - "qcom,pcie-sc8180x" for sc8180x
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| H A D | xilinx-nwl-pcie.txt | 4 - compatible: Should contain "xlnx,nwl-pcie-2.11"
5 - #address-cells: Address representation for root ports, set to <3>
6 - #size-cells: Size representation for root ports, set to <2>
7 - #interrupt-cells: specifies the number of cells needed to encode an
9 - reg: Should contain Bridge, PCIe Controller registers location,
11 - reg-names: Must include the following entries:
15 - device_type: must be "pci"
16 - interrupts: Should contain NWL PCIe interrupt
17 - interrupt-names: Must include the following entries:
18 "msi1, msi0": interrupt asserted when an MSI is received
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| H A D | xlnx,nwl-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/xlnx,nwl-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thippeswamy Havalige <thippeswamy.havalige@amd.com>
13 - $ref: /schemas/pci/pci-host-bridge.yaml#
14 - $ref: /schemas/interrupt-controller/msi-controller.yaml#
18 const: xlnx,nwl-pcie-2.11
22 - description: PCIe bridge registers location.
23 - description: PCIe Controller registers location.
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| H A D | altera-pcie.txt | 4 - compatible : should contain "altr,pcie-root-port-1.0" or "altr,pcie-root-port-2.0"
5 - reg: a list of physical base address and length for TXS and CRA.
6 For "altr,pcie-root-port-2.0", additional HIP base address and length.
7 - reg-names: must include the following entries:
10 "Hip": Hard IP region (if "altr,pcie-root-port-2.0")
11 - interrupts: specifies the interrupt source of the parent interrupt
12 controller. The format of the interrupt specifier depends
14 - device_type: must be "pci"
15 - #address-cells: set to <3>
16 - #size-cells: set to <2>
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| H A D | uniphier-pcie.txt | 9 Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
12 - compatible: Should be "socionext,uniphier-pcie".
13 - reg: Specifies offset and length of the register set for the device.
14 According to the reg-names, appropriate register sets are required.
15 - reg-names: Must include the following entries:
16 "dbi" - controller configuration registers
17 "link" - SoC-specific glue layer registers
18 "config" - PCIe configuration space
19 "atu" - iATU registers for DWC version 4.80 or later
20 - clocks: A phandle to the clock gate for PCIe glue layer including
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| H A D | rockchip-pcie-host.txt | 4 - #address-cells: Address representation for root ports, set to <3>
5 - #size-cells: Size representation for root ports, set to <2>
6 - #interrupt-cells: specifies the number of cells needed to encode an
8 - compatible: Should contain "rockchip,rk3399-pcie"
9 - reg: Two register ranges as listed in the reg-names property
10 - reg-names: Must include the following names
11 - "axi-base"
12 - "apb-base"
13 - clocks: Must contain an entry for each entry in clock-names.
14 See ../clocks/clock-bindings.txt for details.
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| H A D | nvidia,tegra194-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Vidya Sagar <vidyas@nvidia.com>
16 inherits all the common properties defined in snps,dw-pcie.yaml. Some of
20 See nvidia,tegra194-pcie-ep.yaml for details on the Endpoint mode device
26 - nvidia,tegra194-pcie
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| H A D | nvidia,tegra194-pcie.txt | 4 and thus inherits all the common properties defined in snps,dw-pcie.yaml and
5 snps,dw-pcie-ep.yaml.
10 - power-domains: A phandle to the node that controls power to the respective
11 PCIe controller and a specifier name for the PCIe controller. Following are
20 "include/dt-bindings/power/tegra194-powergate.h" file.
21 - reg: A list of physical base address and length pairs for each set of
22 controller registers. Must contain an entry for each entry in the reg-names
24 - reg-names: Must include the following entries:
26 "config": As per the definition in snps,dw-pcie.yaml
32 - interrupts: A list of interrupt outputs of the controller. Must contain an
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| H A D | rcar-pci.txt | 1 * Renesas R-Car PCIe interface
4 compatible: "renesas,pcie-r8a7742" for the R8A7742 SoC;
5 "renesas,pcie-r8a7743" for the R8A7743 SoC;
6 "renesas,pcie-r8a7744" for the R8A7744 SoC;
7 "renesas,pcie-r8a774a1" for the R8A774A1 SoC;
8 "renesas,pcie-r8a774b1" for the R8A774B1 SoC;
9 "renesas,pcie-r8a774c0" for the R8A774C0 SoC;
10 "renesas,pcie-r8a7779" for the R8A7779 SoC;
11 "renesas,pcie-r8a7790" for the R8A7790 SoC;
12 "renesas,pcie-r8a7791" for the R8A7791 SoC;
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| H A D | mediatek-pcie.txt | 4 - compatible: Should contain one of the following strings:
5 "mediatek,mt2701-pcie"
6 "mediatek,mt2712-pcie"
7 "mediatek,mt7622-pcie"
8 "mediatek,mt7623-pcie"
9 "mediatek,mt7629-pcie"
10 "airoha,en7523-pcie"
11 - device_type: Must be "pci"
12 - reg: Base addresses and lengths of the root ports.
13 - reg-names: Names of the above areas to use during resource lookup.
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| /freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/ |
| H A D | msi-controller.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/msi-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MSI controller
10 - Marc Zyngier <maz@kernel.org>
13 An MSI controller signals interrupts to a CPU when a write is made
14 to an MMIO address by some master. An MSI controller may feature a
18 "#msi-cells":
20 The number of cells in an msi-specifier, required if not zero.
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| H A D | msi.txt | 1 This document describes the generic device tree binding for MSI controllers and
9 those busses to the MSI controllers which they are capable of using,
14 - The doorbell (the MMIO address written to).
17 they can address. An MSI controller may feature a number of doorbells.
19 - The payload (the value written to the doorbell).
22 MSI controllers may have restrictions on permitted payloads.
24 - Sideband information accompanying the write.
28 MSI controller and device rather than a property of either in isolation).
31 MSI controllers:
34 An MSI controller signals interrupts to a CPU when a write is made to an MMIO
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| /freebsd/sys/contrib/device-tree/Bindings/misc/ |
| H A D | fsl,qoriq-mc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/misc/fsl,qoriq-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
13 The Freescale Management Complex (fsl-mc) is a hardware resource
15 network-oriented packet processing applications. After the fsl-mc
22 For an overview of the DPAA2 architecture and fsl-mc bus see:
26 same hardware "isolation context" and a 10-bit value called an ICID
31 between ICIDs and IOMMUs, so an iommu-map property is used to define
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| H A D | fsl,qoriq-mc.txt | 3 The Freescale Management Complex (fsl-mc) is a hardware resource
5 network-oriented packet processing applications. After the fsl-mc
12 For an overview of the DPAA2 architecture and fsl-mc bus see:
16 same hardware "isolation context" and a 10-bit value called an ICID
21 between ICIDs and IOMMUs, so an iommu-map property is used to define
28 For arm-smmu binding, see:
31 The MSI writes are accompanied by sideband data which is derived from the ICID.
32 The msi-map property is used to associate the devices with both the ITS
35 For generic MSI bindings, see
36 Documentation/devicetree/bindings/interrupt-controller/msi.txt.
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| /freebsd/sys/contrib/device-tree/Bindings/net/wireless/ |
| H A D | qcom,ath10k.txt | 4 - compatible: Should be one of the following:
6 * "qcom,ipq4019-wifi"
7 * "qcom,wcn3990-wifi"
10 data along with board specific data via "qcom,ath10k-calibration-data".
13 AHB based devices (i.e. ipq4019) uses compatible string "qcom,ipq4019-wifi"
15 "qcom,ath10k-calibration-data"). It uses "qcom,ath10k-pre-calibration-data"
18 In general, entry "qcom,ath10k-pre-calibration-data" and
19 "qcom,ath10k-calibration-data" conflict with each other and only one
22 SNOC based devices (i.e. wcn3990) uses compatible string "qcom,wcn3990-wifi".
24 - reg: Address and length of the register set for the device.
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| /freebsd/contrib/llvm-project/clang/lib/Sema/ |
| H A D | SemaCXXScopeSpec.cpp | 1 //===--- SemaCXXScopeSpec.cpp - Semantic Analysis for C++ scope specifiers-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
32 const Type *Ty = T->getCanonicalTypeInternal().getTypePtr(); in getCurrentInstantiationOf()
34 CXXRecordDecl *Record = cast<CXXRecordDecl>(RecordTy->getDecl()); in getCurrentInstantiationOf()
35 if (!Record->isDependentContext() || in getCurrentInstantiationOf()
36 Record->isCurrentInstantiation(CurContext)) in getCurrentInstantiationOf()
41 return cast<InjectedClassNameType>(Ty)->getDecl(); in getCurrentInstantiationOf()
47 if (!T->isDependentType()) in computeDeclContext()
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| H A D | SemaType.cpp | 1 //===--- SemaType.cpp - Semantic Analysis for Types -----------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file implements type-related semantic analysis.
11 //===----------------------------------------------------------------------===//
62 /// isOmittedBlockReturnType - Return true if this declarator is missing a
79 /// diagnoseBadTypeAttribute - Diagnoses a type attribute which
100 StringRef name = attr.getAttrName()->getName(); in diagnoseBadTypeAttribute()
102 // The GC attributes are usually written with macros; special-case them. in diagnoseBadTypeAttribute()
103 IdentifierInfo *II = attr.isArgIdent(0) ? attr.getArgAsIdent(0)->Ident in diagnoseBadTypeAttribute()
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| /freebsd/contrib/llvm-project/clang/lib/AST/ |
| H A D | Decl.cpp | 1 //===- Decl.cpp - Declaration AST Node Implementation ---------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
78 return D->getASTContext().getPrimaryMergedDecl(D); in getPrimaryMergedDecl()
82 SourceLocation Loc = this->Loc; in print()
83 if (!Loc.isValid() && TheDecl) Loc = TheDecl->getLocation(); in print()
92 ND->getNameForDiagnostic(OS, Context.getPrintingPolicy(), true); in print()
101 return !getLexicalDeclContext()->Equals(getDeclContext()); in isOutOfLine()
108 //===----------------------------------------------------------------------===//
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| /freebsd/sys/dev/ofw/ |
| H A D | ofw_bus_subr.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org>.
59 if ((OF_getprop_alloc(node, "name", (void **)&obd->obd_name)) == -1) in ofw_bus_gen_setup_devinfo()
61 OF_getprop_alloc(node, "compatible", (void **)&obd->obd_compat); in ofw_bus_gen_setup_devinfo()
62 OF_getprop_alloc(node, "device_type", (void **)&obd->obd_type); in ofw_bus_gen_setup_devinfo()
63 OF_getprop_alloc(node, "model", (void **)&obd->obd_model); in ofw_bus_gen_setup_devinfo()
64 OF_getprop_alloc(node, "status", (void **)&obd->obd_status); in ofw_bus_gen_setup_devinfo()
65 obd->obd_node = node; in ofw_bus_gen_setup_devinfo()
75 if (obd->obd_compat != NULL) in ofw_bus_gen_destroy_devinfo()
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| /freebsd/contrib/file/ |
| H A D | ChangeLog | 1 2024-11-27 14:44 Christos Zoulas <christos@zoulas.com>
6 2024-11-25 13:56 Christos Zoulas <christos@zoulas.com>
10 2024-11-10 13:56 Christos Zoulas <christos@zoulas.com>
14 offset that the "use" starts so that we don't double-count it.
17 2024-11-09 19:30 Christos Zoulas <christos@zoulas.com>
21 2024-11-02 14:34 Christos Zoulas <christos@zoulas.com>
25 2023-12-29 12:55 Christos Zoulas <christos@zoulas.com>
29 2023-07-29 12:55 Christos Zoulas <christos@zoulas.com>
33 2023-07-27 15:45 Christos Zoulas <christos@zoulas.com>
37 2023-07-17 11:53 Christos Zoulas <christos@zoulas.com>
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| /freebsd/contrib/llvm-project/clang/lib/Serialization/ |
| H A D | ASTReaderDecl.cpp | 1 //===- ASTReaderDecl.cpp - Decl Deserialization ---------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
78 //===----------------------------------------------------------------------===//
80 //===----------------------------------------------------------------------===//
108 return LocalOffset ? Loc.Offset - LocalOffset : 0; in ReadLocalOffset()
272 ASTContext &C = D->getASTContext(); in AddLazySpecializations()
274 auto *&LazySpecializations = D->getCommonPtr()->LazySpecializations; in AddLazySpecializations()
322 Cat->NextClassCategory = Next; in setNextObjCCategory()
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