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/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dmsi.txt1 This document describes the generic device tree binding for MSI controllers and
9 those busses to the MSI controllers which they are capable of using,
14 - The doorbell (the MMIO address written to).
17 they can address. An MSI controller may feature a number of doorbells.
19 - The payload (the value written to the doorbell).
22 MSI controllers may have restrictions on permitted payloads.
24 - Sideband information accompanying the write.
28 MSI controller and device rather than a property of either in isolation).
31 MSI controllers:
34 An MSI controller signals interrupts to a CPU when a write is made to an MMIO
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H A Dfsl,ls-msi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,ls-msi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale Layerscape SCFG PCIe MSI controller
11 is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
12 platforms. If interrupt-parent is not provided, the default parent interrupt
15 Each PCIe node needs to have property msi-parent that points to
16 MSI controller node
19 - Frank Li <Frank.Li@nxp.com>
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H A Dloongson,pch-msi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/loongson,pch-msi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Loongson PCH MSI Controller
10 - Jiaxun Yang <jiaxun.yang@flygoat.com>
14 transforming interrupts from PCIe MSI into HyperTransport vectorized
19 const: loongson,pch-msi-1.0
24 loongson,msi-base-vec:
26 u32 value of the base of parent HyperTransport vector allocated
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H A Dal,alpine-msix.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/al,alpine-msix.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Antoine Tenart <atenart@kernel.org>
14 const: al,alpine-msix
19 interrupt-parent: true
21 msi-controller: true
23 al,msi-base-spi:
24 description: SPI base of the MSI frame
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/linux/kernel/irq/
H A Dmsi.c1 // SPDX-License-Identifier: GPL-2.0
14 #include <linux/msi.h>
26 * struct msi_device_data - MSI per device data
27 * @properties: MSI properties which are interesting to drivers
28 * @mutex: Mutex protecting the MSI descriptor store
29 * @__domains: Internal data for per device MSI domains
40 * struct msi_ctrl - MSI internal management control structure
45 * than the range due to PCI/multi-MSI.
55 #define MSI_XA_MAX_INDEX (ULONG_MAX - 1)
66 * msi_alloc_desc - Allocate an initialized msi_desc
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/linux/drivers/irqchip/
H A Dirq-loongson-pch-msi.c1 // SPDX-License-Identifier: GPL-2.0
4 * Loongson PCH MSI support
7 #define pr_fmt(fmt) "pch-msi: " fmt
10 #include <linux/msi.h>
18 #include <linux/irqchip/irq-msi-lib.h>
19 #include "irq-loongson.h"
37 mutex_lock(&priv->msi_map_lock); in pch_msi_allocate_hwirq()
39 first = bitmap_find_free_region(priv->msi_map, priv->num_irqs, in pch_msi_allocate_hwirq()
42 mutex_unlock(&priv->msi_map_lock); in pch_msi_allocate_hwirq()
43 return -ENOSPC; in pch_msi_allocate_hwirq()
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H A Dirq-bcm2712-mip.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/msi.h>
14 #include <linux/irqchip/irq-msi-lib.h>
30 * struct mip_priv - MSI-X interrupt controller data
33 * @msg_addr: PCIe MSI-X address
34 * @msi_base: MSI base
36 * @msi_offset: MSI offset
38 * @parent: Parent domain (GIC)
49 struct irq_domain *parent; member
57 msg->address_hi = upper_32_bits(mip->msg_addr); in mip_compose_msi_msg()
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H A Dirq-gic-v2m.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * ARM GIC v2m MSI(-X) support
21 #include <linux/msi.h>
26 #include <linux/irqchip/arm-gic.h>
27 #include <linux/irqchip/arm-gic-common.h>
29 #include <linux/irqchip/irq-msi-lib.h>
34 * [25:16] lowest SPI assigned to MSI
36 * [9:0] Numer of SPIs assigned to MSI
52 /* APM X-Gene with GICv2m MSI_IIDR register value */
73 unsigned long *bm; /* MSI vector bitmap */
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H A Dirq-alpine-msi.c6 * Antoine Tenart <antoine.tenart@free-electrons.com>
16 #include <linux/irqchip/arm-gic.h>
17 #include <linux/irqchip/irq-msi-lib.h>
18 #include <linux/msi.h>
27 #include <asm/msi.h>
44 guard(spinlock)(&priv->msi_map_lock); in alpine_msix_allocate_sgi()
45 first = bitmap_find_next_zero_area(priv->msi_map, priv->num_spis, 0, num_req, 0); in alpine_msix_allocate_sgi()
46 if (first >= priv->num_spis) in alpine_msix_allocate_sgi()
47 return -ENOSPC; in alpine_msix_allocate_sgi()
49 bitmap_set(priv->msi_map, first, num_req); in alpine_msix_allocate_sgi()
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H A Dirq-ls-scfg-msi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Freescale SCFG MSI(-X) support
12 #include <linux/msi.h>
17 #include <linux/irqchip/irq-msi-lib.h>
50 struct irq_domain *parent; member
70 .prefix = "MSI-",
78 if (p && strncmp(p, "no-affinity", 11) == 0) in early_parse_ls_scfg_msi()
91 msg->data = data->hwirq; in ls_scfg_msi_compose_msg()
97 msg->data |= cpumask_first(mask); in ls_scfg_msi_compose_msg()
101 msi_data->msiir_addr); in ls_scfg_msi_compose_msg()
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/linux/drivers/of/
H A Dirq.c1 // SPDX-License-Identifier: GPL-2.0+
6 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
8 * Copyright (C) 1996-2001 Cort Dougan
32 * irq_of_parse_and_map - Parse and map an interrupt into linux virq space
55 * of_irq_find_parent - Given a device node, find its interrupt parent node
58 * Return: A pointer to the interrupt parent node with refcount increased
59 * or NULL if the interrupt parent could not be determined.
64 phandle parent; in of_irq_find_parent() local
70 if (of_property_read_u32(child, "interrupt-parent", &parent)) { in of_irq_find_parent()
76 p = of_find_node_by_phandle(parent); in of_irq_find_parent()
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/linux/drivers/base/
H A Dplatform-msi.c1 // SPDX-License-Identifier: GPL-2.0
3 * MSI framework for platform devices
12 #include <linux/msi.h>
21 irq_write_msi_msg_t cb = d->chip_data; in platform_msi_write_msi_msg()
28 arg->desc = desc; in platform_msi_set_desc()
29 arg->hwirq = desc->msi_index; in platform_msi_set_desc()
38 /* The rest is filled in by the platform MSI parent */
51 * platform_device_msi_init_and_alloc_irqs - Initialize platform device MSI
60 * This creates a MSI domain on @dev which has @dev->msi.domain as
61 * parent. The parent domain sets up the new domain. The domain has
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/linux/arch/arm64/boot/dts/marvell/
H A Darmada-ap810-ap0.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 /dts-v1/;
13 #address-cells = <2>;
14 #size-cells = <2>;
15 interrupt-parent = <&gic>;
23 compatible = "arm,psci-0.2";
28 compatible = "arm,armv8-timer";
36 #address-cells = <2>;
37 #size-cells = <2>;
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H A Darmada-ap80x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/thermal.h>
11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cells = <2>;
25 compatible = "arm,psci-0.2";
29 reserved-memory {
30 #address-cells = <2>;
31 #size-cells = <2>;
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/linux/arch/riscv/boot/dts/sophgo/
H A Dsg2044.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 #include <dt-bindings/clock/sophgo,sg2044-pll.h>
7 #include <dt-bindings/clock/sophgo,sg2044-clk.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/pinctrl/pinctrl-sg2044.h>
12 #include "sg2044-cpus.dtsi"
13 #include "sg2044-reset.h"
24 compatible = "fixed-clock";
25 clock-output-names = "osc";
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/linux/drivers/bus/fsl-mc/
H A Dfsl-mc-msi.c1 // SPDX-License-Identifier: GPL-2.0
3 * Freescale Management Complex (MC) bus driver MSI support
5 * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
13 #include <linux/msi.h>
16 #include "fsl-mc-private.h"
20 * Generate a unique ID identifying the interrupt (only used within the MSI
30 return (irq_hw_number_t)(desc->msi_index + (dev->icid * 10000)); in fsl_mc_domain_calc_hwirq()
36 arg->desc = desc; in fsl_mc_msi_set_desc()
37 arg->hwirq = fsl_mc_domain_calc_hwirq(to_fsl_mc_device(desc->dev), in fsl_mc_msi_set_desc()
46 struct msi_domain_ops *ops = info->ops; in fsl_mc_msi_update_dom_ops()
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/linux/arch/x86/kernel/apic/
H A Dmsi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Support of MSI, HPET and DMAR interrupts.
16 #include <linux/msi.h>
31 irq_data_get_irq_chip(irqd)->irq_write_msi_msg(irqd, msg); in irq_msi_update_msg()
38 struct irq_data *parent = irqd->parent_data; in msi_set_affinity() local
47 ret = parent->chip->irq_set_affinity(parent, mask, force); in msi_set_affinity()
52 * For non-maskable and non-remapped MSI interrupts the migration in msi_set_affinity()
55 * caused by the non-atomic update of the address/data pair. in msi_set_affinity()
58 * - The MSI is maskable (remapped MSI does not use this code path). in msi_set_affinity()
60 * - The new vector is the same as the old vector in msi_set_affinity()
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/linux/Documentation/devicetree/bindings/pci/
H A Dapple,pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Kettenis <kettenis@openbsd.org>
26 the standard "reset-gpios" and "max-link-speed" properties appear on
38 - items:
39 - enum:
40 - apple,t8103-pcie
41 - apple,t8112-pcie
42 - apple,t6000-pcie
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H A Dxlnx,nwl-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/xlnx,nwl-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thippeswamy Havalige <thippeswamy.havalige@amd.com>
13 - $ref: /schemas/pci/pci-host-bridge.yaml#
14 - $ref: /schemas/interrupt-controller/msi-controller.yaml#
18 const: xlnx,nwl-pcie-2.11
22 - description: PCIe bridge registers location.
23 - description: PCIe Controller registers location.
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/linux/arch/mips/boot/dts/loongson/
H A Dloongson64c_4core_ls7a.dts1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include "loongson64c-package.dtsi"
6 #include "ls7a-pch.dtsi"
9 compatible = "loongson,loongson64c-4core-ls7a";
13 htvec: interrupt-controller@efdfb000080 {
14 compatible = "loongson,htvec-1.0";
16 interrupt-controller;
17 #interrupt-cells = <1>;
19 interrupt-parent = <&liointc>;
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H A Dloongson64g_4core_ls7a.dts1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include "loongson64g-package.dtsi"
6 #include "ls7a-pch.dtsi"
9 compatible = "loongson,loongson64g-4core-ls7a";
13 htvec: interrupt-controller@efdfb000080 {
14 compatible = "loongson,htvec-1.0";
16 interrupt-controller;
17 #interrupt-cells = <1>;
19 interrupt-parent = <&liointc>;
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/linux/arch/arm64/boot/dts/hisilicon/
H A Dhip07.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip07-d05";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
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/linux/Documentation/devicetree/bindings/perf/
H A Darm,smmu-v3-pmcg.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/perf/arm,smmu-v3-pmcg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Will Deacon <will@kernel.org>
11 - Robin Murphy <robin.murphy@arm.com>
20 pattern: "^pmu@[0-9a-f]*"
23 - items:
24 - const: arm,mmu-600-pmcg
25 - const: arm,smmu-v3-pmcg
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/linux/Documentation/devicetree/bindings/dma/
H A Dmarvell,xor-v2.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/dma/marvell,xor-v2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
15 - const: marvell,xor-v2
16 - items:
17 - enum:
18 - marvell,armada-7k-xor
19 - const: marvell,xor-v2
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/linux/arch/loongarch/boot/dts/
H A Dloongson-2k2000.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/clock/loongson,ls2k-clk.h>
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <1>;
17 #size-cells = <0>;
34 ref_100m: clock-ref-100m {
35 compatible = "fixed-clock";
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