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/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dmsi.txt1 This document describes the generic device tree binding for MSI controllers and
9 those busses to the MSI controllers which they are capable of using,
14 - The doorbell (the MMIO address written to).
17 they can address. An MSI controller may feature a number of doorbells.
19 - The payload (the value written to the doorbell).
22 MSI controllers may have restrictions on permitted payloads.
24 - Sideband information accompanying the write.
28 MSI controller and device rather than a property of either in isolation).
31 MSI controllers:
34 An MSI controller signals interrupts to a CPU when a write is made to an MMIO
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H A Dfsl,ls-msi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,ls-msi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale Layerscape SCFG PCIe MSI controller
11 is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
12 platforms. If interrupt-parent is not provided, the default parent interrupt
15 Each PCIe node needs to have property msi-parent that points to
16 MSI controller node
19 - Frank Li <Frank.Li@nxp.com>
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H A Dloongson,pch-msi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/loongson,pch-msi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Loongson PCH MSI Controller
10 - Jiaxun Yang <jiaxun.yang@flygoat.com>
14 transforming interrupts from PCIe MSI into HyperTransport vectorized
19 const: loongson,pch-msi-1.0
24 loongson,msi-base-vec:
26 u32 value of the base of parent HyperTransport vector allocated
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H A Driscv,aplic.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,aplic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V Advanced Platform Level Interrupt Controller (APLIC)
10 - Anup Patel <anup@brainfault.org>
13 The RISC-V advanced interrupt architecture (AIA) defines an advanced
15 in a RISC-V platform. The RISC-V AIA specification can be found at
16 https://github.com/riscv/riscv-aia.
18 The RISC-V APLIC is implemented as hierarchical APLIC domains where all
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H A Dhisilicon,mbigen-v2.txt6 MBI is kind of msi interrupt only used on Non-PCI devices.
12 Non-pci devices can connect to mbigen and generate the
18 -------------------------------------------
19 - compatible: Should be "hisilicon,mbigen-v2"
21 - reg: Specifies the base physical address and size of the Mbigen
25 ------------------------------------------
26 - interrupt controller: Identifies the node as an interrupt controller
28 - msi-parent: Specifies the MSI controller this mbigen use.
29 For more detail information,please refer to the generic msi-parent binding in
30 Documentation/devicetree/bindings/interrupt-controller/msi.txt.
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/linux/drivers/irqchip/
H A Dirq-msi-lib.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include "irq-msi-lib.h"
10 * msi_lib_init_dev_msi_info - Domain info setup for MSI domains
13 * @real_parent: The real parent domain of the domain to be initialized
18 * This function is to be used for all types of MSI domains above the root
19 * parent domain and any intermediates. The topmost parent domain specific
30 const struct msi_parent_ops *pops = real_parent->msi_parent_ops; in msi_lib_init_dev_msi_info()
33 /* Parent ops available? */ in msi_lib_init_dev_msi_info()
38 * MSI parent domain specific settings. For now there is only the in msi_lib_init_dev_msi_info()
39 * root parent domain, e.g. NEXUS, acting as a MSI parent, but it is in msi_lib_init_dev_msi_info()
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H A Dirq-gic-v3-its-msi-parent.c1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (C) 2013-2015 ARM Limited, All Rights Reserved.
10 #include "irq-gic-common.h"
11 #include "irq-msi-lib.h"
24 int msi, msix, *count = data; in its_pci_msi_vec_count() local
26 msi = max(pci_msi_vec_count(pdev), 0); in its_pci_msi_vec_count()
28 *count += max(msi, msix); in its_pci_msi_vec_count()
50 return -EINVAL; in its_pci_msi_prepare()
61 if (alias_dev->subordinate) in its_pci_msi_prepare()
62 pci_walk_bus(alias_dev->subordinate, in its_pci_msi_prepare()
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H A Dirq-loongson-pch-msi.c1 // SPDX-License-Identifier: GPL-2.0
4 * Loongson PCH MSI support
7 #define pr_fmt(fmt) "pch-msi: " fmt
10 #include <linux/msi.h>
18 #include "irq-msi-lib.h"
19 #include "irq-loongson.h"
37 mutex_lock(&priv->msi_map_lock); in pch_msi_allocate_hwirq()
39 first = bitmap_find_free_region(priv->msi_map, priv->num_irqs, in pch_msi_allocate_hwirq()
42 mutex_unlock(&priv->msi_map_lock); in pch_msi_allocate_hwirq()
43 return -ENOSPC; in pch_msi_allocate_hwirq()
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H A Dirq-gic-v2m.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * ARM GIC v2m MSI(-X) support
21 #include <linux/msi.h>
26 #include <linux/irqchip/arm-gic.h>
27 #include <linux/irqchip/arm-gic-common.h>
29 #include "irq-msi-lib.h"
34 * [25:16] lowest SPI assigned to MSI
36 * [9:0] Numer of SPIs assigned to MSI
52 /* APM X-Gene with GICv2m MSI_IIDR register value */
73 unsigned long *bm; /* MSI vector bitmap */
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H A Dirq-ls-scfg-msi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Freescale SCFG MSI(-X) support
12 #include <linux/msi.h>
49 struct irq_domain *parent; member
61 .name = "MSI",
77 if (p && strncmp(p, "no-affinity", 11) == 0) in early_parse_ls_scfg_msi()
90 msg->address_hi = upper_32_bits(msi_data->msiir_addr); in ls_scfg_msi_compose_msg()
91 msg->address_lo = lower_32_bits(msi_data->msiir_addr); in ls_scfg_msi_compose_msg()
92 msg->data = data->hwirq; in ls_scfg_msi_compose_msg()
98 msg->data |= cpumask_first(mask); in ls_scfg_msi_compose_msg()
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H A Dirq-imx-mu-msi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Freescale MU used as MSI controller
10 * Based on drivers/mailbox/imx-mailbox.c
20 #include <linux/msi.h>
27 #include "irq-msi-lib.h"
52 #define IMX_MU_xCR_RIEn(data, x) ((data->cfg->type) & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
53 #define IMX_MU_xSR_RFn(data, x) ((data->cfg->type) & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
75 iowrite32(val, msi_data->regs + offs); in imx_mu_write()
80 return ioread32(msi_data->regs + offs); in imx_mu_read()
88 raw_spin_lock_irqsave(&msi_data->lock, flags); in imx_mu_xcr_rmw()
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/linux/include/linux/
H A Dmsi.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 * This header file contains MSI data structures and functions which are
8 * - Interrupt core code
9 * - PCI/MSI core code
10 * - MSI interrupt domain implementations
11 * - IOMMU, low level VFIO, NTB and other justified exceptions
12 * dealing with low level MSI details.
15 * especially storing MSI descriptor pointers in random code is considered
26 #include <asm/msi.h>
52 * msi_msg - Representation of a MSI message
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/linux/drivers/cdx/
H A Dcdx_msi.c1 // SPDX-License-Identifier: GPL-2.0
3 * AMD CDX bus driver MSI support
5 * Copyright (C) 2022-2023, Advanced Micro Devices, Inc.
14 #include <linux/msi.h>
22 struct cdx_device *cdx_dev = to_cdx_device(msi_desc->dev); in cdx_msi_write_msg()
27 msi_desc->msg = *msg; in cdx_msi_write_msg()
28 cdx_dev->msi_write_pending = true; in cdx_msi_write_msg()
34 struct cdx_device *cdx_dev = to_cdx_device(msi_desc->dev); in cdx_msi_write_irq_lock()
36 mutex_lock(&cdx_dev->irqchip_lock); in cdx_msi_write_irq_lock()
42 struct cdx_device *cdx_dev = to_cdx_device(msi_desc->dev); in cdx_msi_write_irq_unlock()
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/linux/drivers/pci/msi/
H A Dirqdomain.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCI Message Signaled Interrupt (MSI) - irqdomain support
9 #include "msi.h"
15 domain = dev_get_msi_domain(&dev->dev); in pci_msi_setup_msi_irqs()
17 return msi_domain_alloc_irqs_all_locked(&dev->dev, MSI_DEFAULT_DOMAIN, nvec); in pci_msi_setup_msi_irqs()
26 domain = dev_get_msi_domain(&dev->dev); in pci_msi_teardown_msi_irqs()
28 msi_domain_free_irqs_all_locked(&dev->dev, MSI_DEFAULT_DOMAIN); in pci_msi_teardown_msi_irqs()
31 msi_free_msi_descs(&dev->dev); in pci_msi_teardown_msi_irqs()
36 * pci_msi_domain_write_msg - Helper to write MSI message to PCI config space
37 * @irq_data: Pointer to interrupt data of the MSI interrupt
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/linux/kernel/irq/
H A Dmsi.c1 // SPDX-License-Identifier: GPL-2.0
14 #include <linux/msi.h>
25 * struct msi_device_data - MSI per device data
26 * @properties: MSI properties which are interesting to drivers
27 * @mutex: Mutex protecting the MSI descriptor store
28 * @__domains: Internal data for per device MSI domains
39 * struct msi_ctrl - MSI internal management control structure
44 * than the range due to PCI/multi-MSI.
54 #define MSI_XA_MAX_INDEX (ULONG_MAX - 1)
64 * msi_alloc_desc - Allocate an initialized msi_desc
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/linux/Documentation/devicetree/bindings/pci/
H A Dxgene-pci-msi.txt1 * AppliedMicro X-Gene v1 PCIe MSI controller
5 - compatible: should be "apm,xgene1-msi" to identify
6 X-Gene v1 PCIe MSI controller block.
7 - msi-controller: indicates that this is an X-Gene v1 PCIe MSI controller node
8 - reg: physical base address (0x79000000) and length (0x900000) for controller
9 registers. These registers include the MSI termination address and data
10 registers as well as the MSI interrupt status registers.
11 - reg-names: not required
12 - interrupts: A list of 16 interrupt outputs of the controller, starting from
14 - interrupt-names: not required
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/linux/drivers/of/
H A Dirq.c1 // SPDX-License-Identifier: GPL-2.0+
6 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
8 * Copyright (C) 1996-2001 Cort Dougan
31 * irq_of_parse_and_map - Parse and map an interrupt into linux virq space
50 * of_irq_find_parent - Given a device node, find its interrupt parent node
53 * Return: A pointer to the interrupt parent node, or NULL if the interrupt
54 * parent could not be determined.
59 phandle parent; in of_irq_find_parent() local
65 if (of_property_read_u32(child, "interrupt-parent", &parent)) { in of_irq_find_parent()
71 p = of_find_node_by_phandle(parent); in of_irq_find_parent()
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/linux/drivers/base/
H A Dplatform-msi.c1 // SPDX-License-Identifier: GPL-2.0
3 * MSI framework for platform devices
12 #include <linux/msi.h>
21 irq_write_msi_msg_t cb = d->chip_data; in platform_msi_write_msi_msg()
28 arg->desc = desc; in platform_msi_set_desc()
29 arg->hwirq = desc->msi_index; in platform_msi_set_desc()
38 /* The rest is filled in by the platform MSI parent */
51 * platform_device_msi_init_and_alloc_irqs - Initialize platform device MSI
60 * This creates a MSI domain on @dev which has @dev->msi.domain as
61 * parent. The parent domain sets up the new domain. The domain has
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/linux/arch/arm64/boot/dts/marvell/
H A Darmada-ap810-ap0.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 /dts-v1/;
14 compatible = "marvell,armada-ap810";
15 #address-cells = <2>;
16 #size-cells = <2>;
24 compatible = "arm,psci-0.2";
28 ap810-ap0 {
29 #address-cells = <2>;
30 #size-cells = <2>;
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H A Darmada-ap80x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/thermal.h>
11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cells = <2>;
25 compatible = "arm,psci-0.2";
29 reserved-memory {
30 #address-cells = <2>;
31 #size-cells = <2>;
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/linux/drivers/bus/fsl-mc/
H A Dfsl-mc-msi.c1 // SPDX-License-Identifier: GPL-2.0
3 * Freescale Management Complex (MC) bus driver MSI support
5 * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
13 #include <linux/msi.h>
16 #include "fsl-mc-private.h"
20 * Generate a unique ID identifying the interrupt (only used within the MSI
30 return (irq_hw_number_t)(desc->msi_index + (dev->icid * 10000)); in fsl_mc_domain_calc_hwirq()
36 arg->desc = desc; in fsl_mc_msi_set_desc()
37 arg->hwirq = fsl_mc_domain_calc_hwirq(to_fsl_mc_device(desc->dev), in fsl_mc_msi_set_desc()
46 struct msi_domain_ops *ops = info->ops; in fsl_mc_msi_update_dom_ops()
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/linux/drivers/pci/controller/
H A Dpcie-rcar-host.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe driver for Renesas R-Car SoCs
4 * Copyright (C) 2014-2020 Renesas Electronics Europe Ltd
7 * arch/sh/drivers/pci/pcie-sh7786.c
8 * arch/sh/drivers/pci/ops-sh7786.c
9 * Copyright (C) 2009 - 2011 Paul Mundt
16 #include <linux/clk-provider.h>
24 #include <linux/msi.h>
34 #include "pcie-rcar.h"
50 struct rcar_msi msi; member
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/linux/arch/arm64/boot/dts/broadcom/northstar2/
H A Dns2.dtsi35 #include <dt-bindings/interrupt-controller/arm-gic.h>
36 #include <dt-bindings/clock/bcm-ns2.h>
40 interrupt-parent = <&gic>;
41 #address-cells = <2>;
42 #size-cells = <2>;
45 #address-cells = <2>;
46 #size-cells = <0>;
50 compatible = "arm,cortex-a57";
52 enable-method = "psci";
53 next-level-cache = <&CLUSTER0_L2>;
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/linux/arch/mips/boot/dts/loongson/
H A Dloongson64c_4core_ls7a.dts1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include "loongson64c-package.dtsi"
6 #include "ls7a-pch.dtsi"
9 compatible = "loongson,loongson64c-4core-ls7a";
13 htvec: interrupt-controller@efdfb000080 {
14 compatible = "loongson,htvec-1.0";
16 interrupt-controller;
17 #interrupt-cells = <1>;
19 interrupt-parent = <&liointc>;
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H A Dloongson64g_4core_ls7a.dts1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include "loongson64g-package.dtsi"
6 #include "ls7a-pch.dtsi"
9 compatible = "loongson,loongson64g-4core-ls7a";
13 htvec: interrupt-controller@efdfb000080 {
14 compatible = "loongson,htvec-1.0";
16 interrupt-controller;
17 #interrupt-cells = <1>;
19 interrupt-parent = <&liointc>;
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