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/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dmsi.txt1 This document describes the generic device tree binding for MSI controllers and
9 those busses to the MSI controllers which they are capable of using,
14 - The doorbell (the MMIO address written to).
17 they can address. An MSI controller may feature a number of doorbells.
19 - The payload (the value written to the doorbell).
22 MSI controllers may have restrictions on permitted payloads.
24 - Sideband information accompanying the write.
28 MSI controller and device rather than a property of either in isolation).
31 MSI controllers:
34 An MSI controller signals interrupts to a CPU when a write is made to an MMIO
[all …]
H A Dfsl,ls-msi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,ls-msi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale Layerscape SCFG PCIe MSI controller
11 is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
12 platforms. If interrupt-parent is not provided, the default parent interrupt
15 Each PCIe node needs to have property msi-parent that points to
16 MSI controller node
19 - Frank Li <Frank.Li@nxp.com>
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H A Dloongson,pch-msi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/loongson,pch-msi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Loongson PCH MSI Controller
10 - Jiaxun Yang <jiaxun.yang@flygoat.com>
14 transforming interrupts from PCIe MSI into HyperTransport vectorized
19 const: loongson,pch-msi-1.0
24 loongson,msi-base-vec:
26 u32 value of the base of parent HyperTransport vector allocated
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H A Dal,alpine-msix.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/al,alpine-msix.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Antoine Tenart <atenart@kernel.org>
14 const: al,alpine-msix
19 interrupt-parent: true
21 msi-controller: true
23 al,msi-base-spi:
24 description: SPI base of the MSI frame
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/linux/drivers/irqchip/
H A Dirq-gic-its-msi-parent.c1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (C) 2013-2015 ARM Limited, All Rights Reserved.
11 #include "irq-gic-its-msi-parent.h"
12 #include <linux/irqchip/irq-msi-lib.h>
27 ret = of_property_match_string(msi_node, "reg-names", "ns-translate"); in its_translate_frame_address()
42 int msi, msix, *count = data; in its_pci_msi_vec_count() local
44 msi = max(pci_msi_vec_count(pdev), 0); in its_pci_msi_vec_count()
46 *count += max(msi, msix); in its_pci_msi_vec_count()
68 return -EINVAL; in its_pci_msi_prepare()
79 if (alias_dev->subordinate) in its_pci_msi_prepare()
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H A Dirq-msi-lib.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/irqchip/irq-msi-lib.h>
10 * msi_lib_init_dev_msi_info - Domain info setup for MSI domains
13 * @real_parent: The real parent domain of the domain to be initialized
18 * This function is to be used for all types of MSI domains above the root
19 * parent domain and any intermediates. The topmost parent domain specific
30 const struct msi_parent_ops *pops = real_parent->msi_parent_ops; in msi_lib_init_dev_msi_info()
31 struct irq_chip *chip = info->chip; in msi_lib_init_dev_msi_info()
34 /* Parent ops available? */ in msi_lib_init_dev_msi_info()
39 * MSI parent domain specific settings. For now there is only the in msi_lib_init_dev_msi_info()
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H A Dirq-loongson-pch-msi.c1 // SPDX-License-Identifier: GPL-2.0
4 * Loongson PCH MSI support
7 #define pr_fmt(fmt) "pch-msi: " fmt
10 #include <linux/msi.h>
18 #include <linux/irqchip/irq-msi-lib.h>
19 #include "irq-loongson.h"
37 mutex_lock(&priv->msi_map_lock); in pch_msi_allocate_hwirq()
39 first = bitmap_find_free_region(priv->msi_map, priv->num_irqs, in pch_msi_allocate_hwirq()
42 mutex_unlock(&priv->msi_map_lock); in pch_msi_allocate_hwirq()
43 return -ENOSPC; in pch_msi_allocate_hwirq()
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H A Dirq-bcm2712-mip.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/msi.h>
14 #include <linux/irqchip/irq-msi-lib.h>
30 * struct mip_priv - MSI-X interrupt controller data
33 * @msg_addr: PCIe MSI-X address
34 * @msi_base: MSI base
36 * @msi_offset: MSI offset
38 * @parent: Parent domain (GIC)
49 struct irq_domain *parent; member
57 msg->address_hi = upper_32_bits(mip->msg_addr); in mip_compose_msi_msg()
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H A Dirq-gic-v2m.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * ARM GIC v2m MSI(-X) support
21 #include <linux/msi.h>
26 #include <linux/irqchip/arm-gic.h>
27 #include <linux/irqchip/arm-gic-common.h>
29 #include <linux/irqchip/irq-msi-lib.h>
34 * [25:16] lowest SPI assigned to MSI
36 * [9:0] Numer of SPIs assigned to MSI
52 /* APM X-Gene with GICv2m MSI_IIDR register value */
73 unsigned long *bm; /* MSI vector bitmap */
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H A Dirq-imx-mu-msi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Freescale MU used as MSI controller
10 * Based on drivers/mailbox/imx-mailbox.c
20 #include <linux/msi.h>
27 #include <linux/irqchip/irq-msi-lib.h>
52 #define IMX_MU_xCR_RIEn(data, x) ((data->cfg->type) & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
53 #define IMX_MU_xSR_RFn(data, x) ((data->cfg->type) & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
75 iowrite32(val, msi_data->regs + offs); in imx_mu_write()
80 return ioread32(msi_data->regs + offs); in imx_mu_read()
88 raw_spin_lock_irqsave(&msi_data->lock, flags); in imx_mu_xcr_rmw()
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H A Dirq-riscv-aplic-main.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/irqchip/riscv-aplic.h>
10 #include <linux/irqchip/riscv-imsic.h>
17 #include "irq-riscv-aplic-main.h"
23 writel(d->hwirq, priv->regs + APLIC_SETIENUM); in aplic_irq_unmask()
30 writel(d->hwirq, priv->regs + APLIC_CLRIENUM); in aplic_irq_mask()
56 return -EINVAL; in aplic_irq_set_type()
59 sourcecfg = priv->regs + APLIC_SOURCECFG_BASE; in aplic_irq_set_type()
60 sourcecfg += (d->hwirq - 1) * sizeof(u32); in aplic_irq_set_type()
69 if (WARN_ON(fwspec->param_count < 2)) in aplic_irqdomain_translate()
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H A Dirq-alpine-msi.c6 * Antoine Tenart <antoine.tenart@free-electrons.com>
16 #include <linux/irqchip/arm-gic.h>
17 #include <linux/irqchip/irq-msi-lib.h>
18 #include <linux/msi.h>
27 #include <asm/msi.h>
44 guard(spinlock)(&priv->msi_map_lock); in alpine_msix_allocate_sgi()
45 first = bitmap_find_next_zero_area(priv->msi_map, priv->num_spis, 0, num_req, 0); in alpine_msix_allocate_sgi()
46 if (first >= priv->num_spis) in alpine_msix_allocate_sgi()
47 return -ENOSPC; in alpine_msix_allocate_sgi()
49 bitmap_set(priv->msi_map, first, num_req); in alpine_msix_allocate_sgi()
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/linux/include/linux/
H A Dmsi.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 * This header file contains MSI data structures and functions which are
8 * - Interrupt core code
9 * - PCI/MSI core code
10 * - MSI interrupt domain implementations
11 * - IOMMU, low level VFIO, NTB and other justified exceptions
12 * dealing with low level MSI details.
15 * especially storing MSI descriptor pointers in random code is considered
26 #include <asm/msi.h>
52 * msi_msg - Representation of a MSI message
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/linux/drivers/cdx/
H A Dcdx_msi.c1 // SPDX-License-Identifier: GPL-2.0
3 * AMD CDX bus driver MSI support
5 * Copyright (C) 2022-2023, Advanced Micro Devices, Inc.
14 #include <linux/msi.h>
22 struct cdx_device *cdx_dev = to_cdx_device(msi_desc->dev); in cdx_msi_write_msg()
27 msi_desc->msg = *msg; in cdx_msi_write_msg()
28 cdx_dev->msi_write_pending = true; in cdx_msi_write_msg()
34 struct cdx_device *cdx_dev = to_cdx_device(msi_desc->dev); in cdx_msi_write_irq_lock()
36 mutex_lock(&cdx_dev->irqchip_lock); in cdx_msi_write_irq_lock()
42 struct cdx_device *cdx_dev = to_cdx_device(msi_desc->dev); in cdx_msi_write_irq_unlock()
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/linux/kernel/irq/
H A Dmsi.c1 // SPDX-License-Identifier: GPL-2.0
14 #include <linux/msi.h>
26 * struct msi_device_data - MSI per device data
27 * @properties: MSI properties which are interesting to drivers
28 * @mutex: Mutex protecting the MSI descriptor store
29 * @__domains: Internal data for per device MSI domains
40 * struct msi_ctrl - MSI internal management control structure
45 * than the range due to PCI/multi-MSI.
55 #define MSI_XA_MAX_INDEX (ULONG_MAX - 1)
66 * msi_alloc_desc - Allocate an initialized msi_desc
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/linux/drivers/base/
H A Dplatform-msi.c1 // SPDX-License-Identifier: GPL-2.0
3 * MSI framework for platform devices
12 #include <linux/msi.h>
21 irq_write_msi_msg_t cb = d->chip_data; in platform_msi_write_msi_msg()
28 arg->desc = desc; in platform_msi_set_desc()
29 arg->hwirq = desc->msi_index; in platform_msi_set_desc()
38 /* The rest is filled in by the platform MSI parent */
51 * platform_device_msi_init_and_alloc_irqs - Initialize platform device MSI
60 * This creates a MSI domain on @dev which has @dev->msi.domain as
61 * parent. The parent domain sets up the new domain. The domain has
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/linux/drivers/pci/endpoint/
H A Dpci-ep-msi.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCI Endpoint *Controller* (EPC) MSI library
13 #include <linux/msi.h>
15 #include <linux/pci-epc.h>
16 #include <linux/pci-epf.h>
17 #include <linux/pci-ep-cfs.h>
18 #include <linux/pci-ep-msi.h>
30 epf = list_first_entry_or_null(&epc->pci_epf, struct pci_epf, list); in pci_epf_write_msi_msg()
32 if (epf && epf->db_msg && desc->msi_index < epf->num_db) in pci_epf_write_msi_msg()
33 memcpy(&epf->db_msg[desc->msi_index].msg, msg, sizeof(*msg)); in pci_epf_write_msi_msg()
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/linux/arch/arm64/boot/dts/marvell/
H A Darmada-ap810-ap0.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 /dts-v1/;
13 #address-cells = <2>;
14 #size-cells = <2>;
15 interrupt-parent = <&gic>;
23 compatible = "arm,psci-0.2";
28 compatible = "arm,armv8-timer";
36 #address-cells = <2>;
37 #size-cells = <2>;
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H A Darmada-ap80x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/thermal.h>
11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cells = <2>;
25 compatible = "arm,psci-0.2";
29 reserved-memory {
30 #address-cells = <2>;
31 #size-cells = <2>;
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/linux/arch/riscv/boot/dts/sophgo/
H A Dsg2044.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 #include <dt-bindings/clock/sophgo,sg2044-pll.h>
7 #include <dt-bindings/clock/sophgo,sg2044-clk.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/pinctrl/pinctrl-sg2044.h>
12 #include "sg2044-cpus.dtsi"
13 #include "sg2044-reset.h"
24 compatible = "fixed-clock";
25 clock-output-names = "osc";
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/linux/drivers/bus/fsl-mc/
H A Dfsl-mc-msi.c1 // SPDX-License-Identifier: GPL-2.0
3 * Freescale Management Complex (MC) bus driver MSI support
5 * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
13 #include <linux/msi.h>
16 #include "fsl-mc-private.h"
20 * Generate a unique ID identifying the interrupt (only used within the MSI
30 return (irq_hw_number_t)(desc->msi_index + (dev->icid * 10000)); in fsl_mc_domain_calc_hwirq()
36 arg->desc = desc; in fsl_mc_msi_set_desc()
37 arg->hwirq = fsl_mc_domain_calc_hwirq(to_fsl_mc_device(desc->dev), in fsl_mc_msi_set_desc()
46 struct msi_domain_ops *ops = info->ops; in fsl_mc_msi_update_dom_ops()
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/linux/arch/x86/kernel/apic/
H A Dmsi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Support of MSI, HPET and DMAR interrupts.
16 #include <linux/msi.h>
31 irq_data_get_irq_chip(irqd)->irq_write_msi_msg(irqd, msg); in irq_msi_update_msg()
38 struct irq_data *parent = irqd->parent_data; in msi_set_affinity() local
47 ret = parent->chip->irq_set_affinity(parent, mask, force); in msi_set_affinity()
52 * For non-maskable and non-remapped MSI interrupts the migration in msi_set_affinity()
55 * caused by the non-atomic update of the address/data pair. in msi_set_affinity()
58 * - The MSI is maskable (remapped MSI does not use this code path). in msi_set_affinity()
60 * - The new vector is the same as the old vector in msi_set_affinity()
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/linux/Documentation/devicetree/bindings/pci/
H A Dapple,pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Kettenis <kettenis@openbsd.org>
26 the standard "reset-gpios" and "max-link-speed" properties appear on
38 - items:
39 - enum:
40 - apple,t8103-pcie
41 - apple,t8112-pcie
42 - apple,t6000-pcie
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/linux/arch/mips/boot/dts/loongson/
H A Dloongson64c_4core_ls7a.dts1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include "loongson64c-package.dtsi"
6 #include "ls7a-pch.dtsi"
9 compatible = "loongson,loongson64c-4core-ls7a";
13 htvec: interrupt-controller@efdfb000080 {
14 compatible = "loongson,htvec-1.0";
16 interrupt-controller;
17 #interrupt-cells = <1>;
19 interrupt-parent = <&liointc>;
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H A Dloongson64g_4core_ls7a.dts1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include "loongson64g-package.dtsi"
6 #include "ls7a-pch.dtsi"
9 compatible = "loongson,loongson64g-4core-ls7a";
13 htvec: interrupt-controller@efdfb000080 {
14 compatible = "loongson,htvec-1.0";
16 interrupt-controller;
17 #interrupt-cells = <1>;
19 interrupt-parent = <&liointc>;
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