1 // SPDX-License-Identifier: GPL-2.0-only
3  * Freescale MU used as MSI controller
10  * Based on drivers/mailbox/imx-mailbox.c
20 #include <linux/msi.h>
27 #include "irq-msi-lib.h"
52 #define IMX_MU_xCR_RIEn(data, x) ((data->cfg->type) & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
53 #define IMX_MU_xSR_RFn(data, x) ((data->cfg->type) & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
75 	iowrite32(val, msi_data->regs + offs);  in imx_mu_write()
80 	return ioread32(msi_data->regs + offs);  in imx_mu_read()
88 	raw_spin_lock_irqsave(&msi_data->lock, flags);  in imx_mu_xcr_rmw()
89 	val = imx_mu_read(msi_data, msi_data->cfg->xCR[type]);  in imx_mu_xcr_rmw()
92 	imx_mu_write(msi_data, val, msi_data->cfg->xCR[type]);  in imx_mu_xcr_rmw()
93 	raw_spin_unlock_irqrestore(&msi_data->lock, flags);  in imx_mu_xcr_rmw()
102 	imx_mu_xcr_rmw(msi_data, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(msi_data, data->hwirq));  in imx_mu_msi_parent_mask_irq()
109 	imx_mu_xcr_rmw(msi_data, IMX_MU_RCR, IMX_MU_xCR_RIEn(msi_data, data->hwirq), 0);  in imx_mu_msi_parent_unmask_irq()
116 	imx_mu_read(msi_data, msi_data->cfg->xRR + data->hwirq * 4);  in imx_mu_msi_parent_ack_irq()
123 	u64 addr = msi_data->msiir_addr + 4 * data->hwirq;  in imx_mu_msi_parent_compose_msg()
125 	msg->address_hi = upper_32_bits(addr);  in imx_mu_msi_parent_compose_msg()
126 	msg->address_lo = lower_32_bits(addr);  in imx_mu_msi_parent_compose_msg()
127 	msg->data = data->hwirq;  in imx_mu_msi_parent_compose_msg()
133 	return -EINVAL;  in imx_mu_msi_parent_set_affinity()
150 	struct imx_mu_msi *msi_data = domain->host_data;  in imx_mu_msi_domain_irq_alloc()
156 	raw_spin_lock_irqsave(&msi_data->lock, flags);  in imx_mu_msi_domain_irq_alloc()
157 	pos = find_first_zero_bit(&msi_data->used, IMX_MU_CHANS);  in imx_mu_msi_domain_irq_alloc()
159 		__set_bit(pos, &msi_data->used);  in imx_mu_msi_domain_irq_alloc()
161 		err = -ENOSPC;  in imx_mu_msi_domain_irq_alloc()
162 	raw_spin_unlock_irqrestore(&msi_data->lock, flags);  in imx_mu_msi_domain_irq_alloc()
180 	raw_spin_lock_irqsave(&msi_data->lock, flags);  in imx_mu_msi_domain_irq_free()
181 	__clear_bit(d->hwirq, &msi_data->used);  in imx_mu_msi_domain_irq_free()
182 	raw_spin_unlock_irqrestore(&msi_data->lock, flags);  in imx_mu_msi_domain_irq_free()
198 	status = imx_mu_read(msi_data, msi_data->cfg->xSR[IMX_MU_RSR]);  in imx_mu_msi_irq_handler()
203 			generic_handle_domain_irq(msi_data->msi_domain, i);  in imx_mu_msi_irq_handler()
219 	.prefix			= "MU-MSI-",
226 	struct irq_domain *parent;  in imx_mu_msi_domains_init()  local
228 	/* Initialize MSI domain parent */  in imx_mu_msi_domains_init()
229 	parent = irq_domain_create_linear(fwnodes, IMX_MU_CHANS,  in imx_mu_msi_domains_init()
231 	if (!parent) {  in imx_mu_msi_domains_init()
233 		return -ENOMEM;  in imx_mu_msi_domains_init()
236 	irq_domain_update_bus_token(parent, DOMAIN_BUS_NEXUS);  in imx_mu_msi_domains_init()
237 	parent->dev = parent->pm_dev = dev;  in imx_mu_msi_domains_init()
238 	parent->flags |= IRQ_DOMAIN_FLAG_MSI_PARENT;  in imx_mu_msi_domains_init()
239 	parent->msi_parent_ops = &imx_mu_msi_parent_ops;  in imx_mu_msi_domains_init()
299 				 struct device_node *parent,  in imx_mu_of_init()  argument
313 	dev = &pdev->dev;  in imx_mu_of_init()
315 	msi_data = devm_kzalloc(&pdev->dev, sizeof(*msi_data), GFP_KERNEL);  in imx_mu_of_init()
317 		return -ENOMEM;  in imx_mu_of_init()
319 	msi_data->cfg = cfg;  in imx_mu_of_init()
321 	msi_data->regs = devm_platform_ioremap_resource_byname(pdev, "processor-a-side");  in imx_mu_of_init()
322 	if (IS_ERR(msi_data->regs)) {  in imx_mu_of_init()
323 		dev_err(&pdev->dev, "failed to initialize 'regs'\n");  in imx_mu_of_init()
324 		return PTR_ERR(msi_data->regs);  in imx_mu_of_init()
327 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "processor-b-side");  in imx_mu_of_init()
329 		return -EIO;  in imx_mu_of_init()
331 	msi_data->msiir_addr = res->start + msi_data->cfg->xTR;  in imx_mu_of_init()
339 	msi_data->clk = devm_clk_get(dev, NULL);  in imx_mu_of_init()
340 	if (IS_ERR(msi_data->clk))  in imx_mu_of_init()
341 		return PTR_ERR(msi_data->clk);  in imx_mu_of_init()
343 	pd_a = dev_pm_domain_attach_by_name(dev, "processor-a-side");  in imx_mu_of_init()
347 	pd_b = dev_pm_domain_attach_by_name(dev, "processor-b-side");  in imx_mu_of_init()
389 	return -EINVAL;  in imx_mu_of_init()
396 	clk_disable_unprepare(priv->clk);  in imx_mu_runtime_suspend()
406 	ret = clk_prepare_enable(priv->clk);  in imx_mu_runtime_resume()
419 					 struct device_node *parent)  in imx_mu_imx7ulp_of_init()  argument
421 	return imx_mu_of_init(dn, parent, &imx_mu_cfg_imx7ulp);  in imx_mu_imx7ulp_of_init()
425 					struct device_node *parent)  in imx_mu_imx6sx_of_init()  argument
427 	return imx_mu_of_init(dn, parent, &imx_mu_cfg_imx6sx);  in imx_mu_imx6sx_of_init()
431 					 struct device_node *parent)  in imx_mu_imx8ulp_of_init()  argument
433 	return imx_mu_of_init(dn, parent, &imx_mu_cfg_imx8ulp);  in imx_mu_imx8ulp_of_init()
437 IRQCHIP_MATCH("fsl,imx7ulp-mu-msi", imx_mu_imx7ulp_of_init)
438 IRQCHIP_MATCH("fsl,imx6sx-mu-msi", imx_mu_imx6sx_of_init)
439 IRQCHIP_MATCH("fsl,imx8ulp-mu-msi", imx_mu_imx8ulp_of_init)
444 MODULE_DESCRIPTION("Freescale MU MSI controller driver");