| /freebsd/share/man/man9/ |
| H A D | pci.9 | 211 at offset
224 at offset
232 function is used to modify the value of a register in the PCI-express
235 The offset
237 specifies a relative offset in the register set with
251 function is used to read the value of a register in the PCI-express
254 The offset
256 specifies a relative offset in the register set with
264 to a register in the PCI-express capability register set of device
266 The offset
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| /freebsd/sys/contrib/device-tree/Bindings/pci/ |
| H A D | brcm,iproc-pcie.txt | 4 - compatible:
5 "brcm,iproc-pcie" for the first generation of PAXB based controller,
7 "brcm,iproc-pcie-paxb-v2" for the second generation of PAXB-based
9 "brcm,iproc-pcie-paxc" for the first generation of PAXC based
11 "brcm,iproc-pcie-paxc-v2" for the second generation of PAXC based
13 PAXB-based root complex is used for external endpoint devices. PAXC-based
15 - reg: base address and length of the PCIe controller I/O register space
16 - #interrupt-cells: set to <1>
17 - interrupt-map-mask and interrupt-map, standard PCI properties to define the
19 - linux,pci-domain: PCI domain ID. Should be unique for each host controller
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| H A D | brcm,iproc-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/brcm,iproc-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ray Jui <ray.jui@broadcom.com>
11 - Scott Branden <scott.branden@broadcom.com>
14 - $ref: /schemas/pci/pci-host-bridge.yaml#
19 - enum:
22 - brcm,iproc-pcie
23 # for the second generation of PAXB-based controllers, used in
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| H A D | mediatek-pcie-gen3.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/mediatek-pcie-gen3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jianjun Wang <jianjun.wang@mediatek.com>
16 This PCIe controller supports up to 256 MSI vectors, the MSI hardware
19 +-----+
21 +-----+
24 port->irq
26 +-+-+-+-+-+-+-+-+
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| /freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/ |
| H A D | arm,gic.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
22 - $ref: /schemas/interrupt-controller.yaml#
27 - items:
28 - enum:
29 - arm,arm11mp-gic
30 - arm,cortex-a15-gic
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| H A D | brcm,bcm2712-msix.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm2712-msix.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom bcm2712 MSI-X Interrupt Peripheral support
10 - Stanimir Varbanov <svarbanov@suse.de>
15 external MSI-X controller for PCIe root complex.
18 - $ref: /schemas/interrupt-controller/msi-controller.yaml#
22 const: brcm,bcm2712-mip
26 - description: Base register address
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| /freebsd/sys/contrib/device-tree/Bindings/misc/ |
| H A D | fsl,qoriq-mc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/misc/fsl,qoriq-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
13 The Freescale Management Complex (fsl-mc) is a hardware resource
15 network-oriented packet processing applications. After the fsl-mc
22 For an overview of the DPAA2 architecture and fsl-mc bus see:
26 same hardware "isolation context" and a 10-bit value called an ICID
31 between ICIDs and IOMMUs, so an iommu-map property is used to define
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| H A D | fsl,qoriq-mc.txt | 3 The Freescale Management Complex (fsl-mc) is a hardware resource
5 network-oriented packet processing applications. After the fsl-mc
12 For an overview of the DPAA2 architecture and fsl-mc bus see:
16 same hardware "isolation context" and a 10-bit value called an ICID
21 between ICIDs and IOMMUs, so an iommu-map property is used to define
28 For arm-smmu binding, see:
31 The MSI writes are accompanied by sideband data which is derived from the ICID.
32 The msi-map property is used to associate the devices with both the ITS
35 For generic MSI bindings, see
36 Documentation/devicetree/bindings/interrupt-controller/msi.txt.
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| /freebsd/sys/amd64/vmm/ |
| H A D | vmm_lapic.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
43 * Some MSI message definitions
99 VM_CTR2(vm, "lapic MSI addr: %#lx msg: %#lx", addr, msg); in lapic_intr_msi()
102 VM_CTR1(vm, "lapic MSI invalid addr %#lx", addr); in lapic_intr_msi()
103 return (-1); in lapic_intr_msi()
107 * Extract the x86-specific fields from the MSI addr/msg in lapic_intr_msi()
111 * MSI/MSI-X so ignore trigger level in 'msg'. in lapic_intr_msi()
119 * Extended Destination ID support uses bits 5-11 of the address: in lapic_intr_msi()
128 VM_CTR3(vm, "lapic MSI %s dest %#x, vec %d", in lapic_intr_msi()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64StackTagging.cpp | 1 //===- AArch64StackTagging.cpp - Stack tagging in IR --===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
8 //===----------------------------------------------------------------------===//
63 #define DEBUG_TYPE "aarch64-stack-tagging"
66 "stack-tagging-merge-init", cl::Hidden, cl::init(true),
70 ClUseStackSafety("stack-tagging-use-stack-safety", cl::Hidden,
74 static cl::opt<unsigned> ClScanLimit("stack-tagging-merge-init-scan-limit",
78 ClMergeInitSizeLimit("stack-tagging-merge-init-size-limit", cl::init(272),
82 "stack-tagging-max-lifetimes-for-alloca", cl::Hidden, cl::init(3),
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| /freebsd/sys/contrib/dev/athk/ath11k/ |
| H A D | pci.c | 1 // SPDX-License-Identifier: BSD-3-Clause-Clear
3 * Copyright (c) 2019-2020 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
8 #include <linux/msi.h>
50 return mhi_device_get_sync(ab_pci->mhi_ctrl->mhi_dev); in ath11k_pci_bus_wake_up()
57 mhi_device_put(ab_pci->mhi_ctrl->mhi_dev); in ath11k_pci_bus_release()
60 static u32 ath11k_pci_get_window_start(struct ath11k_base *ab, u32 offset) in ath11k_pci_get_window_start() argument
62 if (!ab->hw_params.static_window_map) in ath11k_pci_get_window_start()
65 if ((offset ^ HAL_SEQ_WCSS_UMAC_OFFSET) < ATH11K_PCI_WINDOW_RANGE_MASK) in ath11k_pci_get_window_start()
66 /* if offset lies within DP register range, use 3rd window */ in ath11k_pci_get_window_start()
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| H A D | pcic.c | 1 // SPDX-License-Identifier: BSD-3-Clause-Clear
3 * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved.
13 "mhi-er0",
14 "mhi-er1",
27 "host2wbm-desc-feed",
28 "host2reo-re-injection",
29 "host2reo-command",
30 "host2rxdma-monitor-ring3",
31 "host2rxdma-monitor-ring2",
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| /freebsd/share/man/man4/ |
| H A D | vmx.4 | 28 .Bd -ragged -offset indent
36 .Bd -literal -offset indent
61 checksum offloading, MSI/MSI-X support and hardware VLAN tagging in
70 .Bl -bullet -compact -offset indent
88 The number of queues allocated depends on the presence of MSI-X,
92 does not enable MSI-X support on VMware by default.
95 tunable must be disabled to enable MSI-X support.
101 .Bl -tag -width indent
131 .Bd -literal -offset indent
145 .An -nosplit
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| H A D | bxe.4 | 35 .Bd -ragged -offset indent
42 .Bd -literal -offset indent
51 tagging, checksum offload (IPv4, TCP, UDP, IPv6-TCP, IPv6-UDP), MSI-X
60 .Bl -bullet -compact
70 QLogic NetXtreme II BCM57712-MF 10Gb
74 QLogic NetXtreme II BCM57800-MF 10Gb
78 QLogic NetXtreme II BCM57810-MF 10Gb
82 QLogic NetXtreme II BCM57840-MF 10Gb
92 .Bl -tag -width indent
102 Sets the default interrupt mode: 0=IRQ, 1=MSI, 2=MSIX.
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| H A D | vmd.4 | 1 .\"-
2 .\" SPDX-License-Identifier: BSD-2-Clause
37 .Bd -ragged -offset indent
44 .Bd -literal -offset indent
48 This driver attaches to Intel VMD devices, representing them as PCI-to-PCI
57 .Bl -tag -width indent
59 By default all VMD devices remap children MSI/MSI-X interrupts into their
64 Limits number of Message Signaled Interrupt (MSI) vectors allowed to each
66 VMD can't distinguish MSI vectors of the same device, so there are no
71 Limits number of Extended Message Signaled Interrupt (MSI-X) vectors
|
| H A D | ahci.4 | 1 .\" Copyright (c) 2009-2013 Alexander Motin <mav@FreeBSD.org>
35 .Bd -ragged -offset indent
44 .Bd -literal -offset indent
50 .Bl -ohang
51 .It Va hint.ahci. Ns Ar X Ns Va .msi
52 controls Message Signaled Interrupts (MSI) usage by the specified controller.
54 .Bl -tag -width 4n -offset indent -compact
58 single MSI vector used, if supported;
60 multiple MSI vectors used, if supported (default);
64 Non-zero value enables CCC and defines maximum time (in ms), request can wait
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| H A D | mps.4 | 4 .\" Copyright (c) 2015-2017 Avago Technologies
5 .\" Copyright (c) 2015-2017 Broadcom Ltd.
45 .Nd "LSI Fusion-MPT 2 IT/IR 6Gb/s Serial Attached SCSI/SATA driver"
49 .Bd -ragged -offset indent
57 .Bd -literal -offset indent
64 Fusion-MPT 2 IT/IR
72 .Bl -bullet -compact
99 To disable MSI interrupts for all
103 .Bd -literal -offset indent
107 To disable MSI interrupts for a specific
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| /freebsd/usr.sbin/bhyve/ |
| H A D | pci_passthru.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
78 static int pcifd = -1;
117 len = 10; /* minimum length of msi capability */ in msi_caplen()
124 * Ignore the 'mask' and 'pending' bits in the MSI capability. in msi_caplen()
142 return (-1); in pcifd_open()
157 if (caph_rights_limit(pcifd, &pcifd_rights) == -1) in pcifd_init()
162 if (caph_ioctls_limit(pcifd, pcifd_ioctls, nitems(pcifd_ioctls)) == -1) in pcifd_init()
252 * Copy the msi capability structure in the last 16 bytes of the in passthru_add_msicap()
256 capoff = 256 - roundup(sizeof(msicap), 4); in passthru_add_msicap()
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| /freebsd/sys/arm64/arm64/ |
| H A D | gic_v3.c | 1 /*-
2 * Copyright (c) 2015-2016 The FreeBSD Foundation
112 static u_int sgi_to_ipi[GIC_LAST_SGI - GIC_FIRST_SGI + 1];
144 /* MSI/MSI-X */
166 * Driver-specific definitions.
173 /* Destination registers, either Distributor or Re-Distributor */
185 /* be used for MSI/MSI-X interrupts */
187 /* for a MSI/MSI-X interrupt */
220 gic_r_read_4(device_t dev, bus_size_t offset) in gic_r_read_4() argument
226 rdist = sc->gic_redists.pcpu[PCPU_GET(cpuid)].res; in gic_r_read_4()
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| /freebsd/sys/dev/ntb/ntb_hw/ |
| H A D | ntb_hw_amd.c | 1 /*-
46 * The Non-Transparent Bridge (NTB) is a device that allows you to connect
47 * two or more systems using a PCI-e links, providing remote memory access.
89 .desc = "AMD Non-Transparent Bridge"},
99 .desc = "AMD Non-Transparent Bridge"},
109 .desc = "Hygon Non-Transparent Bridge"},
115 PCI_DESCR("AMD Non-Transparent Bridge") },
118 PCI_DESCR("AMD Non-Transparent Bridge") },
121 PCI_DESCR("Hygon Non-Transparent Bridge") }
126 &g_amd_ntb_hw_debug_level, 0, "amd_ntb_hw log level -- higher is verbose");
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| /freebsd/sys/contrib/device-tree/src/arm64/apm/ |
| H A D | apm-shadowcat.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * dts file for AppliedMicro (APM) X-Gene Shadowcat SOC
9 compatible = "apm,xgene-shadowcat";
10 interrupt-parent = <&gic>;
11 #address-cells = <2>;
12 #size-cells = <2>;
15 #address-cells = <2>;
16 #size-cells = <0>;
22 enable-method = "spin-table";
23 cpu-release-addr = <0x1 0x0000fff8>;
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| /freebsd/sys/dev/pci/ |
| H A D | pcib_if.m | 1 #-
72 # argument is a byte offset into configuration space for that
74 # many byte of configuration space to read from that offset.
88 # argument is a byte offset into configuration space for that
113 # Allocate 'count' MSI messages mapped onto 'count' IRQs. 'irq' points
128 # Release 'count' MSI messages mapped onto 'count' IRQs stored in the
139 # Allocate a single MSI-X message mapped onto '*irq'.
148 # Release a single MSI-X message mapped onto 'irq'.
157 # Determine the MSI/MSI-X message address and data for 'irq'. The address
198 # Return non-zero if PCI ARI is enabled, or zero otherwise
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| /freebsd/sys/contrib/device-tree/Bindings/powerpc/4xx/ |
| H A D | hsta.txt | 10 Currently only the MSI support is used by Linux using the following
14 - compatible : "ibm,476gtr-hsta-msi", "ibm,hsta-msi"
15 - reg : register mapping for the HSTA MSI space
16 - interrupts : ordered interrupt mapping for each MSI in the register
18 register offset of 0x00, the second to 0x10, etc.
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| /freebsd/sys/contrib/device-tree/Bindings/powerpc/fsl/ |
| H A D | msi-pic.txt | 1 * Freescale MSI interrupt controller
4 - compatible : compatible list, may contain one or two entries
5 The first is "fsl,CHIP-msi", where CHIP is the processor(mpc8610, mpc8572,
6 etc.) and the second is "fsl,mpic-msi" or "fsl,ipic-msi" or
7 "fsl,mpic-msi-v4.3" depending on the parent type and version. If mpic
8 version is 4.3, the number of MSI registers is increased to 16, MSIIR1 is
9 provided to access these 16 registers, and compatible "fsl,mpic-msi-v4.3"
13 - reg : It may contain one or two regions. The first region should contain
17 region must be added because different MSI group has different MSIIR1 offset.
19 - interrupts : each one of the interrupts here is one entry per 32 MSIs,
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| /freebsd/sys/dev/mvs/ |
| H A D | mvs_pci.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
104 ctlr->dev = dev; in mvs_attach()
110 ctlr->channels = mvs_ids[i].ports; in mvs_attach()
111 ctlr->quirks = mvs_ids[i].quirks; in mvs_attach()
112 ctlr->ccc = 0; in mvs_attach()
114 device_get_unit(dev), "ccc", &ctlr->ccc); in mvs_attach()
115 ctlr->cccc = 8; in mvs_attach()
117 device_get_unit(dev), "cccc", &ctlr->cccc); in mvs_attach()
118 if (ctlr->ccc == 0 || ctlr->cccc == 0) { in mvs_attach()
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