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/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dpci-msi.txt2 relationship between PCI devices and MSI controllers.
18 Requester ID. A mechanism is required to associate a device with both the MSI
22 For generic MSI bindings, see
23 Documentation/devicetree/bindings/interrupt-controller/msi.txt.
30 -------------------
32 - msi-map: Maps a Requester ID to an MSI controller and associated
33 msi-specifier data. The property is an arbitrary number of tuples of
34 (rid-base,msi-controller,msi-base,length), where:
36 * rid-base is a single cell describing the first RID matched by the entry.
38 * msi-controller is a single phandle to an MSI controller
[all …]
H A Dbrcm,iproc-pcie.txt1 * Broadcom iProc PCIe controller with the platform bus interface
4 - compatible:
5 "brcm,iproc-pcie" for the first generation of PAXB based controller,
7 "brcm,iproc-pcie-paxb-v2" for the second generation of PAXB-based
9 "brcm,iproc-pcie-paxc" for the first generation of PAXC based
10 controller, used in NS2
11 "brcm,iproc-pcie-paxc-v2" for the second generation of PAXC based
12 controller, used in Stingray
13 PAXB-based root complex is used for external endpoint devices. PAXC-based
15 - reg: base address and length of the PCIe controller I/O register space
[all …]
H A Dxgene-pci-msi.txt1 * AppliedMicro X-Gene v1 PCIe MSI controller
5 - compatible: should be "apm,xgene1-msi" to identify
6 X-Gene v1 PCIe MSI controller block.
7 - msi-controller: indicates that this is an X-Gene v1 PCIe MSI controller node
8 - reg: physical base address (0x79000000) and length (0x900000) for controller
9 registers. These registers include the MSI termination address and data
10 registers as well as the MSI interrupt status registers.
11 - reg-names: not required
12 - interrupts: A list of 16 interrupt outputs of the controller, starting from
14 - interrupt-names: not required
[all …]
H A Daltr,msi-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/altr,msi-controller.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Altera PCIe MSI controller
11 - Matthew Gerlach <matthew.gerlach@linux.intel.com>
16 - altr,msi-1.0
20 - description: CSR registers
21 - description: Vectors slave port region
23 reg-names:
[all …]
H A Dbrcm,iproc-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/brcm,iproc-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom iProc PCIe controller with the platform bus interface
10 - Ray Jui <ray.jui@broadcom.com>
11 - Scott Branden <scott.branden@broadcom.com>
14 - $ref: /schemas/pci/pci-host-bridge.yaml#
19 - enum:
20 # for the first generation of PAXB based controller, used in SoCs
[all …]
H A Daltera-pcie-msi.txt1 * Altera PCIe MSI controller
4 - compatible: should contain "altr,msi-1.0"
5 - reg: specifies the physical base address of the controller and
7 - reg-names: must include the following entries:
10 - interrupts: specifies the interrupt source of the parent interrupt
11 controller. The format of the interrupt specifier depends on the
12 parent interrupt controller.
13 - num-vectors: number of vectors, range 1 to 32.
14 - msi-controller: indicates that this is MSI controller node
18 msi0: msi@0xFF200000 {
[all …]
H A Dplda,xpressrich3-axi-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/plda,xpressrich3-axi-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Daire McNamara <daire.mcnamara@microchip.com>
11 - Kevin Xie <kevin.xie@starfivetech.com>
17 - $ref: /schemas/pci/pci-host-bridge.yaml#
24 reg-names:
26 - items:
27 - const: cfg
[all …]
H A Dpci-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/pci-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PCI Endpoint Controller
10 Common properties for PCI Endpoint Controller Nodes.
13 - Kishon Vijay Abraham I <kishon@kernel.org>
14 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
18 pattern: "^pcie-ep@"
20 iommu-map:
[all …]
H A Dlayerscape-pcie-gen4.txt1 NXP Layerscape PCIe Gen4 controller
3 This PCIe controller is based on the Mobiveil PCIe IP and thus inherits all
4 the common properties defined in mobiveil-pcie.txt.
7 - compatible: should contain the platform identifier such as:
8 "fsl,lx2160a-pcie"
9 - reg: base addresses and lengths of the PCIe controller register blocks.
11 "config_axi_slave": PCIe controller registers
12 - interrupts: A list of interrupt outputs of the controller. Must contain an
13 entry for each entry in the interrupt-names property.
14 - interrupt-names: It could include the following entries:
[all …]
/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dmsi.txt1 This document describes the generic device tree binding for MSI controllers and
9 those busses to the MSI controllers which they are capable of using,
14 - The doorbell (the MMIO address written to).
17 they can address. An MSI controller may feature a number of doorbells.
19 - The payload (the value written to the doorbell).
22 MSI controllers may have restrictions on permitted payloads.
24 - Sideband information accompanying the write.
28 MSI controller and device rather than a property of either in isolation).
31 MSI controllers:
34 An MSI controller signals interrupts to a CPU when a write is made to an MMIO
[all …]
H A Dfsl,ls-msi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,ls-msi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale Layerscape SCFG PCIe MSI controller
10 This interrupt controller hardware is a second level interrupt controller that
11 is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
12 platforms. If interrupt-parent is not provided, the default parent interrupt
13 controller will be used.
15 Each PCIe node needs to have property msi-parent that points to
[all …]
H A Dfsl,ls-scfg-msi.txt1 * Freescale Layerscape SCFG PCIe MSI controller
5 - compatible: should be "fsl,<soc-name>-msi" to identify
6 Layerscape PCIe MSI controller block such as:
7 "fsl,ls1021a-msi"
8 "fsl,ls1043a-msi"
9 "fsl,ls1046a-msi"
10 "fsl,ls1043a-v1.1-msi"
11 "fsl,ls1012a-msi"
12 - msi-controller: indicates that this is a PCIe MSI controller node
13 - reg: physical base address of the controller and length of memory mapped.
[all …]
H A Dsophgo,sg2042-msi.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/sophgo,sg2042-msi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Sophgo SG2042 MSI Controller
10 - Chen Wang <unicorn_wang@outlook.com>
13 This interrupt controller is in Sophgo SG2042 for transforming interrupts from
14 PCIe MSI to PLIC interrupts.
17 - $ref: /schemas/interrupt-controller/msi-controller.yaml#
22 - sophgo,sg2042-msi
[all …]
H A Dloongson,pch-msi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/loongson,pch-msi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Loongson PCH MSI Controller
10 - Jiaxun Yang <jiaxun.yang@flygoat.com>
13 This interrupt controller is found in the Loongson LS7A family of PCH for
14 transforming interrupts from PCIe MSI into HyperTransport vectorized
19 const: loongson,pch-msi-1.0
24 loongson,msi-base-vec:
[all …]
H A Dmsi-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/msi-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MSI controller
10 - Marc Zyngier <maz@kernel.org>
13 An MSI controller signals interrupts to a CPU when a write is made
14 to an MMIO address by some master. An MSI controller may feature a
18 "#msi-cells":
20 The number of cells in an msi-specifier, required if not zero.
[all …]
H A Dfsl,mu-msi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,mu-msi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale/NXP i.MX Messaging Unit (MU) work as msi controller
10 - Frank Li <Frank.Li@nxp.com>
23 registers (Processor A-side, Processor B-side).
25 MU can work as msi interrupt controller to do doorbell
28 - $ref: /schemas/interrupt-controller/msi-controller.yaml#
33 - fsl,imx6sx-mu-msi
[all …]
H A Dbrcm,bcm2712-msix.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm2712-msix.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom bcm2712 MSI-X Interrupt Peripheral support
10 - Stanimir Varbanov <svarbanov@suse.de>
13 This interrupt controller is used to provide interrupt vectors to the
14 generic interrupt controller (GIC) on bcm2712. It will be used as
15 external MSI-X controller for PCIe root complex.
18 - $ref: /schemas/interrupt-controller/msi-controller.yaml#
[all …]
H A Darm,gic-v3.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM Generic Interrupt Controller, version 3
10 - Marc Zyngier <maz@kernel.org>
15 Software Generated Interrupts (SGI), and Locality-specific Peripheral
19 - $ref: /schemas/interrupt-controller.yaml#
24 - items:
25 - enum:
[all …]
H A Driscv,imsics.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,imsics.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V Incoming MSI Controller (IMSIC)
10 - Anup Patel <anup@brainfault.org>
13 The RISC-V advanced interrupt architecture (AIA) defines a per-CPU incoming
14 MSI controller (IMSIC) for handling MSIs in a RISC-V platform. The RISC-V
15 AIA specification can be found at https://github.com/riscv/riscv-aia.
17 The IMSIC is a per-CPU (or per-HART) device with separate interrupt file
[all …]
H A Dal,alpine-msix.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/al,alpine-msix.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Alpine MSIX controller
10 - Antoine Tenart <atenart@kernel.org>
14 const: al,alpine-msix
19 interrupt-parent: true
21 msi-controller: true
23 al,msi-base-spi:
[all …]
H A Daltr,msi-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/interrupt-controller/altr,msi-controller.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Altera PCIe MSI controller
11 - Matthew Gerlach <matthew.gerlach@linux.intel.com>
16 - altr,msi-1.0
20 - description: CSR registers
21 - description: Vectors slave port region
23 reg-names:
[all …]
H A Dal,alpine-msix.txt1 Alpine MSIX controller
3 See arm,gic-v3.txt for SPI and MSI definitions.
7 - compatible: should be "al,alpine-msix"
8 - reg: physical base address and size of the registers
9 - interrupt-controller: identifies the node as an interrupt controller
10 - msi-controller: identifies the node as an PCI Message Signaled Interrupt
11 controller
12 - al,msi-base-spi: SPI base of the MSI frame
13 - al,msi-num-spis: number of SPIs assigned to the MSI frame, relative to SPI0
18 compatible = "al,alpine-msix";
[all …]
H A Darm,gic.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM Generic Interrupt Controller v1 and v2
10 - Marc Zyngier <marc.zyngier@arm.com>
18 Secondary GICs are cascaded into the upward interrupt controller and do not
22 - $ref: /schemas/interrupt-controller.yaml#
27 - items:
28 - enum:
[all …]
/freebsd/sys/contrib/device-tree/Bindings/bus/
H A Dfsl,imx8qxp-pixel-link-msi-bus.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX8qxp Pixel Link Medium Speed Interconnect (MSI) Bus
10 - Liu Ying <victor.liu@nxp.com>
13 i.MX8qxp pixel link MSI bus is used to control settings of PHYs, I/Os
14 sitting together with the PHYs. It is not the same as the MSI bus coming
15 from i.MX8 System Controller Unit (SCU) which is used to control power,
16 clock and reset through the i.MX8 Distributed Slave System Controller (DSC).
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/marvell/
H A Darmada-ap80x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/thermal.h>
11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cells = <2>;
25 compatible = "arm,psci-0.2";
29 reserved-memory {
30 #address-cells = <2>;
31 #size-cells = <2>;
[all …]

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