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/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dloongson,pch-msi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/loongson,pch-msi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Loongson PCH MSI Controller
10 - Jiaxun Yang <jiaxun.yang@flygoat.com>
14 transforming interrupts from PCIe MSI into HyperTransport vectorized
19 const: loongson,pch-msi-1.0
24 loongson,msi-base-vec:
26 u32 value of the base of parent HyperTransport vector allocated
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/linux/drivers/irqchip/
H A Dirq-riscv-imsic-platform.c1 // SPDX-License-Identifier: GPL-2.0
7 #define pr_fmt(fmt) "riscv-imsic: " fmt
17 #include <linux/msi.h>
23 #include <linux/irqchip/irq-msi-lib.h>
24 #include "irq-riscv-imsic-state.h"
32 global = &imsic->global; in imsic_cpu_page_phys()
33 local = per_cpu_ptr(global->local, cpu); in imsic_cpu_page_phys()
35 if (BIT(global->guest_index_bits) <= guest_index) in imsic_cpu_page_phys()
39 *out_msi_pa = local->msi_pa + (guest_index * IMSIC_MMIO_PAGE_SZ); in imsic_cpu_page_phys()
56 struct imsic_vector *vec = irq_data_get_irq_chip_data(d); in imsic_irq_retrigger() local
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H A Dirq-loongson-pch-msi.c1 // SPDX-License-Identifier: GPL-2.0
4 * Loongson PCH MSI support
7 #define pr_fmt(fmt) "pch-msi: " fmt
10 #include <linux/msi.h>
18 #include <linux/irqchip/irq-msi-lib.h>
19 #include "irq-loongson.h"
37 mutex_lock(&priv->msi_map_lock); in pch_msi_allocate_hwirq()
39 first = bitmap_find_free_region(priv->msi_map, priv->num_irqs, in pch_msi_allocate_hwirq()
42 mutex_unlock(&priv->msi_map_lock); in pch_msi_allocate_hwirq()
43 return -ENOSPC; in pch_msi_allocate_hwirq()
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H A Dirq-sg2042-msi.c1 // SPDX-License-Identifier: GPL-2.0
3 * SG2042 MSI Controller
15 #include <linux/msi.h>
20 #include <linux/irqchip/irq-msi-lib.h>
28 * struct sg204x_msi_chipdata - chip data for the SG204x MSI IRQ controller
34 * @msi_map: mapping for allocated MSI vectors.
57 guard(mutex)(&data->msi_map_lock); in sg204x_msi_allocate_hwirq()
58 first = bitmap_find_free_region(data->msi_map, data->num_irqs, in sg204x_msi_allocate_hwirq()
60 return first >= 0 ? first : -ENOSPC; in sg204x_msi_allocate_hwirq()
65 guard(mutex)(&data->msi_map_lock); in sg204x_msi_free_hwirq()
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H A Dirq-riscv-imsic-state.c1 // SPDX-License-Identifier: GPL-2.0
7 #define pr_fmt(fmt) "riscv-imsic: " fmt
22 #include "irq-riscv-imsic-state.h"
63 return imsic ? &imsic->global : NULL; in imsic_get_global_config()
74 imask = BIT(id & (__riscv_xlen - 1)); in __imsic_eix_read_clear()
102 * are XLEN-wide and we must not touch IDs which in __imsic_eix_update()
106 for (i = id & (__riscv_xlen - 1); id < last_id && i < __riscv_xlen; i++) { in __imsic_eix_update()
130 struct imsic_vector *vec, *tvec, *mvec; in __imsic_local_sync() local
134 lockdep_assert_held(&lpriv->lock); in __imsic_local_sync()
136 for_each_set_bit(i, lpriv->dirty_bitmap, imsic->global.nr_ids + 1) { in __imsic_local_sync()
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/linux/arch/powerpc/sysdev/xics/
H A Dics-native.c1 // SPDX-License-Identifier: GPL-2.0-or-later
20 #include <linux/msi.h>
34 void __iomem *base; member
40 static void __iomem *ics_native_xive(struct ics_native *in, unsigned int vec) in ics_native_xive() argument
42 return in->base + 0x800 + ((vec - in->ibase) << 2); in ics_native_xive()
47 unsigned int vec = (unsigned int)irqd_to_hwirq(d); in ics_native_unmask_irq() local
52 pr_devel("ics-native: unmask virq %d [hw 0x%x]\n", d->irq, vec); in ics_native_unmask_irq()
54 if (vec < in->ibase || vec >= (in->ibase + in->icount)) in ics_native_unmask_irq()
57 server = xics_get_irq_server(d->irq, irq_data_get_affinity_mask(d), 0); in ics_native_unmask_irq()
58 out_be32(ics_native_xive(in, vec), (server << 8) | DEFAULT_PRIORITY); in ics_native_unmask_irq()
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/linux/arch/mips/boot/dts/loongson/
H A Dloongson64c_4core_ls7a.dts1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include "loongson64c-package.dtsi"
6 #include "ls7a-pch.dtsi"
9 compatible = "loongson,loongson64c-4core-ls7a";
13 htvec: interrupt-controller@efdfb000080 {
14 compatible = "loongson,htvec-1.0";
16 interrupt-controller;
17 #interrupt-cells = <1>;
19 interrupt-parent = <&liointc>;
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H A Dloongson64g_4core_ls7a.dts1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include "loongson64g-package.dtsi"
6 #include "ls7a-pch.dtsi"
9 compatible = "loongson,loongson64g-4core-ls7a";
13 htvec: interrupt-controller@efdfb000080 {
14 compatible = "loongson,htvec-1.0";
16 interrupt-controller;
17 #interrupt-cells = <1>;
19 interrupt-parent = <&liointc>;
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/linux/drivers/crypto/cavium/nitrox/
H A Dnitrox_isr.c1 // SPDX-License-Identifier: GPL-2.0
15 * - NPS packet ring, AQMQ ring and ZQMQ ring
19 /* base entry for packet ring/port */
24 * nps_pkt_slc_isr - IRQ handler for NPS solicit port
32 struct nitrox_cmdq *cmdq = qvec->cmdq; in nps_pkt_slc_isr()
34 slc_cnts.value = readq(cmdq->compl_cnt_csr_addr); in nps_pkt_slc_isr()
37 tasklet_hi_schedule(&qvec->resp_tasklet); in nps_pkt_slc_isr()
207 struct nitrox_device *ndev = qvec->ndev; in nps_core_int_tasklet()
210 if (ndev->mode == __NDEV_MODE_PF) { in nps_core_int_tasklet()
220 * nps_core_int_isr - interrupt handler for NITROX errors and
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/linux/drivers/net/ethernet/chelsio/cxgb4vf/
H A Dcxgb4vf_main.c2 * This file is part of the Chelsio T4 PCI-E SR-IOV Virtual Function Ethernet
5 * Copyright (c) 2009-2010 Chelsio Communications, Inc. All rights reserved.
17 * - Redistributions of source code must retain the above
21 * - Redistributions in binary form must reproduce the above
42 #include <linux/dma-mapping.h>
74 * order MSI-X then MSI. This parameter determines which of these schemes the
77 * msi = 2: choose from among MSI-X and MSI
78 * msi = 1: only consider MSI interrupts
82 * the PCI-E SR-IOV standard).
88 static int msi = MSI_DEFAULT; variable
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H A Dadapter.h2 * This file is part of the Chelsio T4 PCI-E SR-IOV Virtual Function Ethernet
5 * Copyright (c) 2009-2010 Chelsio Communications, Inc. All rights reserved.
17 * - Redistributions of source code must retain the above
21 * - Redistributions in binary form must reproduce the above
62 * MSI-X interrupt index usage.
64 MSIX_FW = 0, /* MSI-X index for firmware Q */
65 MSIX_IQFLINT = 1, /* MSI-X index base for Ingress Qs */
90 * Per-"port" information. This is really per-Virtual Interface information
118 * absolute Queue ID base of the section of the Queue ID space allocated to
123 * SGE free-list queue state.
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/linux/arch/loongarch/boot/dts/
H A Dloongson-2k2000.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/clock/loongson,ls2k-clk.h>
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <1>;
17 #size-cells = <0>;
34 ref_100m: clock-ref-100m {
35 compatible = "fixed-clock";
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/linux/drivers/i2c/busses/
H A Di2c-ismt.c65 #include <linux/dma-mapping.h>
70 #include <linux/io-64-nonatomic-lo-hi.h>
87 /* Hardware Descriptor Constants - Control Field */
96 /* Hardware Descriptor Constants - Status Field */
117 #define ISMT_MSTR_MDBA 0x100 /* Master Descriptor Base Address */
153 /* MSI Control Register (MSICTL) bit definitions */
154 #define ISMT_MSICTL_MSIE 0x01 /* MSI Enable */
174 struct ismt_desc *hw; /* descriptor virt base addr */
175 dma_addr_t io_rng_dma; /* descriptor HW base addr */
195 /* Bus speed control bits for slow debuggers - refer to the docs for usage */
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/linux/drivers/ntb/hw/amd/
H A Dntb_hw_amd.c8 * Copyright (C) 2016 T-Platforms. All Rights Reserved.
17 * Copyright (C) 2016 T-Platforms. All Rights Reserved.
65 #define NTB_DESC "AMD(R) PCI-E Non-Transparent Bridge Driver"
78 if (idx < 0 || idx > ndev->mw_count) in ndev_mw_to_bar()
79 return -EINVAL; in ndev_mw_to_bar()
81 return ndev->dev_data->mw_idx << idx; in ndev_mw_to_bar()
87 return -EINVAL; in amd_ntb_mw_count()
89 return ntb_ndev(ntb)->mw_count; in amd_ntb_mw_count()
101 return -EINVAL; in amd_ntb_mw_get_align()
114 *size_max = pci_resource_len(ndev->ntb.pdev, bar); in amd_ntb_mw_get_align()
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/linux/drivers/net/ethernet/chelsio/cxgb3/
H A Dcxgb3_main.c2 * Copyright (c) 2003-2008 Chelsio, Inc. All rights reserved.
14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
38 #include <linux/dma-mapping.h>
77 #define PORT_MASK ((1 << MAX_NPORTS) - 1)
99 CH_DEVICE(0x35, 6), /* T3C20-derived T3C10 */
100 CH_DEVICE(0x36, 3), /* S320E-CR */
101 CH_DEVICE(0x37, 7), /* N320E-G2 */
117 * order MSI-X, MSI, legacy pin interrupts. This parameter determines which
120 * msi = 2: choose from among all three options
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/linux/drivers/ntb/hw/intel/
H A Dntb_hw_gen1.c9 * Copyright (C) 2016 T-Platforms. All Rights Reserved.
19 * Copyright (C) 2016 T-Platforms. All Rights Reserved.
66 #define NTB_DESC "Intel(R) PCI-E Non-Transparent Bridge Driver"
74 #define bar0_off(base, bar) ((base) + ((bar) << 2)) argument
75 #define bar2_off(base, bar) bar0_off(base, (bar) - 2) argument
88 static int b2b_mw_idx = -1;
105 "XEON B2B USD BAR 2 64-bit address");
110 "XEON B2B USD BAR 4 64-bit address");
115 "XEON B2B USD split-BAR 4 32-bit address");
120 "XEON B2B USD split-BAR 5 32-bit address");
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/linux/arch/alpha/kernel/
H A Dsys_marvel.c1 // SPDX-License-Identifier: GPL-2.0
52 * -----+-----+--------+--- in io7_device_interrupt()
57 * 0x0800 - 0x0ff0 - 0x0800 + (LSI id << 4) in io7_device_interrupt()
58 * 0x1000 - 0x2ff0 - 0x1000 + (MSI_DAT<8:0> << 4) in io7_device_interrupt()
61 irq = ((vector & 0xffff) - 0x800) >> 4; in io7_device_interrupt()
81 "%s for nonexistent io7 -- vec %x, pid %d\n", in io7_get_irq_ctl()
87 irq -= 16; /* subtract legacy bias */ in io7_get_irq_ctl()
91 "%s for invalid irq -- pid %d adjusted irq %x\n", in io7_get_irq_ctl()
96 ctl = &io7->csrs->PO7_LSI_CTL[irq & 0xff].csr; /* assume LSI */ in io7_get_irq_ctl()
97 if (irq >= 0x80) /* MSI */ in io7_get_irq_ctl()
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/linux/drivers/net/ethernet/chelsio/cxgb4/
H A Dcxgb4_main.c4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
109 /* Include PCI Device IDs for both PF4 and PF0-3 so our PCI probe() routine is
126 #define FW4_CFNAME "cxgb4/t4-config.txt"
127 #define FW5_CFNAME "cxgb4/t5-config.txt"
128 #define FW6_CFNAME "cxgb4/t6-config.txt"
144 * order MSI-X, MSI, legacy INTx interrupts. This parameter determines which
147 * msi = 2: choose from among all three options
148 * msi = 1: only consider MSI and INTx interrupts
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H A Dcxgb4.h4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
62 #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__)
138 FEC_RS = 1 << 1, /* Reed-Solomon */
139 FEC_BASER_RS = 1 << 2 /* BaseR/Reed-Solomon */
262 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */
263 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */
264 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */
265 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */
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H A Dt4_hw.c4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
43 * t4_wait_op_done_val - wait until an operation is completed
46 * @mask: a single-bit field within @reg that indicates completion
55 * operation completes and -EAGAIN otherwise.
68 if (--attempts == 0) in t4_wait_op_done_val()
69 return -EAGAIN; in t4_wait_op_done_val()
83 * t4_set_reg_field - set a register field to a value
102 * t4_read_indirect - read indirectly addressed registers
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/linux/drivers/net/ethernet/netronome/nfp/
H A Dnfp_net.h1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2 /* Copyright (C) 2015-2018 Netronome Systems, Inc. */
21 #include <linux/io-64-nonatomic-hi-lo.h>
32 if (__nn->dp.netdev) \
33 netdev_printk(lvl, __nn->dp.netdev, fmt, ## args); \
35 dev_printk(lvl, __nn->dp.dev, "ctrl: " fmt, ## args); \
48 if (__dp->netdev) \
49 netdev_warn(__dp->netdev, fmt, ## args); \
51 dev_warn(__dp->dev, fmt, ## args); \
118 #define D_IDX(ring, idx) ((idx) & ((ring)->cnt - 1))
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/linux/include/linux/
H A Dpci.h1 /* SPDX-License-Identifier: GPL-2.0 */
7 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
60 * The PCI interface treats multi-function devices as independent
68 * In the interest of not exposing interfaces to user-space unnecessarily,
69 * the following kernel-only defines are being added here.
80 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
86 return kobject_name(&slot->kobj); in pci_slot_name()
97 /* #0-5: standard PCI resources */
99 PCI_STD_RESOURCE_END = PCI_STD_RESOURCES + PCI_STD_NUM_BARS - 1,
104 /* Device-specific resources */
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/linux/drivers/net/ethernet/intel/i40e/
H A Di40e_main.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2013 - 2021 Intel Corporation. */
32 static const char i40e_copyright[] = "Copyright (c) 2013 - 2019 Intel Corporation.";
58 /* i40e_pci_tbl - PCI Device ID Table
98 static int debug = -1;
118 if (is_unicast_ether_addr(f->macaddr) || is_link_local_ether_addr(f->macaddr)) in netdev_hw_addr_refcnt()
119 ha_list = &netdev->uc; in netdev_hw_addr_refcnt()
121 ha_list = &netdev->mc; in netdev_hw_addr_refcnt()
124 if (ether_addr_equal(ha->addr, f->macaddr)) { in netdev_hw_addr_refcnt()
125 ha->refcount += delta; in netdev_hw_addr_refcnt()
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/linux/drivers/scsi/csiostor/
H A Dcsio_hw.c4 * Copyright (c) 2008-2012 Chelsio Communications, Inc. All rights reserved.
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
56 /* Default MSI param level */
64 {"T580-Dbg 10G", "Chelsio T580-Dbg 10G [FCoE]"},
65 {"T520-CR 10G", "Chelsio T520-CR 10G [FCoE]"},
66 {"T522-CR 10G/1G", "Chelsio T522-CR 10G/1G [FCoE]"},
67 {"T540-CR 10G", "Chelsio T540-CR 10G [FCoE]"},
68 {"T520-BCH 10G", "Chelsio T520-BCH 10G [FCoE]"},
69 {"T540-BCH 10G", "Chelsio T540-BCH 10G [FCoE]"},
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/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_sriov.c3 * Copyright 2009-2013 Broadcom Corporation
10 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
82 /* acking a VF sb through the PF - use the GRC */ in bnx2x_vf_igu_ack_sb()
86 u32 func_encode = vf->abs_vfid; in bnx2x_vf_igu_ack_sb()
132 "VF[%d] Q_SETUP: txq[%d]-- vfsb=%d, sb-index=%d, hc-rate=%d, flags=0x%lx, traffic-type=%d", in bnx2x_vfop_qctor_dump_tx()
133 vf->abs_vfid, in bnx2x_vfop_qctor_dump_tx()
136 init_params->tx.sb_cq_index, in bnx2x_vfop_qctor_dump_tx()
137 init_params->tx.hc_rate, in bnx2x_vfop_qctor_dump_tx()
138 setup_params->flags, in bnx2x_vfop_qctor_dump_tx()
139 setup_params->txq_params.traffic_type); in bnx2x_vfop_qctor_dump_tx()
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