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/linux/drivers/pci/controller/
H A Dpcie-iproc-msi.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/irqchip/irq-msi-lib.h>
10 #include <linux/msi.h>
15 #include "pcie-iproc.h"
19 #define IPROC_MSI_INT_N_EVENT_SHIFT 1
35 /* Size of each MSI address region */
53 * struct iproc_msi_grp - iProc MSI group
55 * One MSI group is allocated per GIC interrupt, serviced by one iProc MSI
58 * @msi: pointer to iProc MSI data
63 struct iproc_msi *msi; member
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H A Dpcie-altera-msi.c1 // SPDX-License-Identifier: GPL-2.0
3 * Altera PCIe MSI support
7 * Copyright Altera Corporation (C) 2013-2015. All rights reserved
12 #include <linux/irqchip/irq-msi-lib.h>
16 #include <linux/msi.h>
41 static inline void msi_writel(struct altera_msi *msi, const u32 value, in msi_writel() argument
44 writel_relaxed(value, msi->csr_base + reg); in msi_writel()
47 static inline u32 msi_readl(struct altera_msi *msi, const u32 reg) in msi_readl() argument
49 return readl_relaxed(msi->csr_base + reg); in msi_readl()
55 struct altera_msi *msi; in altera_msi_isr() local
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H A Dpcie-rcar-host.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe driver for Renesas R-Car SoCs
4 * Copyright (C) 2014-2020 Renesas Electronics Europe Ltd
7 * arch/sh/drivers/pci/pcie-sh7786.c
8 * arch/sh/drivers/pci/ops-sh7786.c
9 * Copyright (C) 2009 - 2011 Paul Mundt
17 #include <linux/clk-provider.h>
21 #include <linux/irqchip/irq-msi-lib.h>
26 #include <linux/msi.h>
36 #include "pcie-rcar.h"
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H A Dpci-xgene-msi.c1 // SPDX-License-Identifier: GPL-2.0+
3 * APM X-Gene MSI Driver
14 #include <linux/msi.h>
16 #include <linux/irqchip/irq-msi-lib.h>
49 * X-Gene v1 has 16 frames of MSI termination registers MSInIRx, where n is
54 * Each register supports 16 MSI vectors (0..15) to generate interrupts. A
60 * Additionally, each MSI termination frame has 1 MSIINTn register (n is
61 * 0..15) to indicate the MSI pending status caused by any of its 8
64 * extra 1MB).
66 * There is one GIC IRQ assigned for each MSI termination frame, 16 in
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H A Dpcie-brcmstb.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2009 - 2019 Broadcom */
15 #include <linux/irqchip/irq-msi-lib.h>
21 #include <linux/msi.h>
27 #include <linux/pci-ecam.h>
38 /* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */
171 #define BRCM_INT_PCI_MSI_MASK GENMASK(BRCM_INT_PCI_MSI_NR - 1, 0)
173 32 - BRCM_INT_PCI_MSI_LEGACY_NR)
175 /* MSI target addresses */
189 #define MDIO_RD_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 1 : 0)
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/linux/include/linux/
H A Dmsi.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 * This header file contains MSI data structures and functions which are
8 * - Interrupt core code
9 * - PCI/MSI core code
10 * - MSI interrupt domain implementations
11 * - IOMMU, low level VFIO, NTB and other justified exceptions
12 * dealing with low level MSI details.
15 * especially storing MSI descriptor pointers in random code is considered
26 #include <asm/msi.h>
52 * msi_msg - Representation of a MSI message
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/linux/arch/powerpc/sysdev/
H A Dfsl_msi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2007-2011 Freescale Semiconductor, Inc.
11 #include <linux/msi.h>
24 #include <asm/ppc-pci.h>
39 #define msi_hwirq(msi, msir_index, intr_index) \ argument
40 ((msir_index) << (msi)->srs_shift | \
41 ((intr_index) << (msi)->ibs_shift))
63 * in the cascade interrupt. So, this MSI interrupt has been acked
71 struct fsl_msi *msi_data = irqd->domain->host_data; in fsl_msi_print_chip()
75 srs = (hwirq >> msi_data->srs_shift) & MSI_SRS_MASK; in fsl_msi_print_chip()
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/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dmsi.txt1 This document describes the generic device tree binding for MSI controllers and
9 those busses to the MSI controllers which they are capable of using,
14 - The doorbell (the MMIO address written to).
17 they can address. An MSI controller may feature a number of doorbells.
19 - The payload (the value written to the doorbell).
22 MSI controllers may have restrictions on permitted payloads.
24 - Sideband information accompanying the write.
28 MSI controller and device rather than a property of either in isolation).
31 MSI controllers:
34 An MSI controller signals interrupts to a CPU when a write is made to an MMIO
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H A Dfsl,ls-msi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,ls-msi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale Layerscape SCFG PCIe MSI controller
11 is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
12 platforms. If interrupt-parent is not provided, the default parent interrupt
15 Each PCIe node needs to have property msi-parent that points to
16 MSI controller node
19 - Frank Li <Frank.Li@nxp.com>
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H A Dloongson,pch-msi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/loongson,pch-msi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Loongson PCH MSI Controller
10 - Jiaxun Yang <jiaxun.yang@flygoat.com>
14 transforming interrupts from PCIe MSI into HyperTransport vectorized
19 const: loongson,pch-msi-1.0
22 maxItems: 1
24 loongson,msi-base-vec:
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H A Darm,gic-v3.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <maz@kernel.org>
15 Software Generated Interrupts (SGI), and Locality-specific Peripheral
19 - $ref: /schemas/interrupt-controller.yaml#
24 - items:
25 - enum:
26 - qcom,msm8996-gic-v3
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H A Dfsl,mpic-msi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,mpic-msi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale MSI interrupt controller
10 The Freescale hypervisor and msi-address-64
11 -------------------------------------------
14 Freescale MSI driver calculates the address of MSIIR (in the MSI register
15 block) and sets that address as the MSI message address.
39 this. The address specified in the msi-address-64 property is the PCI
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H A Dsophgo,sg2042-msi.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/sophgo,sg2042-msi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Sophgo SG2042 MSI Controller
10 - Chen Wang <unicorn_wang@outlook.com>
14 PCIe MSI to PLIC interrupts.
17 - $ref: /schemas/interrupt-controller/msi-controller.yaml#
22 - sophgo,sg2042-msi
23 - sophgo,sg2044-msi
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/linux/drivers/pci/msi/
H A Dapi.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCI MSI/MSI-X — Exported APIs for device drivers
5 * Copyright (C) 2003-2004 Intel
14 #include "msi.h"
17 * pci_enable_msi() - Enable MSI interrupt mode on device
20 * Legacy device driver API to enable MSI interrupts mode on device and
22 * Linux IRQ will be saved at @dev->irq. The driver must invoke
32 int rc = __pci_enable_msi_range(dev, 1, 1, NULL); in pci_enable_msi()
40 * pci_disable_msi() - Disable MSI interrupt mode on device
43 * Legacy device driver API to disable MSI interrupt mode on device,
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H A Dmsi.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCI Message Signaled Interrupt (MSI)
5 * Copyright (C) 2003-2004 Intel
16 #include "msi.h"
21 * pci_msi_supported - check whether MSI may be enabled on a device
22 * @dev: pointer to the pci_dev data structure of MSI device function
26 * to determine if MSI/-X are supported for the device. If MSI/-X is
27 * supported return 1, else return 0.
33 /* MSI must be globally enabled and supported by the device */ in pci_msi_supported()
37 if (!dev || dev->no_msi) in pci_msi_supported()
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/linux/arch/mips/pci/
H A Dmsi-octeon.c6 * Copyright (C) 2005-2009, 2010 Cavium Networks
10 #include <linux/msi.h>
15 #include <asm/octeon/cvmx-npi-defs.h>
16 #include <asm/octeon/cvmx-pci-defs.h>
17 #include <asm/octeon/cvmx-npei-defs.h>
18 #include <asm/octeon/cvmx-sli-defs.h>
19 #include <asm/octeon/cvmx-pexp-defs.h>
20 #include <asm/octeon/pci-octeon.h>
23 * Each bit in msi_free_irq_bitmask represents a MSI interrupt that is
31 * is used so we can disable all of the MSI interrupts when a device
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/linux/drivers/pci/controller/mobiveil/
H A Dpcie-mobiveil-host.c1 // SPDX-License-Identifier: GPL-2.0
6 * Copyright 2019-2020 NXP
15 #include <linux/irqchip/irq-msi-lib.h>
20 #include <linux/msi.h>
26 #include "pcie-mobiveil.h"
38 if ((bus->primary == to_pci_host_bridge(bus->bridge)->busnr) && (PCI_SLOT(devfn) > 0)) in mobiveil_pcie_valid_device()
45 * mobiveil_pcie_map_bus - routine to get the configuration base of either
51 struct mobiveil_pcie *pcie = bus->sysdata; in mobiveil_pcie_map_bus()
52 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_pcie_map_bus()
60 return pcie->csr_axi_slave_base + where; in mobiveil_pcie_map_bus()
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/linux/Documentation/devicetree/bindings/pci/
H A Dpci-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/pci-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
13 - Kishon Vijay Abraham I <kishon@kernel.org>
14 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
18 pattern: "^pcie-ep@"
20 iommu-map:
21 $ref: /schemas/types.yaml#/definitions/uint32-matrix
24 - description: Device ID (see msi-map) base
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/linux/arch/arm64/kvm/vgic/
H A Dvgic-irqfd.c1 // SPDX-License-Identifier: GPL-2.0-only
22 unsigned int spi_id = e->irqchip.pin + VGIC_NR_PRIVATE_IRQS; in vgic_irqfd_set_irq()
25 return -EINVAL; in vgic_irqfd_set_irq()
36 * return 0 on success, -EINVAL on errors.
42 int r = -EINVAL; in kvm_set_routing_entry()
44 switch (ue->type) { in kvm_set_routing_entry()
46 e->set = vgic_irqfd_set_irq; in kvm_set_routing_entry()
47 e->irqchip.irqchip = ue->u.irqchip.irqchip; in kvm_set_routing_entry()
48 e->irqchip.pin = ue->u.irqchip.pin; in kvm_set_routing_entry()
49 if ((e->irqchip.pin >= KVM_IRQCHIP_NUM_PINS) || in kvm_set_routing_entry()
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/linux/kernel/irq/
H A Dmsi.c1 // SPDX-License-Identifier: GPL-2.0
14 #include <linux/msi.h>
26 * struct msi_device_data - MSI per device data
27 * @properties: MSI properties which are interesting to drivers
28 * @mutex: Mutex protecting the MSI descriptor store
29 * @__domains: Internal data for per device MSI domains
40 * struct msi_ctrl - MSI internal management control structure
45 * than the range due to PCI/multi-MSI.
55 #define MSI_XA_MAX_INDEX (ULONG_MAX - 1)
57 #define MSI_XA_DOMAIN_SIZE (MSI_MAX_INDEX + 1)
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/linux/Documentation/devicetree/bindings/misc/
H A Dfsl,qoriq-mc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/misc/fsl,qoriq-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
13 The Freescale Management Complex (fsl-mc) is a hardware resource
15 network-oriented packet processing applications. After the fsl-mc
22 For an overview of the DPAA2 architecture and fsl-mc bus see:
26 same hardware "isolation context" and a 10-bit value called an ICID
31 between ICIDs and IOMMUs, so an iommu-map property is used to define
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/linux/drivers/irqchip/
H A Dirq-msi-lib.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/irqchip/irq-msi-lib.h>
10 * msi_lib_init_dev_msi_info - Domain info setup for MSI domains
18 * This function is to be used for all types of MSI domains above the root
30 const struct msi_parent_ops *pops = real_parent->msi_parent_ops; in msi_lib_init_dev_msi_info()
31 struct irq_chip *chip = info->chip; in msi_lib_init_dev_msi_info()
39 * MSI parent domain specific settings. For now there is only the in msi_lib_init_dev_msi_info()
40 * root parent domain, e.g. NEXUS, acting as a MSI parent, but it is in msi_lib_init_dev_msi_info()
41 * possible to stack MSI parents. See x86 vector -> irq remapping in msi_lib_init_dev_msi_info()
43 if (domain->bus_token == pops->bus_select_token) { in msi_lib_init_dev_msi_info()
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/linux/arch/s390/pci/
H A Dpci_irq.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/msi.h>
20 * FLOATING - summary bit per function
21 * DIRECTED - summary bit per cpu (only used in fallback path)
27 * FLOATING - interrupt bit vector per function
28 * DIRECTED - interrupt bit vector per cpu
35 u64 req = ZPCI_CREATE_REQ(zdev->fh, 0, ZPCI_MOD_FC_REG_INT); in zpci_set_airq()
40 fib.fmt0.sum = 1; /* enable summary notifications */ in zpci_set_airq()
41 fib.fmt0.noi = airq_iv_end(zdev->aibv); in zpci_set_airq()
42 fib.fmt0.aibv = virt_to_phys(zdev->aibv->vector); in zpci_set_airq()
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/linux/arch/riscv/kvm/
H A Dvm.c1 // SPDX-License-Identifier: GPL-2.0
63 return -ENXIO; in kvm_vm_ioctl_irq_line()
65 return kvm_riscv_aia_inject_irq(kvm, irql->irq, irql->level); in kvm_vm_ioctl_irq_line()
72 struct kvm_msi msi; in kvm_set_msi() local
75 return -1; in kvm_set_msi()
77 msi.address_lo = e->msi.address_lo; in kvm_set_msi()
78 msi.address_hi = e->msi.address_hi; in kvm_set_msi()
79 msi.data = e->msi.data; in kvm_set_msi()
80 msi.flags = e->msi.flags; in kvm_set_msi()
81 msi.devid = e->msi.devid; in kvm_set_msi()
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/linux/drivers/ntb/
H A Dmsi.c1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
6 #include <linux/msi.h>
19 * ntb_msi_init() - Initialize the MSI context
23 * It initializes the context for MSI operations and maps
43 return -EINVAL; in ntb_msi_init()
45 ntb->msi = devm_kzalloc(&ntb->dev, struct_size(ntb->msi, peer_mws, peers), in ntb_msi_init()
47 if (!ntb->msi) in ntb_msi_init()
48 return -ENOMEM; in ntb_msi_init()
50 ntb->msi->desc_changed = desc_changed; in ntb_msi_init()
53 peer_widx = ntb_peer_mw_count(ntb) - 1 - i; in ntb_msi_init()
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