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/linux/Documentation/devicetree/bindings/pci/
H A Dpci-msi.txt2 relationship between PCI devices and MSI controllers.
18 Requester ID. A mechanism is required to associate a device with both the MSI
22 For generic MSI bindings, see
23 Documentation/devicetree/bindings/interrupt-controller/msi.txt.
30 -------------------
32 - msi-map: Maps a Requester ID to an MSI controller and associated
33 msi-specifier data. The property is an arbitrary number of tuples of
34 (rid-base,msi-controller,msi-base,length), where:
36 * rid-base is a single cell describing the first RID matched by the entry.
38 * msi-controller is a single phandle to an MSI controller
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H A Dxgene-pci-msi.txt1 * AppliedMicro X-Gene v1 PCIe MSI controller
5 - compatible: should be "apm,xgene1-msi" to identify
6 X-Gene v1 PCIe MSI controller block.
7 - msi-controller: indicates that this is an X-Gene v1 PCIe MSI controller node
8 - reg: physical base address (0x79000000) and length (0x900000) for controller
9 registers. These registers include the MSI termination address and data
10 registers as well as the MSI interrupt status registers.
11 - reg-names: not required
12 - interrupts: A list of 16 interrupt outputs of the controller, starting from
14 - interrupt-names: not required
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/linux/drivers/pci/controller/
H A Dpcie-iproc-msi.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/msi.h>
14 #include "pcie-iproc.h"
18 #define IPROC_MSI_INT_N_EVENT_SHIFT 1
34 /* Size of each MSI address region */
52 * struct iproc_msi_grp - iProc MSI group
54 * One MSI group is allocated per GIC interrupt, serviced by one iProc MSI
57 * @msi: pointer to iProc MSI data
62 struct iproc_msi *msi; member
68 * struct iproc_msi - iProc event queue based MSI
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/linux/include/linux/
H A Dmsi.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 * This header file contains MSI data structures and functions which are
8 * - Interrupt core code
9 * - PCI/MSI core code
10 * - MSI interrupt domain implementations
11 * - IOMMU, low level VFIO, NTB and other justified exceptions
12 * dealing with low level MSI details.
15 * especially storing MSI descriptor pointers in random code is considered
26 #include <asm/msi.h>
52 * msi_msg - Representation of a MSI message
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/linux/arch/powerpc/sysdev/
H A Dfsl_msi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2007-2011 Freescale Semiconductor, Inc.
11 #include <linux/msi.h>
24 #include <asm/ppc-pci.h>
39 #define msi_hwirq(msi, msir_index, intr_index) \ argument
40 ((msir_index) << (msi)->srs_shift | \
41 ((intr_index) << (msi)->ibs_shift))
63 * in the cascade interrupt. So, this MSI interrupt has been acked
71 struct fsl_msi *msi_data = irqd->domain->host_data; in fsl_msi_print_chip()
75 srs = (hwirq >> msi_data->srs_shift) & MSI_SRS_MASK; in fsl_msi_print_chip()
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/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dmsi.txt1 This document describes the generic device tree binding for MSI controllers and
9 those busses to the MSI controllers which they are capable of using,
14 - The doorbell (the MMIO address written to).
17 they can address. An MSI controller may feature a number of doorbells.
19 - The payload (the value written to the doorbell).
22 MSI controllers may have restrictions on permitted payloads.
24 - Sideband information accompanying the write.
28 MSI controller and device rather than a property of either in isolation).
31 MSI controllers:
34 An MSI controller signals interrupts to a CPU when a write is made to an MMIO
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H A Dfsl,ls-msi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,ls-msi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale Layerscape SCFG PCIe MSI controller
11 is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
12 platforms. If interrupt-parent is not provided, the default parent interrupt
15 Each PCIe node needs to have property msi-parent that points to
16 MSI controller node
19 - Frank Li <Frank.Li@nxp.com>
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H A Dloongson,pch-msi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/loongson,pch-msi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Loongson PCH MSI Controller
10 - Jiaxun Yang <jiaxun.yang@flygoat.com>
14 transforming interrupts from PCIe MSI into HyperTransport vectorized
19 const: loongson,pch-msi-1.0
22 maxItems: 1
24 loongson,msi-base-vec:
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H A Darm,gic-v3.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <maz@kernel.org>
15 Software Generated Interrupts (SGI), and Locality-specific Peripheral
19 - $ref: /schemas/interrupt-controller.yaml#
24 - items:
25 - enum:
26 - qcom,msm8996-gic-v3
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H A Driscv,imsics.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,imsics.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V Incoming MSI Controller (IMSIC)
10 - Anup Patel <anup@brainfault.org>
13 The RISC-V advanced interrupt architecture (AIA) defines a per-CPU incoming
14 MSI controller (IMSIC) for handling MSIs in a RISC-V platform. The RISC-V
15 AIA specification can be found at https://github.com/riscv/riscv-aia.
17 The IMSIC is a per-CPU (or per-HART) device with separate interrupt file
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H A Darm,gic.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
22 - $ref: /schemas/interrupt-controller.yaml#
27 - items:
28 - enum:
29 - arm,arm11mp-gic
30 - arm,cortex-a15-gic
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H A Dmsi-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/msi-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MSI controller
10 - Marc Zyngier <maz@kernel.org>
13 An MSI controller signals interrupts to a CPU when a write is made
14 to an MMIO address by some master. An MSI controller may feature a
18 "#msi-cells":
20 The number of cells in an msi-specifier, required if not zero.
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/linux/arch/mips/pci/
H A Dmsi-octeon.c6 * Copyright (C) 2005-2009, 2010 Cavium Networks
10 #include <linux/msi.h>
15 #include <asm/octeon/cvmx-npi-defs.h>
16 #include <asm/octeon/cvmx-pci-defs.h>
17 #include <asm/octeon/cvmx-npei-defs.h>
18 #include <asm/octeon/cvmx-sli-defs.h>
19 #include <asm/octeon/cvmx-pexp-defs.h>
20 #include <asm/octeon/pci-octeon.h>
23 * Each bit in msi_free_irq_bitmask represents a MSI interrupt that is
31 * is used so we can disable all of the MSI interrupts when a device
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/linux/drivers/pci/controller/mobiveil/
H A Dpcie-mobiveil-host.c1 // SPDX-License-Identifier: GPL-2.0
6 * Copyright 2019-2020 NXP
19 #include <linux/msi.h>
25 #include "pcie-mobiveil.h"
37 if ((bus->primary == to_pci_host_bridge(bus->bridge)->busnr) && (PCI_SLOT(devfn) > 0)) in mobiveil_pcie_valid_device()
44 * mobiveil_pcie_map_bus - routine to get the configuration base of either
50 struct mobiveil_pcie *pcie = bus->sysdata; in mobiveil_pcie_map_bus()
51 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_pcie_map_bus()
59 return pcie->csr_axi_slave_base + where; in mobiveil_pcie_map_bus()
67 value = bus->number << PAB_BUS_SHIFT | in mobiveil_pcie_map_bus()
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/linux/arch/arm64/kvm/vgic/
H A Dvgic-irqfd.c1 // SPDX-License-Identifier: GPL-2.0-only
22 unsigned int spi_id = e->irqchip.pin + VGIC_NR_PRIVATE_IRQS; in vgic_irqfd_set_irq()
25 return -EINVAL; in vgic_irqfd_set_irq()
36 * return 0 on success, -EINVAL on errors.
42 int r = -EINVAL; in kvm_set_routing_entry()
44 switch (ue->type) { in kvm_set_routing_entry()
46 e->set = vgic_irqfd_set_irq; in kvm_set_routing_entry()
47 e->irqchip.irqchip = ue->u.irqchip.irqchip; in kvm_set_routing_entry()
48 e->irqchip.pin = ue->u.irqchip.pin; in kvm_set_routing_entry()
49 if ((e->irqchip.pin >= KVM_IRQCHIP_NUM_PINS) || in kvm_set_routing_entry()
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/linux/kernel/irq/
H A Dmsi.c1 // SPDX-License-Identifier: GPL-2.0
14 #include <linux/msi.h>
25 * struct msi_device_data - MSI per device data
26 * @properties: MSI properties which are interesting to drivers
27 * @mutex: Mutex protecting the MSI descriptor store
28 * @__domains: Internal data for per device MSI domains
39 * struct msi_ctrl - MSI internal management control structure
44 * than the range due to PCI/multi-MSI.
54 #define MSI_XA_MAX_INDEX (ULONG_MAX - 1)
56 #define MSI_XA_DOMAIN_SIZE (MSI_MAX_INDEX + 1)
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/linux/drivers/pci/msi/
H A Dmsi.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCI Message Signaled Interrupt (MSI)
5 * Copyright (C) 2003-2004 Intel
15 #include "msi.h"
17 int pci_msi_enable = 1;
21 * pci_msi_supported - check whether MSI may be enabled on a device
22 * @dev: pointer to the pci_dev data structure of MSI device function
26 * to determine if MSI/-X are supported for the device. If MSI/-X is
27 * supported return 1, else return 0.
33 /* MSI must be globally enabled and supported by the device */ in pci_msi_supported()
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/linux/Documentation/PCI/endpoint/
H A Dpci-test-howto.rst1 .. SPDX-License-Identifier: GPL-2.0
9 This document is a guide to help users use pci-epf-test function driver
17 ---------------------------
31 -------------------------
35 # ls /sys/bus/pci-epf/drivers
44 Creating pci-epf-test Device
45 ----------------------------
48 pci-epf-test device, the following commands can be used::
50 # mount -t configfs none /sys/kernel/config
54 The "mkdir func1" above creates the pci-epf-test function device that will
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/linux/drivers/irqchip/
H A Dirq-msi-lib.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include "irq-msi-lib.h"
10 * msi_lib_init_dev_msi_info - Domain info setup for MSI domains
18 * This function is to be used for all types of MSI domains above the root
30 const struct msi_parent_ops *pops = real_parent->msi_parent_ops; in msi_lib_init_dev_msi_info()
38 * MSI parent domain specific settings. For now there is only the in msi_lib_init_dev_msi_info()
39 * root parent domain, e.g. NEXUS, acting as a MSI parent, but it is in msi_lib_init_dev_msi_info()
40 * possible to stack MSI parents. See x86 vector -> irq remapping in msi_lib_init_dev_msi_info()
42 if (domain->bus_token == pops->bus_select_token) { in msi_lib_init_dev_msi_info()
46 WARN_ON_ONCE(1); in msi_lib_init_dev_msi_info()
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/linux/Documentation/devicetree/bindings/misc/
H A Dfsl,qoriq-mc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/misc/fsl,qoriq-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
13 The Freescale Management Complex (fsl-mc) is a hardware resource
15 network-oriented packet processing applications. After the fsl-mc
22 For an overview of the DPAA2 architecture and fsl-mc bus see:
26 same hardware "isolation context" and a 10-bit value called an ICID
31 between ICIDs and IOMMUs, so an iommu-map property is used to define
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/linux/arch/s390/pci/
H A Dpci_irq.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/msi.h>
20 * FLOATING - summary bit per function
21 * DIRECTED - summary bit per cpu (only used in fallback path)
27 * FLOATING - interrupt bit vector per function
28 * DIRECTED - interrupt bit vector per cpu
35 u64 req = ZPCI_CREATE_REQ(zdev->fh, 0, ZPCI_MOD_FC_REG_INT); in zpci_set_airq()
40 fib.fmt0.sum = 1; /* enable summary notifications */ in zpci_set_airq()
41 fib.fmt0.noi = airq_iv_end(zdev->aibv); in zpci_set_airq()
42 fib.fmt0.aibv = virt_to_phys(zdev->aibv->vector); in zpci_set_airq()
[all …]
/linux/Documentation/devicetree/bindings/bus/
H A Dfsl,imx8qxp-pixel-link-msi-bus.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX8qxp Pixel Link Medium Speed Interconnect (MSI) Bus
10 - Liu Ying <victor.liu@nxp.com>
13 i.MX8qxp pixel link MSI bus is used to control settings of PHYs, I/Os
14 sitting together with the PHYs. It is not the same as the MSI bus coming
18 i.MX8qxp pixel link MSI bus is a simple memory-mapped bus. Two input clocks,
19 that is, MSI clock and AHB clock, need to be enabled so that peripherals
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/linux/arch/riscv/kvm/
H A Dvm.c1 // SPDX-License-Identifier: GPL-2.0
62 return -ENXIO; in kvm_vm_ioctl_irq_line()
64 return kvm_riscv_aia_inject_irq(kvm, irql->irq, irql->level); in kvm_vm_ioctl_irq_line()
71 struct kvm_msi msi; in kvm_set_msi() local
74 return -1; in kvm_set_msi()
76 msi.address_lo = e->msi.address_lo; in kvm_set_msi()
77 msi.address_hi = e->msi.address_hi; in kvm_set_msi()
78 msi.data = e->msi.data; in kvm_set_msi()
79 msi.flags = e->msi.flags; in kvm_set_msi()
80 msi.devid = e->msi.devid; in kvm_set_msi()
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/linux/drivers/ntb/
H A Dmsi.c1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
6 #include <linux/msi.h>
19 * ntb_msi_init() - Initialize the MSI context
23 * It initializes the context for MSI operations and maps
43 return -EINVAL; in ntb_msi_init()
45 ntb->msi = devm_kzalloc(&ntb->dev, struct_size(ntb->msi, peer_mws, peers), in ntb_msi_init()
47 if (!ntb->msi) in ntb_msi_init()
48 return -ENOMEM; in ntb_msi_init()
50 ntb->msi->desc_changed = desc_changed; in ntb_msi_init()
53 peer_widx = ntb_peer_mw_count(ntb) - 1 - i; in ntb_msi_init()
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/linux/drivers/pci/controller/plda/
H A Dpcie-plda-host.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/msi.h>
15 #include <linux/pci-ecam.h>
17 #include "pcie-plda.h"
22 struct plda_pcie_rp *pcie = bus->sysdata; in plda_pcie_map_bus()
24 return pcie->config_base + PCIE_ECAM_OFFSET(bus->number, devfn, where); in plda_pcie_map_bus()
32 struct device *dev = port->dev; in plda_handle_msi()
33 struct plda_msi *msi = &port->msi; in plda_handle_msi() local
34 void __iomem *bridge_base_addr = port->bridge_addr; in plda_handle_msi()
46 for_each_set_bit(bit, &status, msi->num_vectors) { in plda_handle_msi()
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