6  * Copyright (C) 2005-2009, 2010 Cavium Networks
10 #include <linux/msi.h>
15 #include <asm/octeon/cvmx-npi-defs.h>
16 #include <asm/octeon/cvmx-pci-defs.h>
17 #include <asm/octeon/cvmx-npei-defs.h>
18 #include <asm/octeon/cvmx-sli-defs.h>
19 #include <asm/octeon/cvmx-pexp-defs.h>
20 #include <asm/octeon/pci-octeon.h>
23  * Each bit in msi_free_irq_bitmask represents a MSI interrupt that is
31  * is used so we can disable all of the MSI interrupts when a device
43  * Number of MSI IRQs used. This variable is set up in
49  * arch_setup_msi_irq() - setup MSI IRQs for a device
50  * @dev:    Device requesting MSI interrupts
51  * @desc:   MSI descriptor
53  * Called when a driver requests MSI interrupts instead of the
54  * legacy INT A-D. This routine will allocate multiple interrupts
55  * for MSI devices that support them. A device can override this by
56  * programming the MSI control bits [6:4] before calling
59  * Return: %0 on success, non-%0 on error.
72 	if (desc->pci.msi_attrib.is_msix)  in arch_setup_msi_irq()
73 		return -EINVAL;  in arch_setup_msi_irq()
76 	 * Read the MSI config to figure out how many IRQs this device  in arch_setup_msi_irq()
77 	 * wants.  Most devices only want 1, which will give  in arch_setup_msi_irq()
80 	pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);  in arch_setup_msi_irq()
91 		request_private_bits = (control & PCI_MSI_FLAGS_QMASK) >> 1;  in arch_setup_msi_irq()
113 	irq_step = 1 << request_private_bits;  in arch_setup_msi_irq()
116 	search_mask = (1 << irq_step) - 1;  in arch_setup_msi_irq()
120 	 * bits. This represents an MSI interrupt number that isn't in  in arch_setup_msi_irq()
128 				msi_multiple_irq_bitmask[index] |= (search_mask >> 1) << irq;  in arch_setup_msi_irq()
140 			       1 << request_private_bits);  in arch_setup_msi_irq()
144 			panic("arch_setup_msi_irq: Unable to find a free MSI interrupt");  in arch_setup_msi_irq()
147 	/* MSI interrupts start at logical IRQ OCTEON_IRQ_MSI_BIT0 */  in arch_setup_msi_irq()
177 	msg.data = irq - OCTEON_IRQ_MSI_BIT0;  in arch_setup_msi_irq()
182 	pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);  in arch_setup_msi_irq()
190  * arch_teardown_msi_irq() - release MSI IRQs for a device
193  * Called when a device no longer needs its MSI interrupts. All
194  * MSI interrupts for the device are freed.
206 		      "MSI interrupt (%d)", irq);  in arch_teardown_msi_irq()
208 	irq -= OCTEON_IRQ_MSI_BIT0;  in arch_teardown_msi_irq()
220 		& (1ull << (irq0 + number_irqs))))  in arch_teardown_msi_irq()
224 	bitmask = (1 << number_irqs) - 1;  in arch_teardown_msi_irq()
228 		panic("arch_teardown_msi_irq: Attempted to teardown MSI "  in arch_teardown_msi_irq()
247 	int msi_number = data->irq - OCTEON_IRQ_MSI_BIT0;  in octeon_irq_msi_enable_pcie()
253 	en |= 1ull << irq_bit;  in octeon_irq_msi_enable_pcie()
263 	int msi_number = data->irq - OCTEON_IRQ_MSI_BIT0;  in octeon_irq_msi_disable_pcie()
269 	en &= ~(1ull << irq_bit);  in octeon_irq_msi_disable_pcie()
276 	.name = "MSI",
284 	 * Octeon PCI doesn't have the ability to mask/unmask MSI  in octeon_irq_msi_enable_pci()
286 	 * in groups of 16, we simple assume MSI devices are well  in octeon_irq_msi_enable_pci()
287 	 * behaved. MSI interrupts are always enable and the ACK is  in octeon_irq_msi_enable_pci()
298 	.name = "MSI",
304  * Called by the interrupt handling code when an MSI interrupt
314 		bit--;  in __octeon_msi_do_interrupt()
316 		cvmx_write_csr(msi_rcv_reg[index], 1ull << bit);  in __octeon_msi_do_interrupt()
333  * Create octeon_msi_interrupt{0-3} function body
336 OCTEON_MSI_INT_HANDLER_X(1);
341  * Initializes the MSI interrupt handling code
346 	struct irq_chip *msi;  in octeon_msi_initialize()  local
352 		msi_rcv_reg[1] = CVMX_PEXP_NPEI_MSI_RCV1;  in octeon_msi_initialize()
356 		mis_ena_reg[1] = CVMX_PEXP_NPEI_MSI_ENB1;  in octeon_msi_initialize()
359 		msi = &octeon_irq_chip_msi_pcie;  in octeon_msi_initialize()
363 		msi_rcv_reg[1] = INVALID_GENERATE_ADE;  in octeon_msi_initialize()
367 		mis_ena_reg[1] = INVALID_GENERATE_ADE;  in octeon_msi_initialize()
370 		msi = &octeon_irq_chip_msi_pci;  in octeon_msi_initialize()
374 		irq_set_chip_and_handler(irq, msi, handle_simple_irq);  in octeon_msi_initialize()
378 				0, "MSI[0:63]", octeon_msi_interrupt0))  in octeon_msi_initialize()
382 				0, "MSI[64:127]", octeon_msi_interrupt1))  in octeon_msi_initialize()
386 				0, "MSI[127:191]", octeon_msi_interrupt2))  in octeon_msi_initialize()
390 				0, "MSI[192:255]", octeon_msi_interrupt3))  in octeon_msi_initialize()
396 				0, "MSI[0:15]", octeon_msi_interrupt0))  in octeon_msi_initialize()
400 				0, "MSI[16:31]", octeon_msi_interrupt0))  in octeon_msi_initialize()
404 				0, "MSI[32:47]", octeon_msi_interrupt0))  in octeon_msi_initialize()
408 				0, "MSI[48:63]", octeon_msi_interrupt0))  in octeon_msi_initialize()