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Searched +full:mpc5125 +full:- +full:gpio (Results 1 – 5 of 5) sorted by relevance

/linux/arch/powerpc/boot/dts/
H A Dmpc5125twr.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * STx/Freescale ADS5125 MPC5125 silicon
7 * Reworked by Matteo Facchinetti (engineering@sirius-es.it)
11 #include <dt-bindings/clock/mpc512x-clock.h>
13 /dts-v1/;
17 compatible = "fsl,mpc5125ads", "fsl,mpc5125";
18 #address-cells = <1>;
19 #size-cells = <1>;
20 interrupt-parent = <&ipic>;
29 #address-cells = <1>;
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/linux/Documentation/devicetree/bindings/gpio/
H A Dfsl,qoriq-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/fsl,qoriq-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale MPC512x/MPC8xxx/QorIQ/Layerscape GPIO controller
10 - Frank Li <Frank.Li@nxp.com>
15 - enum:
16 - fsl,mpc5121-gpio
17 - fsl,mpc5125-gpio
18 - fsl,mpc8349-gpio
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/linux/drivers/gpio/
H A Dgpio-mpc8xxx.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/gpio/driver.h>
49 * This hardware has a big endian bit assignment such that GPIO line 0 is
55 return BIT(31 - offset); in mpc_pin2mask()
58 /* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs
63 static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio) in mpc8572_gpio_get() argument
69 out_mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_DIR); in mpc8572_gpio_get()
70 val = gc->read_reg(mpc8xxx_gc->regs + GPIO_DAT) & ~out_mask; in mpc8572_gpio_get()
71 out_shadow = gc->bgpio_data & out_mask; in mpc8572_gpio_get()
73 return !!((val | out_shadow) & mpc_pin2mask(gpio)); in mpc8572_gpio_get()
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/linux/arch/powerpc/platforms/512x/
H A Dmpc512x_shared.c1 // SPDX-License-Identifier: GPL-2.0-or-later
17 #include <linux/fsl-diu-fb.h>
36 out_be32(&reset_module_base->rpr, 0x52535445); in mpc512x_restart()
38 out_be32(&reset_module_base->rcr, 0x2); in mpc512x_restart()
47 u8 gamma[0x300]; /* 32-bit aligned! */
48 struct diu_ad ad0; /* 32-bit aligned! */
63 np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-diu"); in mpc512x_set_pixel_clock()
71 clk_diu = clk_get_sys(np->name, "ipg"); in mpc512x_set_pixel_clock()
85 * determine the acceptable clock range for the monitor (+/- 5%), in mpc512x_set_pixel_clock()
88 pr_debug("DIU pixclock in ps - %u\n", pixclock); in mpc512x_set_pixel_clock()
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/linux/drivers/mtd/nand/raw/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
9 <http://www.linux-mtd.infradead.org/doc/nand.html>.
126 include NAND flash controllers with built-in hardware ECC
161 - PXA3xx processors (NFCv1)
162 - 32-bit Armada platforms (XP, 37x, 38x, 39x) (NFCv2)
163 - 64-bit Aramda platforms (7k, 8k, ac5) (NFCv2)
229 Controller Module with built-in hardware ECC capabilities.
240 with built-in hardware ECC capabilities.
250 processor localbus with User-Programmable Machine support.
253 tristate "Freescale VF610/MPC5125 NAND controller"
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