Lines Matching +full:mpc5125 +full:- +full:gpio
1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/gpio/driver.h>
49 * This hardware has a big endian bit assignment such that GPIO line 0 is
55 return BIT(31 - offset); in mpc_pin2mask()
58 /* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs
63 static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio) in mpc8572_gpio_get() argument
69 out_mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_DIR); in mpc8572_gpio_get()
70 val = gc->read_reg(mpc8xxx_gc->regs + GPIO_DAT) & ~out_mask; in mpc8572_gpio_get()
71 out_shadow = gc->bgpio_data & out_mask; in mpc8572_gpio_get()
73 return !!((val | out_shadow) & mpc_pin2mask(gpio)); in mpc8572_gpio_get()
77 unsigned int gpio, int val) in mpc5121_gpio_dir_out() argument
80 /* GPIO 28..31 are input only on MPC5121 */ in mpc5121_gpio_dir_out()
81 if (gpio >= 28) in mpc5121_gpio_dir_out()
82 return -EINVAL; in mpc5121_gpio_dir_out()
84 return mpc8xxx_gc->direction_output(gc, gpio, val); in mpc5121_gpio_dir_out()
88 unsigned int gpio, int val) in mpc5125_gpio_dir_out() argument
91 /* GPIO 0..3 are input only on MPC5125 */ in mpc5125_gpio_dir_out()
92 if (gpio <= 3) in mpc5125_gpio_dir_out()
93 return -EINVAL; in mpc5125_gpio_dir_out()
95 return mpc8xxx_gc->direction_output(gc, gpio, val); in mpc5125_gpio_dir_out()
102 if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS) in mpc8xxx_gpio_to_irq()
103 return irq_create_mapping(mpc8xxx_gc->irq, offset); in mpc8xxx_gpio_to_irq()
105 return -ENXIO; in mpc8xxx_gpio_to_irq()
111 struct gpio_chip *gc = &mpc8xxx_gc->gc; in mpc8xxx_gpio_irq_cascade()
115 mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_IER) in mpc8xxx_gpio_irq_cascade()
116 & gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR); in mpc8xxx_gpio_irq_cascade()
118 generic_handle_domain_irq(mpc8xxx_gc->irq, 31 - i); in mpc8xxx_gpio_irq_cascade()
126 struct gpio_chip *gc = &mpc8xxx_gc->gc; in mpc8xxx_irq_unmask()
129 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); in mpc8xxx_irq_unmask()
131 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, in mpc8xxx_irq_unmask()
132 gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR) in mpc8xxx_irq_unmask()
135 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); in mpc8xxx_irq_unmask()
141 struct gpio_chip *gc = &mpc8xxx_gc->gc; in mpc8xxx_irq_mask()
144 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); in mpc8xxx_irq_mask()
146 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, in mpc8xxx_irq_mask()
147 gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR) in mpc8xxx_irq_mask()
150 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); in mpc8xxx_irq_mask()
156 struct gpio_chip *gc = &mpc8xxx_gc->gc; in mpc8xxx_irq_ack()
158 gc->write_reg(mpc8xxx_gc->regs + GPIO_IER, in mpc8xxx_irq_ack()
165 struct gpio_chip *gc = &mpc8xxx_gc->gc; in mpc8xxx_irq_set_type()
171 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); in mpc8xxx_irq_set_type()
172 gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR, in mpc8xxx_irq_set_type()
173 gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR) in mpc8xxx_irq_set_type()
175 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); in mpc8xxx_irq_set_type()
179 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); in mpc8xxx_irq_set_type()
180 gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR, in mpc8xxx_irq_set_type()
181 gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR) in mpc8xxx_irq_set_type()
183 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); in mpc8xxx_irq_set_type()
187 return -EINVAL; in mpc8xxx_irq_set_type()
196 struct gpio_chip *gc = &mpc8xxx_gc->gc; in mpc512x_irq_set_type()
197 unsigned long gpio = irqd_to_hwirq(d); in mpc512x_irq_set_type() local
202 if (gpio < 16) { in mpc512x_irq_set_type()
203 reg = mpc8xxx_gc->regs + GPIO_ICR; in mpc512x_irq_set_type()
204 shift = (15 - gpio) * 2; in mpc512x_irq_set_type()
206 reg = mpc8xxx_gc->regs + GPIO_ICR2; in mpc512x_irq_set_type()
207 shift = (15 - (gpio % 16)) * 2; in mpc512x_irq_set_type()
213 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); in mpc512x_irq_set_type()
214 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift)) in mpc512x_irq_set_type()
216 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); in mpc512x_irq_set_type()
221 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); in mpc512x_irq_set_type()
222 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift)) in mpc512x_irq_set_type()
224 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); in mpc512x_irq_set_type()
228 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); in mpc512x_irq_set_type()
229 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))); in mpc512x_irq_set_type()
230 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); in mpc512x_irq_set_type()
234 return -EINVAL; in mpc512x_irq_set_type()
241 .name = "mpc8xxx-gpio",
252 irq_set_chip_data(irq, h->host_data); in mpc8xxx_gpio_irq_map()
288 { .compatible = "fsl,mpc8349-gpio", },
289 { .compatible = "fsl,mpc8572-gpio", .data = &mpc8572_gpio_devtype, },
290 { .compatible = "fsl,mpc8610-gpio", },
291 { .compatible = "fsl,mpc5121-gpio", .data = &mpc512x_gpio_devtype, },
292 { .compatible = "fsl,mpc5125-gpio", .data = &mpc5125_gpio_devtype, },
293 { .compatible = "fsl,pq3-gpio", },
294 { .compatible = "fsl,ls1028a-gpio", },
295 { .compatible = "fsl,ls1088a-gpio", },
296 { .compatible = "fsl,qoriq-gpio", },
304 struct device *dev = &pdev->dev; in mpc8xxx_probe()
311 return -ENOMEM; in mpc8xxx_probe()
315 raw_spin_lock_init(&mpc8xxx_gc->lock); in mpc8xxx_probe()
317 mpc8xxx_gc->regs = devm_platform_ioremap_resource(pdev, 0); in mpc8xxx_probe()
318 if (IS_ERR(mpc8xxx_gc->regs)) in mpc8xxx_probe()
319 return PTR_ERR(mpc8xxx_gc->regs); in mpc8xxx_probe()
321 gc = &mpc8xxx_gc->gc; in mpc8xxx_probe()
322 gc->parent = dev; in mpc8xxx_probe()
324 if (device_property_read_bool(dev, "little-endian")) { in mpc8xxx_probe()
325 ret = bgpio_init(gc, dev, 4, mpc8xxx_gc->regs + GPIO_DAT, in mpc8xxx_probe()
326 NULL, NULL, mpc8xxx_gc->regs + GPIO_DIR, in mpc8xxx_probe()
330 dev_dbg(dev, "GPIO registers are LITTLE endian\n"); in mpc8xxx_probe()
332 ret = bgpio_init(gc, dev, 4, mpc8xxx_gc->regs + GPIO_DAT, in mpc8xxx_probe()
333 NULL, NULL, mpc8xxx_gc->regs + GPIO_DIR, in mpc8xxx_probe()
338 dev_dbg(dev, "GPIO registers are BIG endian\n"); in mpc8xxx_probe()
341 mpc8xxx_gc->direction_output = gc->direction_output; in mpc8xxx_probe()
348 * It's assumed that only a single type of gpio controller is available in mpc8xxx_probe()
351 if (devtype->irq_set_type) in mpc8xxx_probe()
352 mpc8xxx_irq_chip.irq_set_type = devtype->irq_set_type; in mpc8xxx_probe()
354 if (devtype->gpio_dir_out) in mpc8xxx_probe()
355 gc->direction_output = devtype->gpio_dir_out; in mpc8xxx_probe()
356 if (devtype->gpio_get) in mpc8xxx_probe()
357 gc->get = devtype->gpio_get; in mpc8xxx_probe()
359 gc->to_irq = mpc8xxx_gpio_to_irq; in mpc8xxx_probe()
362 * The GPIO Input Buffer Enable register(GPIO_IBE) is used to control in mpc8xxx_probe()
363 * the input enable of each individual GPIO port. When an individual in mpc8xxx_probe()
364 * GPIO port’s direction is set to input (GPIO_GPDIR[DRn=0]), the in mpc8xxx_probe()
366 * the port value to the GPIO Data Register. in mpc8xxx_probe()
369 if (device_is_compatible(dev, "fsl,qoriq-gpio") || in mpc8xxx_probe()
370 device_is_compatible(dev, "fsl,ls1028a-gpio") || in mpc8xxx_probe()
371 device_is_compatible(dev, "fsl,ls1088a-gpio") || in mpc8xxx_probe()
373 gc->write_reg(mpc8xxx_gc->regs + GPIO_IBE, 0xffffffff); in mpc8xxx_probe()
375 gc->bgpio_data = gc->read_reg(mpc8xxx_gc->regs + GPIO_DAT) & in mpc8xxx_probe()
376 gc->read_reg(mpc8xxx_gc->regs + GPIO_DIR); in mpc8xxx_probe()
382 "GPIO chip registration failed with status %d\n", ret); in mpc8xxx_probe()
386 mpc8xxx_gc->irqn = platform_get_irq(pdev, 0); in mpc8xxx_probe()
387 if (mpc8xxx_gc->irqn < 0) in mpc8xxx_probe()
388 return mpc8xxx_gc->irqn; in mpc8xxx_probe()
390 mpc8xxx_gc->irq = irq_domain_create_linear(fwnode, in mpc8xxx_probe()
395 if (!mpc8xxx_gc->irq) in mpc8xxx_probe()
399 gc->write_reg(mpc8xxx_gc->regs + GPIO_IER, 0xffffffff); in mpc8xxx_probe()
400 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, 0); in mpc8xxx_probe()
402 ret = devm_request_irq(dev, mpc8xxx_gc->irqn, in mpc8xxx_probe()
404 IRQF_NO_THREAD | IRQF_SHARED, "gpio-cascade", in mpc8xxx_probe()
408 mpc8xxx_gc->irqn, ret); in mpc8xxx_probe()
416 irq_domain_remove(mpc8xxx_gc->irq); in mpc8xxx_probe()
424 if (mpc8xxx_gc->irq) { in mpc8xxx_remove()
425 irq_set_chained_handler_and_data(mpc8xxx_gc->irqn, NULL, NULL); in mpc8xxx_remove()
426 irq_domain_remove(mpc8xxx_gc->irq); in mpc8xxx_remove()
434 if (mpc8xxx_gc->irqn && device_may_wakeup(dev)) in mpc8xxx_suspend()
435 enable_irq_wake(mpc8xxx_gc->irqn); in mpc8xxx_suspend()
444 if (mpc8xxx_gc->irqn && device_may_wakeup(dev)) in mpc8xxx_resume()
445 disable_irq_wake(mpc8xxx_gc->irqn); in mpc8xxx_resume()
465 .name = "gpio-mpc8xxx",